drivers/net/ethernet/lantiq_etop.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify it
   3  *   under the terms of the GNU General Public License version 2 as published
   4  *   by the Free Software Foundation.
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/errno.h>
  21 #include <linux/types.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/in.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/phy.h>
  28 #include <linux/ip.h>
  29 #include <linux/tcp.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/mm.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/io.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/module.h>
  39
  40 #include <asm/checksum.h>
  41
  42 #include <lantiq_soc.h>
  43 #include <xway_dma.h>
  44 #include <lantiq_platform.h>
  45
  46 #define LTQ_ETOP_MDIO           0x11804
  47 #define MDIO_REQUEST            0x80000000
  48 #define MDIO_READ               0x40000000
  49 #define MDIO_ADDR_MASK          0x1f
  50 #define MDIO_ADDR_OFFSET        0x15
  51 #define MDIO_REG_MASK           0x1f
  52 #define MDIO_REG_OFFSET         0x10
  53 #define MDIO_VAL_MASK           0xffff
  54
  55 #define PPE32_CGEN              0x800
  56 #define LQ_PPE32_ENET_MAC_CFG   0x1840
  57
  58 #define LTQ_ETOP_ENETS0         0x11850
  59 #define LTQ_ETOP_MAC_DA0        0x1186C
  60 #define LTQ_ETOP_MAC_DA1        0x11870
  61 #define LTQ_ETOP_CFG            0x16020
  62 #define LTQ_ETOP_IGPLEN         0x16080
  63
  64 #define MAX_DMA_CHAN            0x8
  65 #define MAX_DMA_CRC_LEN         0x4
  66 #define MAX_DMA_DATA_LEN        0x600
  67
  68 #define ETOP_FTCU               BIT(28)
  69 #define ETOP_MII_MASK           0xf
  70 #define ETOP_MII_NORMAL         0xd
  71 #define ETOP_MII_REVERSE        0xe
  72 #define ETOP_PLEN_UNDER         0x40
  73 #define ETOP_CGEN               0x800
  74
  75 /* use 2 static channels for TX/RX */
  76 #define LTQ_ETOP_TX_CHANNEL     1
  77 #define LTQ_ETOP_RX_CHANNEL     6
  78 #define IS_TX(x)                (x == LTQ_ETOP_TX_CHANNEL)
  79 #define IS_RX(x)                (x == LTQ_ETOP_RX_CHANNEL)
  80
  81 #define ltq_etop_r32(x)         ltq_r32(ltq_etop_membase + (x))
  82 #define ltq_etop_w32(x, y)      ltq_w32(x, ltq_etop_membase + (y))
  83 #define ltq_etop_w32_mask(x, y, z)      \
  84                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
  85
  86 #define DRV_VERSION     "1.0"
  87
  88 static void __iomem *ltq_etop_membase;
  89
  90 struct ltq_etop_chan {
  91         int idx;
  92         int tx_free;
  93         struct net_device *netdev;
  94         struct napi_struct napi;
  95         struct ltq_dma_channel dma;
  96         struct sk_buff *skb[LTQ_DESC_NUM];
  97 };
  98
  99 struct ltq_etop_priv {
 100         struct net_device *netdev;
 101         struct platform_device *pdev;
 102         struct ltq_eth_data *pldata;
 103         struct resource *res;
 104
 105         struct mii_bus *mii_bus;
 106         struct phy_device *phydev;
 107
 108         struct ltq_etop_chan ch[MAX_DMA_CHAN];
 109         int tx_free[MAX_DMA_CHAN >> 1];
 110
 111         spinlock_t lock;
 112 };
 113
 114 static int
 115 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 116 {
 117         ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 118         if (!ch->skb[ch->dma.desc])
 119                 return -ENOMEM;
 120         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 121                 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
 122                 DMA_FROM_DEVICE);
 123         ch->dma.desc_base[ch->dma.desc].addr =
 124                 CPHYSADDR(ch->skb[ch->dma.desc]->data);
 125         ch->dma.desc_base[ch->dma.desc].ctl =
 126                 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
 127                 MAX_DMA_DATA_LEN;
 128         skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
 129         return 0;
 130 }
 131
 132 static void
 133 ltq_etop_hw_receive(struct ltq_etop_chan *ch)
 134 {
 135         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 136         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 137         struct sk_buff *skb = ch->skb[ch->dma.desc];
 138         int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&priv->lock, flags);
 142         if (ltq_etop_alloc_skb(ch)) {
 143                 netdev_err(ch->netdev,
 144                         "failed to allocate new rx buffer, stopping DMA\n");
 145                 ltq_dma_close(&ch->dma);
 146         }
 147         ch->dma.desc++;
 148         ch->dma.desc %= LTQ_DESC_NUM;
 149         spin_unlock_irqrestore(&priv->lock, flags);
 150
 151         skb_put(skb, len);
 152         skb->protocol = eth_type_trans(skb, ch->netdev);
 153         netif_receive_skb(skb);
 154 }
 155
 156 static int
 157 ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 158 {
 159         struct ltq_etop_chan *ch = container_of(napi,
 160                                 struct ltq_etop_chan, napi);
 161         int rx = 0;
 162         int complete = 0;
 163
 164         while ((rx < budget) && !complete) {
 165                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 166
 167                 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 168                         ltq_etop_hw_receive(ch);
 169                         rx++;
 170                 } else {
 171                         complete = 1;
 172                 }
 173         }
 174         if (complete || !rx) {
 175                 napi_complete(&ch->napi);
 176                 ltq_dma_ack_irq(&ch->dma);
 177         }
 178         return rx;
 179 }
 180
 181 static int
 182 ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 183 {
 184         struct ltq_etop_chan *ch =
 185                 container_of(napi, struct ltq_etop_chan, napi);
 186         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 187         struct netdev_queue *txq =
 188                 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&priv->lock, flags);
 192         while ((ch->dma.desc_base[ch->tx_free].ctl &
 193                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 194                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 195                 ch->skb[ch->tx_free] = NULL;
 196                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 197                         sizeof(struct ltq_dma_desc));
 198                 ch->tx_free++;
 199                 ch->tx_free %= LTQ_DESC_NUM;
 200         }
 201         spin_unlock_irqrestore(&priv->lock, flags);
 202
 203         if (netif_tx_queue_stopped(txq))
 204                 netif_tx_start_queue(txq);
 205         napi_complete(&ch->napi);
 206         ltq_dma_ack_irq(&ch->dma);
 207         return 1;
 208 }
 209
 210 static irqreturn_t
 211 ltq_etop_dma_irq(int irq, void *_priv)
 212 {
 213         struct ltq_etop_priv *priv = _priv;
 214         int ch = irq - LTQ_DMA_CH0_INT;
 215
 216         napi_schedule(&priv->ch[ch].napi);
 217         return IRQ_HANDLED;
 218 }
 219
 220 static void
 221 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 222 {
 223         struct ltq_etop_priv *priv = netdev_priv(dev);
 224
 225         ltq_dma_free(&ch->dma);
 226         if (ch->dma.irq)
 227                 free_irq(ch->dma.irq, priv);
 228         if (IS_RX(ch->idx)) {
 229                 int desc;
 230                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 231                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 232         }
 233 }
 234
 235 static void
 236 ltq_etop_hw_exit(struct net_device *dev)
 237 {
 238         struct ltq_etop_priv *priv = netdev_priv(dev);
 239         int i;
 240
 241         ltq_pmu_disable(PMU_PPE);
 242         for (i = 0; i < MAX_DMA_CHAN; i++)
 243                 if (IS_TX(i) || IS_RX(i))
 244                         ltq_etop_free_channel(dev, &priv->ch[i]);
 245 }
 246
 247 static int
 248 ltq_etop_hw_init(struct net_device *dev)
 249 {
 250         struct ltq_etop_priv *priv = netdev_priv(dev);
 251         int i;
 252
 253         ltq_pmu_enable(PMU_PPE);
 254
 255         switch (priv->pldata->mii_mode) {
 256         case PHY_INTERFACE_MODE_RMII:
 257                 ltq_etop_w32_mask(ETOP_MII_MASK,
 258                         ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 259                 break;
 260
 261         case PHY_INTERFACE_MODE_MII:
 262                 ltq_etop_w32_mask(ETOP_MII_MASK,
 263                         ETOP_MII_NORMAL, LTQ_ETOP_CFG);
 264                 break;
 265
 266         default:
 267                 netdev_err(dev, "unknown mii mode %d\n",
 268                         priv->pldata->mii_mode);
 269                 return -ENOTSUPP;
 270         }
 271
 272         /* enable crc generation */
 273         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 274
 275         ltq_dma_init_port(DMA_PORT_ETOP);
 276
 277         for (i = 0; i < MAX_DMA_CHAN; i++) {
 278                 int irq = LTQ_DMA_CH0_INT + i;
 279                 struct ltq_etop_chan *ch = &priv->ch[i];
 280
 281                 ch->idx = ch->dma.nr = i;
 282
 283                 if (IS_TX(i)) {
 284                         ltq_dma_alloc_tx(&ch->dma);
 285                         request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 286                 } else if (IS_RX(i)) {
 287                         ltq_dma_alloc_rx(&ch->dma);
 288                         for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 289                                         ch->dma.desc++)
 290                                 if (ltq_etop_alloc_skb(ch))
 291                                         return -ENOMEM;
 292                         ch->dma.desc = 0;
 293                         request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 294                 }
 295                 ch->dma.irq = irq;
 296         }
 297         return 0;
 298 }
 299
 300 static void
 301 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 302 {
 303         strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
 304         strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
 305         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 306 }
 307
 308 static int
 309 ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 310 {
 311         struct ltq_etop_priv *priv = netdev_priv(dev);
 312
 313         return phy_ethtool_gset(priv->phydev, cmd);
 314 }
 315
 316 static int
 317 ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 318 {
 319         struct ltq_etop_priv *priv = netdev_priv(dev);
 320
 321         return phy_ethtool_sset(priv->phydev, cmd);
 322 }
 323
 324 static int
 325 ltq_etop_nway_reset(struct net_device *dev)
 326 {
 327         struct ltq_etop_priv *priv = netdev_priv(dev);
 328
 329         return phy_start_aneg(priv->phydev);
 330 }
 331
 332 static const struct ethtool_ops ltq_etop_ethtool_ops = {
 333         .get_drvinfo = ltq_etop_get_drvinfo,
 334         .get_settings = ltq_etop_get_settings,
 335         .set_settings = ltq_etop_set_settings,
 336         .nway_reset = ltq_etop_nway_reset,
 337 };
 338
 339 static int
 340 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 341 {
 342         u32 val = MDIO_REQUEST |
 343                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 344                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 345                 phy_data;
 346
 347         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 348                 ;
 349         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 350         return 0;
 351 }
 352
 353 static int
 354 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
 355 {
 356         u32 val = MDIO_REQUEST | MDIO_READ |
 357                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 358                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 359
 360         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 361                 ;
 362         ltq_etop_w32(val, LTQ_ETOP_MDIO);
 363         while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 364                 ;
 365         val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 366         return val;
 367 }
 368
 369 static void
 370 ltq_etop_mdio_link(struct net_device *dev)
 371 {
 372         /* nothing to do  */
 373 }
 374
 375 static int
 376 ltq_etop_mdio_probe(struct net_device *dev)
 377 {
 378         struct ltq_etop_priv *priv = netdev_priv(dev);
 379         struct phy_device *phydev = NULL;
 380         int phy_addr;
 381
 382         for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 383                 if (priv->mii_bus->phy_map[phy_addr]) {
 384                         phydev = priv->mii_bus->phy_map[phy_addr];
 385                         break;
 386                 }
 387         }
 388
 389         if (!phydev) {
 390                 netdev_err(dev, "no PHY found\n");
 391                 return -ENODEV;
 392         }
 393
 394         phydev = phy_connect(dev, dev_name(&phydev->dev),
 395                              &ltq_etop_mdio_link, priv->pldata->mii_mode);
 396
 397         if (IS_ERR(phydev)) {
 398                 netdev_err(dev, "Could not attach to PHY\n");
 399                 return PTR_ERR(phydev);
 400         }
 401
 402         phydev->supported &= (SUPPORTED_10baseT_Half
 403                               | SUPPORTED_10baseT_Full
 404                               | SUPPORTED_100baseT_Half
 405                               | SUPPORTED_100baseT_Full
 406                               | SUPPORTED_Autoneg
 407                               | SUPPORTED_MII
 408                               | SUPPORTED_TP);
 409
 410         phydev->advertising = phydev->supported;
 411         priv->phydev = phydev;
 412         pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
 413                dev->name, phydev->drv->name,
 414                dev_name(&phydev->dev), phydev->irq);
 415
 416         return 0;
 417 }
 418
 419 static int
 420 ltq_etop_mdio_init(struct net_device *dev)
 421 {
 422         struct ltq_etop_priv *priv = netdev_priv(dev);
 423         int i;
 424         int err;
 425
 426         priv->mii_bus = mdiobus_alloc();
 427         if (!priv->mii_bus) {
 428                 netdev_err(dev, "failed to allocate mii bus\n");
 429                 err = -ENOMEM;
 430                 goto err_out;
 431         }
 432
 433         priv->mii_bus->priv = dev;
 434         priv->mii_bus->read = ltq_etop_mdio_rd;
 435         priv->mii_bus->write = ltq_etop_mdio_wr;
 436         priv->mii_bus->name = "ltq_mii";
 437         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 438                 priv->pdev->name, priv->pdev->id);
 439         priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 440         if (!priv->mii_bus->irq) {
 441                 err = -ENOMEM;
 442                 goto err_out_free_mdiobus;
 443         }
 444
 445         for (i = 0; i < PHY_MAX_ADDR; ++i)
 446                 priv->mii_bus->irq[i] = PHY_POLL;
 447
 448         if (mdiobus_register(priv->mii_bus)) {
 449                 err = -ENXIO;
 450                 goto err_out_free_mdio_irq;
 451         }
 452
 453         if (ltq_etop_mdio_probe(dev)) {
 454                 err = -ENXIO;
 455                 goto err_out_unregister_bus;
 456         }
 457         return 0;
 458
 459 err_out_unregister_bus:
 460         mdiobus_unregister(priv->mii_bus);
 461 err_out_free_mdio_irq:
 462         kfree(priv->mii_bus->irq);
 463 err_out_free_mdiobus:
 464         mdiobus_free(priv->mii_bus);
 465 err_out:
 466         return err;
 467 }
 468
 469 static void
 470 ltq_etop_mdio_cleanup(struct net_device *dev)
 471 {
 472         struct ltq_etop_priv *priv = netdev_priv(dev);
 473
 474         phy_disconnect(priv->phydev);
 475         mdiobus_unregister(priv->mii_bus);
 476         kfree(priv->mii_bus->irq);
 477         mdiobus_free(priv->mii_bus);
 478 }
 479
 480 static int
 481 ltq_etop_open(struct net_device *dev)
 482 {
 483         struct ltq_etop_priv *priv = netdev_priv(dev);
 484         int i;
 485
 486         for (i = 0; i < MAX_DMA_CHAN; i++) {
 487                 struct ltq_etop_chan *ch = &priv->ch[i];
 488
 489                 if (!IS_TX(i) && (!IS_RX(i)))
 490                         continue;
 491                 ltq_dma_open(&ch->dma);
 492                 napi_enable(&ch->napi);
 493         }
 494         phy_start(priv->phydev);
 495         netif_tx_start_all_queues(dev);
 496         return 0;
 497 }
 498
 499 static int
 500 ltq_etop_stop(struct net_device *dev)
 501 {
 502         struct ltq_etop_priv *priv = netdev_priv(dev);
 503         int i;
 504
 505         netif_tx_stop_all_queues(dev);
 506         phy_stop(priv->phydev);
 507         for (i = 0; i < MAX_DMA_CHAN; i++) {
 508                 struct ltq_etop_chan *ch = &priv->ch[i];
 509
 510                 if (!IS_RX(i) && !IS_TX(i))
 511                         continue;
 512                 napi_disable(&ch->napi);
 513                 ltq_dma_close(&ch->dma);
 514         }
 515         return 0;
 516 }
 517
 518 static int
 519 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 520 {
 521         int queue = skb_get_queue_mapping(skb);
 522         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 523         struct ltq_etop_priv *priv = netdev_priv(dev);
 524         struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 525         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 526         int len;
 527         unsigned long flags;
 528         u32 byte_offset;
 529
 530         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 531
 532         if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 533                 dev_kfree_skb_any(skb);
 534                 netdev_err(dev, "tx ring full\n");
 535                 netif_tx_stop_queue(txq);
 536                 return NETDEV_TX_BUSY;
 537         }
 538
 539         /* dma needs to start on a 16 byte aligned address */
 540         byte_offset = CPHYSADDR(skb->data) % 16;
 541         ch->skb[ch->dma.desc] = skb;
 542
 543         dev->trans_start = jiffies;
 544
 545         spin_lock_irqsave(&priv->lock, flags);
 546         desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
 547                                                 DMA_TO_DEVICE)) - byte_offset;
 548         wmb();
 549         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 550                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 551         ch->dma.desc++;
 552         ch->dma.desc %= LTQ_DESC_NUM;
 553         spin_unlock_irqrestore(&priv->lock, flags);
 554
 555         if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 556                 netif_tx_stop_queue(txq);
 557
 558         return NETDEV_TX_OK;
 559 }
 560
 561 static int
 562 ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
 563 {
 564         int ret = eth_change_mtu(dev, new_mtu);
 565
 566         if (!ret) {
 567                 struct ltq_etop_priv *priv = netdev_priv(dev);
 568                 unsigned long flags;
 569
 570                 spin_lock_irqsave(&priv->lock, flags);
 571                 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
 572                         LTQ_ETOP_IGPLEN);
 573                 spin_unlock_irqrestore(&priv->lock, flags);
 574         }
 575         return ret;
 576 }
 577
 578 static int
 579 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 580 {
 581         struct ltq_etop_priv *priv = netdev_priv(dev);
 582
 583         /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
 584         return phy_mii_ioctl(priv->phydev, rq, cmd);
 585 }
 586
 587 static int
 588 ltq_etop_set_mac_address(struct net_device *dev, void *p)
 589 {
 590         int ret = eth_mac_addr(dev, p);
 591
 592         if (!ret) {
 593                 struct ltq_etop_priv *priv = netdev_priv(dev);
 594                 unsigned long flags;
 595
 596                 /* store the mac for the unicast filter */
 597                 spin_lock_irqsave(&priv->lock, flags);
 598                 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
 599                 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
 600                         LTQ_ETOP_MAC_DA1);
 601                 spin_unlock_irqrestore(&priv->lock, flags);
 602         }
 603         return ret;
 604 }
 605
 606 static void
 607 ltq_etop_set_multicast_list(struct net_device *dev)
 608 {
 609         struct ltq_etop_priv *priv = netdev_priv(dev);
 610         unsigned long flags;
 611
 612         /* ensure that the unicast filter is not enabled in promiscious mode */
 613         spin_lock_irqsave(&priv->lock, flags);
 614         if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
 615                 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
 616         else
 617                 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
 618         spin_unlock_irqrestore(&priv->lock, flags);
 619 }
 620
 621 static u16
 622 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb)
 623 {
 624         /* we are currently only using the first queue */
 625         return 0;
 626 }
 627
 628 static int
 629 ltq_etop_init(struct net_device *dev)
 630 {
 631         struct ltq_etop_priv *priv = netdev_priv(dev);
 632         struct sockaddr mac;
 633         int err;
 634         bool random_mac = false;
 635
 636         ether_setup(dev);
 637         dev->watchdog_timeo = 10 * HZ;
 638         err = ltq_etop_hw_init(dev);
 639         if (err)
 640                 goto err_hw;
 641         ltq_etop_change_mtu(dev, 1500);
 642
 643         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 644         if (!is_valid_ether_addr(mac.sa_data)) {
 645                 pr_warn("etop: invalid MAC, using random\n");
 646                 eth_random_addr(mac.sa_data);
 647                 random_mac = true;
 648         }
 649
 650         err = ltq_etop_set_mac_address(dev, &mac);
 651         if (err)
 652                 goto err_netdev;
 653
 654         /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
 655         if (random_mac)
 656                 dev->addr_assign_type = NET_ADDR_RANDOM;
 657
 658         ltq_etop_set_multicast_list(dev);
 659         err = ltq_etop_mdio_init(dev);
 660         if (err)
 661                 goto err_netdev;
 662         return 0;
 663
 664 err_netdev:
 665         unregister_netdev(dev);
 666         free_netdev(dev);
 667 err_hw:
 668         ltq_etop_hw_exit(dev);
 669         return err;
 670 }
 671
 672 static void
 673 ltq_etop_tx_timeout(struct net_device *dev)
 674 {
 675         int err;
 676
 677         ltq_etop_hw_exit(dev);
 678         err = ltq_etop_hw_init(dev);
 679         if (err)
 680                 goto err_hw;
 681         dev->trans_start = jiffies;
 682         netif_wake_queue(dev);
 683         return;
 684
 685 err_hw:
 686         ltq_etop_hw_exit(dev);
 687         netdev_err(dev, "failed to restart etop after TX timeout\n");
 688 }
 689
 690 static const struct net_device_ops ltq_eth_netdev_ops = {
 691         .ndo_open = ltq_etop_open,
 692         .ndo_stop = ltq_etop_stop,
 693         .ndo_start_xmit = ltq_etop_tx,
 694         .ndo_change_mtu = ltq_etop_change_mtu,
 695         .ndo_do_ioctl = ltq_etop_ioctl,
 696         .ndo_set_mac_address = ltq_etop_set_mac_address,
 697         .ndo_validate_addr = eth_validate_addr,
 698         .ndo_set_rx_mode = ltq_etop_set_multicast_list,
 699         .ndo_select_queue = ltq_etop_select_queue,
 700         .ndo_init = ltq_etop_init,
 701         .ndo_tx_timeout = ltq_etop_tx_timeout,
 702 };
 703
 704 static int __init
 705 ltq_etop_probe(struct platform_device *pdev)
 706 {
 707         struct net_device *dev;
 708         struct ltq_etop_priv *priv;
 709         struct resource *res;
 710         int err;
 711         int i;
 712
 713         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714         if (!res) {
 715                 dev_err(&pdev->dev, "failed to get etop resource\n");
 716                 err = -ENOENT;
 717                 goto err_out;
 718         }
 719
 720         res = devm_request_mem_region(&pdev->dev, res->start,
 721                 resource_size(res), dev_name(&pdev->dev));
 722         if (!res) {
 723                 dev_err(&pdev->dev, "failed to request etop resource\n");
 724                 err = -EBUSY;
 725                 goto err_out;
 726         }
 727
 728         ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
 729                 res->start, resource_size(res));
 730         if (!ltq_etop_membase) {
 731                 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
 732                         pdev->id);
 733                 err = -ENOMEM;
 734                 goto err_out;
 735         }
 736
 737         dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 738         if (!dev) {
 739                 err = -ENOMEM;
 740                 goto err_out;
 741         }
 742         strcpy(dev->name, "eth%d");
 743         dev->netdev_ops = &ltq_eth_netdev_ops;
 744         dev->ethtool_ops = &ltq_etop_ethtool_ops;
 745         priv = netdev_priv(dev);
 746         priv->res = res;
 747         priv->pdev = pdev;
 748         priv->pldata = dev_get_platdata(&pdev->dev);
 749         priv->netdev = dev;
 750         spin_lock_init(&priv->lock);
 751
 752         for (i = 0; i < MAX_DMA_CHAN; i++) {
 753                 if (IS_TX(i))
 754                         netif_napi_add(dev, &priv->ch[i].napi,
 755                                 ltq_etop_poll_tx, 8);
 756                 else if (IS_RX(i))
 757                         netif_napi_add(dev, &priv->ch[i].napi,
 758                                 ltq_etop_poll_rx, 32);
 759                 priv->ch[i].netdev = dev;
 760         }
 761
 762         err = register_netdev(dev);
 763         if (err)
 764                 goto err_free;
 765
 766         platform_set_drvdata(pdev, dev);
 767         return 0;
 768
 769 err_free:
 770         free_netdev(dev);
 771 err_out:
 772         return err;
 773 }
 774
 775 static int
 776 ltq_etop_remove(struct platform_device *pdev)
 777 {
 778         struct net_device *dev = platform_get_drvdata(pdev);
 779
 780         if (dev) {
 781                 netif_tx_stop_all_queues(dev);
 782                 ltq_etop_hw_exit(dev);
 783                 ltq_etop_mdio_cleanup(dev);
 784                 unregister_netdev(dev);
 785         }
 786         return 0;
 787 }
 788
 789 static struct platform_driver ltq_mii_driver = {
 790         .remove = ltq_etop_remove,
 791         .driver = {
 792                 .name = "ltq_etop",
 793                 .owner = THIS_MODULE,
 794         },
 795 };
 796
 797 int __init
 798 init_ltq_etop(void)
 799 {
 800         int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 801
 802         if (ret)
 803                 pr_err("ltq_etop: Error registering platform driver!");
 804         return ret;
 805 }
 806
 807 static void __exit
 808 exit_ltq_etop(void)
 809 {
 810         platform_driver_unregister(&ltq_mii_driver);
 811 }
 812
 813 module_init(init_ltq_etop);
 814 module_exit(exit_ltq_etop);
 815
 816 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 817 MODULE_DESCRIPTION("Lantiq SoC ETOP");
 818 MODULE_LICENSE("GPL");