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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / ethernet / marvell / mvneta.c
blobfabdda91fd0eebff5a8732c18896b702e82af733
1 /*
2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <net/ip.h>
24 #include <net/ipv6.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
32
33 /* Registers */
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
83 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
84 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
85 #define MVNETA_DESC_SWAP BIT(6)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_SGMII_SERDES_CFG 0x24A0
92 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
93 #define MVNETA_TYPE_PRIO 0x24bc
94 #define MVNETA_FORCE_UNI BIT(21)
95 #define MVNETA_TXQ_CMD_1 0x24e4
96 #define MVNETA_TXQ_CMD 0x2448
97 #define MVNETA_TXQ_DISABLE_SHIFT 8
98 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
99 #define MVNETA_ACC_MODE 0x2500
100 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
101 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
102 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
103 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
104 #define MVNETA_INTR_NEW_CAUSE 0x25a0
105 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
106 #define MVNETA_INTR_NEW_MASK 0x25a4
107 #define MVNETA_INTR_OLD_CAUSE 0x25a8
108 #define MVNETA_INTR_OLD_MASK 0x25ac
109 #define MVNETA_INTR_MISC_CAUSE 0x25b0
110 #define MVNETA_INTR_MISC_MASK 0x25b4
111 #define MVNETA_INTR_ENABLE 0x25b8
112 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
113 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
114 #define MVNETA_RXQ_CMD 0x2680
115 #define MVNETA_RXQ_DISABLE_SHIFT 8
116 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
117 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
118 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
119 #define MVNETA_GMAC_CTRL_0 0x2c00
120 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
121 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
122 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
123 #define MVNETA_GMAC_CTRL_2 0x2c08
124 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
125 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
126 #define MVNETA_GMAC2_PORT_RESET BIT(6)
127 #define MVNETA_GMAC_STATUS 0x2c10
128 #define MVNETA_GMAC_LINK_UP BIT(0)
129 #define MVNETA_GMAC_SPEED_1000 BIT(1)
130 #define MVNETA_GMAC_SPEED_100 BIT(2)
131 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
134 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
135 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
136 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
137 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
138 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
139 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
140 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
141 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
142 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
143 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
144 #define MVNETA_MIB_COUNTERS_BASE 0x3080
145 #define MVNETA_MIB_LATE_COLLISION 0x7c
146 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
147 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
148 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
149 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
150 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
151 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
152 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
153 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
154 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
155 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
156 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
157 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
158 #define MVNETA_PORT_TX_RESET 0x3cf0
159 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
160 #define MVNETA_TX_MTU 0x3e0c
161 #define MVNETA_TX_TOKEN_SIZE 0x3e14
162 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
163 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
164 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
165
166 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
167
168 /* Descriptor ring Macros */
169 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
170 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
171
172 /* Various constants */
173
174 /* Coalescing */
175 #define MVNETA_TXDONE_COAL_PKTS 16
176 #define MVNETA_RX_COAL_PKTS 32
177 #define MVNETA_RX_COAL_USEC 100
178
179 /* Timer */
180 #define MVNETA_TX_DONE_TIMER_PERIOD 10
181
182 /* Napi polling weight */
183 #define MVNETA_RX_POLL_WEIGHT 64
184
185 /* The two bytes Marvell header. Either contains a special value used
186 * by Marvell switches when a specific hardware mode is enabled (not
187 * supported by this driver) or is filled automatically by zeroes on
188 * the RX side. Those two bytes being at the front of the Ethernet
189 * header, they allow to have the IP header aligned on a 4 bytes
190 * boundary automatically: the hardware skips those two bytes on its
191 * own.
192 */
193 #define MVNETA_MH_SIZE 2
194
195 #define MVNETA_VLAN_TAG_LEN 4
196
197 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
198 #define MVNETA_TX_CSUM_MAX_SIZE 9800
199 #define MVNETA_ACC_MODE_EXT 1
200
201 /* Timeout constants */
202 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
203 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
204 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
205
206 #define MVNETA_TX_MTU_MAX 0x3ffff
207
208 /* Max number of Rx descriptors */
209 #define MVNETA_MAX_RXD 128
210
211 /* Max number of Tx descriptors */
212 #define MVNETA_MAX_TXD 532
213
214 /* descriptor aligned size */
215 #define MVNETA_DESC_ALIGNED_SIZE 32
216
217 #define MVNETA_RX_PKT_SIZE(mtu) \
218 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
219 ETH_HLEN + ETH_FCS_LEN, \
220 MVNETA_CPU_D_CACHE_LINE_SIZE)
221
222 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
223
224 struct mvneta_stats {
225 struct u64_stats_sync syncp;
226 u64 packets;
227 u64 bytes;
228 };
229
230 struct mvneta_port {
231 int pkt_size;
232 void __iomem *base;
233 struct mvneta_rx_queue *rxqs;
234 struct mvneta_tx_queue *txqs;
235 struct timer_list tx_done_timer;
236 struct net_device *dev;
237
238 u32 cause_rx_tx;
239 struct napi_struct napi;
240
241 /* Flags */
242 unsigned long flags;
243 #define MVNETA_F_TX_DONE_TIMER_BIT 0
244
245 /* Napi weight */
246 int weight;
247
248 /* Core clock */
249 struct clk *clk;
250 u8 mcast_count[256];
251 u16 tx_ring_size;
252 u16 rx_ring_size;
253 struct mvneta_stats tx_stats;
254 struct mvneta_stats rx_stats;
255
256 struct mii_bus *mii_bus;
257 struct phy_device *phy_dev;
258 phy_interface_t phy_interface;
259 struct device_node *phy_node;
260 unsigned int link;
261 unsigned int duplex;
262 unsigned int speed;
263 };
264
265 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
266 * layout of the transmit and reception DMA descriptors, and their
267 * layout is therefore defined by the hardware design
268 */
269
270 #define MVNETA_TX_L3_OFF_SHIFT 0
271 #define MVNETA_TX_IP_HLEN_SHIFT 8
272 #define MVNETA_TX_L4_UDP BIT(16)
273 #define MVNETA_TX_L3_IP6 BIT(17)
274 #define MVNETA_TXD_IP_CSUM BIT(18)
275 #define MVNETA_TXD_Z_PAD BIT(19)
276 #define MVNETA_TXD_L_DESC BIT(20)
277 #define MVNETA_TXD_F_DESC BIT(21)
278 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
279 MVNETA_TXD_L_DESC | \
280 MVNETA_TXD_F_DESC)
281 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
282 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
283
284 #define MVNETA_RXD_ERR_CRC 0x0
285 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
286 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
287 #define MVNETA_RXD_ERR_LEN BIT(18)
288 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
289 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
290 #define MVNETA_RXD_L3_IP4 BIT(25)
291 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
292 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
293
294 #if defined(__LITTLE_ENDIAN)
295 struct mvneta_tx_desc {
296 u32 command; /* Options used by HW for packet transmitting.*/
297 u16 reserverd1; /* csum_l4 (for future use) */
298 u16 data_size; /* Data size of transmitted packet in bytes */
299 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
300 u32 reserved2; /* hw_cmd - (for future use, PMT) */
301 u32 reserved3[4]; /* Reserved - (for future use) */
302 };
303
304 struct mvneta_rx_desc {
305 u32 status; /* Info about received packet */
306 u16 reserved1; /* pnc_info - (for future use, PnC) */
307 u16 data_size; /* Size of received packet in bytes */
308
309 u32 buf_phys_addr; /* Physical address of the buffer */
310 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
311
312 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
313 u16 reserved3; /* prefetch_cmd, for future use */
314 u16 reserved4; /* csum_l4 - (for future use, PnC) */
315
316 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
317 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
318 };
319 #else
320 struct mvneta_tx_desc {
321 u16 data_size; /* Data size of transmitted packet in bytes */
322 u16 reserverd1; /* csum_l4 (for future use) */
323 u32 command; /* Options used by HW for packet transmitting.*/
324 u32 reserved2; /* hw_cmd - (for future use, PMT) */
325 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
326 u32 reserved3[4]; /* Reserved - (for future use) */
327 };
328
329 struct mvneta_rx_desc {
330 u16 data_size; /* Size of received packet in bytes */
331 u16 reserved1; /* pnc_info - (for future use, PnC) */
332 u32 status; /* Info about received packet */
333
334 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
335 u32 buf_phys_addr; /* Physical address of the buffer */
336
337 u16 reserved4; /* csum_l4 - (for future use, PnC) */
338 u16 reserved3; /* prefetch_cmd, for future use */
339 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
340
341 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
342 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
343 };
344 #endif
345
346 struct mvneta_tx_queue {
347 /* Number of this TX queue, in the range 0-7 */
348 u8 id;
349
350 /* Number of TX DMA descriptors in the descriptor ring */
351 int size;
352
353 /* Number of currently used TX DMA descriptor in the
354 * descriptor ring
355 */
356 int count;
357
358 /* Array of transmitted skb */
359 struct sk_buff **tx_skb;
360
361 /* Index of last TX DMA descriptor that was inserted */
362 int txq_put_index;
363
364 /* Index of the TX DMA descriptor to be cleaned up */
365 int txq_get_index;
366
367 u32 done_pkts_coal;
368
369 /* Virtual address of the TX DMA descriptors array */
370 struct mvneta_tx_desc *descs;
371
372 /* DMA address of the TX DMA descriptors array */
373 dma_addr_t descs_phys;
374
375 /* Index of the last TX DMA descriptor */
376 int last_desc;
377
378 /* Index of the next TX DMA descriptor to process */
379 int next_desc_to_proc;
380 };
381
382 struct mvneta_rx_queue {
383 /* rx queue number, in the range 0-7 */
384 u8 id;
385
386 /* num of rx descriptors in the rx descriptor ring */
387 int size;
388
389 /* counter of times when mvneta_refill() failed */
390 int missed;
391
392 u32 pkts_coal;
393 u32 time_coal;
394
395 /* Virtual address of the RX DMA descriptors array */
396 struct mvneta_rx_desc *descs;
397
398 /* DMA address of the RX DMA descriptors array */
399 dma_addr_t descs_phys;
400
401 /* Index of the last RX DMA descriptor */
402 int last_desc;
403
404 /* Index of the next RX DMA descriptor to process */
405 int next_desc_to_proc;
406 };
407
408 static int rxq_number = 8;
409 static int txq_number = 8;
410
411 static int rxq_def;
412
413 #define MVNETA_DRIVER_NAME "mvneta"
414 #define MVNETA_DRIVER_VERSION "1.0"
415
416 /* Utility/helper methods */
417
418 /* Write helper method */
419 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
420 {
421 writel(data, pp->base + offset);
422 }
423
424 /* Read helper method */
425 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
426 {
427 return readl(pp->base + offset);
428 }
429
430 /* Increment txq get counter */
431 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
432 {
433 txq->txq_get_index++;
434 if (txq->txq_get_index == txq->size)
435 txq->txq_get_index = 0;
436 }
437
438 /* Increment txq put counter */
439 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
440 {
441 txq->txq_put_index++;
442 if (txq->txq_put_index == txq->size)
443 txq->txq_put_index = 0;
444 }
445
446
447 /* Clear all MIB counters */
448 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
449 {
450 int i;
451 u32 dummy;
452
453 /* Perform dummy reads from MIB counters */
454 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
455 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
456 }
457
458 /* Get System Network Statistics */
459 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
460 struct rtnl_link_stats64 *stats)
461 {
462 struct mvneta_port *pp = netdev_priv(dev);
463 unsigned int start;
464
465 memset(stats, 0, sizeof(struct rtnl_link_stats64));
466
467 do {
468 start = u64_stats_fetch_begin_bh(&pp->rx_stats.syncp);
469 stats->rx_packets = pp->rx_stats.packets;
470 stats->rx_bytes = pp->rx_stats.bytes;
471 } while (u64_stats_fetch_retry_bh(&pp->rx_stats.syncp, start));
472
473
474 do {
475 start = u64_stats_fetch_begin_bh(&pp->tx_stats.syncp);
476 stats->tx_packets = pp->tx_stats.packets;
477 stats->tx_bytes = pp->tx_stats.bytes;
478 } while (u64_stats_fetch_retry_bh(&pp->tx_stats.syncp, start));
479
480 stats->rx_errors = dev->stats.rx_errors;
481 stats->rx_dropped = dev->stats.rx_dropped;
482
483 stats->tx_dropped = dev->stats.tx_dropped;
484
485 return stats;
486 }
487
488 /* Rx descriptors helper methods */
489
490 /* Checks whether the given RX descriptor is both the first and the
491 * last descriptor for the RX packet. Each RX packet is currently
492 * received through a single RX descriptor, so not having each RX
493 * descriptor with its first and last bits set is an error
494 */
495 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc *desc)
496 {
497 return (desc->status & MVNETA_RXD_FIRST_LAST_DESC) ==
498 MVNETA_RXD_FIRST_LAST_DESC;
499 }
500
501 /* Add number of descriptors ready to receive new packets */
502 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
503 struct mvneta_rx_queue *rxq,
504 int ndescs)
505 {
506 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
507 * be added at once
508 */
509 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
510 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
511 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
512 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
513 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
514 }
515
516 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
517 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
518 }
519
520 /* Get number of RX descriptors occupied by received packets */
521 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
522 struct mvneta_rx_queue *rxq)
523 {
524 u32 val;
525
526 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
527 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
528 }
529
530 /* Update num of rx desc called upon return from rx path or
531 * from mvneta_rxq_drop_pkts().
532 */
533 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
534 struct mvneta_rx_queue *rxq,
535 int rx_done, int rx_filled)
536 {
537 u32 val;
538
539 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
540 val = rx_done |
541 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
542 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
543 return;
544 }
545
546 /* Only 255 descriptors can be added at once */
547 while ((rx_done > 0) || (rx_filled > 0)) {
548 if (rx_done <= 0xff) {
549 val = rx_done;
550 rx_done = 0;
551 } else {
552 val = 0xff;
553 rx_done -= 0xff;
554 }
555 if (rx_filled <= 0xff) {
556 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
557 rx_filled = 0;
558 } else {
559 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
560 rx_filled -= 0xff;
561 }
562 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
563 }
564 }
565
566 /* Get pointer to next RX descriptor to be processed by SW */
567 static struct mvneta_rx_desc *
568 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
569 {
570 int rx_desc = rxq->next_desc_to_proc;
571
572 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
573 return rxq->descs + rx_desc;
574 }
575
576 /* Change maximum receive size of the port. */
577 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
578 {
579 u32 val;
580
581 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
582 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
583 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
584 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
585 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
586 }
587
588
589 /* Set rx queue offset */
590 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
591 struct mvneta_rx_queue *rxq,
592 int offset)
593 {
594 u32 val;
595
596 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
597 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
598
599 /* Offset is in */
600 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
601 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
602 }
603
604
605 /* Tx descriptors helper methods */
606
607 /* Update HW with number of TX descriptors to be sent */
608 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
609 struct mvneta_tx_queue *txq,
610 int pend_desc)
611 {
612 u32 val;
613
614 /* Only 255 descriptors can be added at once ; Assume caller
615 * process TX desriptors in quanta less than 256
616 */
617 val = pend_desc;
618 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
619 }
620
621 /* Get pointer to next TX descriptor to be processed (send) by HW */
622 static struct mvneta_tx_desc *
623 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
624 {
625 int tx_desc = txq->next_desc_to_proc;
626
627 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
628 return txq->descs + tx_desc;
629 }
630
631 /* Release the last allocated TX descriptor. Useful to handle DMA
632 * mapping failures in the TX path.
633 */
634 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
635 {
636 if (txq->next_desc_to_proc == 0)
637 txq->next_desc_to_proc = txq->last_desc - 1;
638 else
639 txq->next_desc_to_proc--;
640 }
641
642 /* Set rxq buf size */
643 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
644 struct mvneta_rx_queue *rxq,
645 int buf_size)
646 {
647 u32 val;
648
649 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
650
651 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
652 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
653
654 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
655 }
656
657 /* Disable buffer management (BM) */
658 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
659 struct mvneta_rx_queue *rxq)
660 {
661 u32 val;
662
663 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
664 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
665 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
666 }
667
668
669
670 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
671 static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable)
672 {
673 u32 val;
674
675 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
676
677 if (enable)
678 val |= MVNETA_GMAC2_PORT_RGMII;
679 else
680 val &= ~MVNETA_GMAC2_PORT_RGMII;
681
682 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
683 }
684
685 /* Config SGMII port */
686 static void mvneta_port_sgmii_config(struct mvneta_port *pp)
687 {
688 u32 val;
689
690 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
691 val |= MVNETA_GMAC2_PCS_ENABLE;
692 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
693
694 mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
695 }
696
697 /* Start the Ethernet port RX and TX activity */
698 static void mvneta_port_up(struct mvneta_port *pp)
699 {
700 int queue;
701 u32 q_map;
702
703 /* Enable all initialized TXs. */
704 mvneta_mib_counters_clear(pp);
705 q_map = 0;
706 for (queue = 0; queue < txq_number; queue++) {
707 struct mvneta_tx_queue *txq = &pp->txqs[queue];
708 if (txq->descs != NULL)
709 q_map |= (1 << queue);
710 }
711 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
712
713 /* Enable all initialized RXQs. */
714 q_map = 0;
715 for (queue = 0; queue < rxq_number; queue++) {
716 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
717 if (rxq->descs != NULL)
718 q_map |= (1 << queue);
719 }
720
721 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
722 }
723
724 /* Stop the Ethernet port activity */
725 static void mvneta_port_down(struct mvneta_port *pp)
726 {
727 u32 val;
728 int count;
729
730 /* Stop Rx port activity. Check port Rx activity. */
731 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
732
733 /* Issue stop command for active channels only */
734 if (val != 0)
735 mvreg_write(pp, MVNETA_RXQ_CMD,
736 val << MVNETA_RXQ_DISABLE_SHIFT);
737
738 /* Wait for all Rx activity to terminate. */
739 count = 0;
740 do {
741 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
742 netdev_warn(pp->dev,
743 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
744 val);
745 break;
746 }
747 mdelay(1);
748
749 val = mvreg_read(pp, MVNETA_RXQ_CMD);
750 } while (val & 0xff);
751
752 /* Stop Tx port activity. Check port Tx activity. Issue stop
753 * command for active channels only
754 */
755 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
756
757 if (val != 0)
758 mvreg_write(pp, MVNETA_TXQ_CMD,
759 (val << MVNETA_TXQ_DISABLE_SHIFT));
760
761 /* Wait for all Tx activity to terminate. */
762 count = 0;
763 do {
764 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
765 netdev_warn(pp->dev,
766 "TIMEOUT for TX stopped status=0x%08x\n",
767 val);
768 break;
769 }
770 mdelay(1);
771
772 /* Check TX Command reg that all Txqs are stopped */
773 val = mvreg_read(pp, MVNETA_TXQ_CMD);
774
775 } while (val & 0xff);
776
777 /* Double check to verify that TX FIFO is empty */
778 count = 0;
779 do {
780 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
781 netdev_warn(pp->dev,
782 "TX FIFO empty timeout status=0x08%x\n",
783 val);
784 break;
785 }
786 mdelay(1);
787
788 val = mvreg_read(pp, MVNETA_PORT_STATUS);
789 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
790 (val & MVNETA_TX_IN_PRGRS));
791
792 udelay(200);
793 }
794
795 /* Enable the port by setting the port enable bit of the MAC control register */
796 static void mvneta_port_enable(struct mvneta_port *pp)
797 {
798 u32 val;
799
800 /* Enable port */
801 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
802 val |= MVNETA_GMAC0_PORT_ENABLE;
803 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
804 }
805
806 /* Disable the port and wait for about 200 usec before retuning */
807 static void mvneta_port_disable(struct mvneta_port *pp)
808 {
809 u32 val;
810
811 /* Reset the Enable bit in the Serial Control Register */
812 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
813 val &= ~MVNETA_GMAC0_PORT_ENABLE;
814 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
815
816 udelay(200);
817 }
818
819 /* Multicast tables methods */
820
821 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
822 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
823 {
824 int offset;
825 u32 val;
826
827 if (queue == -1) {
828 val = 0;
829 } else {
830 val = 0x1 | (queue << 1);
831 val |= (val << 24) | (val << 16) | (val << 8);
832 }
833
834 for (offset = 0; offset <= 0xc; offset += 4)
835 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
836 }
837
838 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
839 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
840 {
841 int offset;
842 u32 val;
843
844 if (queue == -1) {
845 val = 0;
846 } else {
847 val = 0x1 | (queue << 1);
848 val |= (val << 24) | (val << 16) | (val << 8);
849 }
850
851 for (offset = 0; offset <= 0xfc; offset += 4)
852 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
853
854 }
855
856 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
857 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
858 {
859 int offset;
860 u32 val;
861
862 if (queue == -1) {
863 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
864 val = 0;
865 } else {
866 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
867 val = 0x1 | (queue << 1);
868 val |= (val << 24) | (val << 16) | (val << 8);
869 }
870
871 for (offset = 0; offset <= 0xfc; offset += 4)
872 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
873 }
874
875 /* This method sets defaults to the NETA port:
876 * Clears interrupt Cause and Mask registers.
877 * Clears all MAC tables.
878 * Sets defaults to all registers.
879 * Resets RX and TX descriptor rings.
880 * Resets PHY.
881 * This method can be called after mvneta_port_down() to return the port
882 * settings to defaults.
883 */
884 static void mvneta_defaults_set(struct mvneta_port *pp)
885 {
886 int cpu;
887 int queue;
888 u32 val;
889
890 /* Clear all Cause registers */
891 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
892 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
893 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
894
895 /* Mask all interrupts */
896 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
897 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
898 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
899 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
900
901 /* Enable MBUS Retry bit16 */
902 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
903
904 /* Set CPU queue access map - all CPUs have access to all RX
905 * queues and to all TX queues
906 */
907 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
908 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
909 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
910 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
911
912 /* Reset RX and TX DMAs */
913 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
914 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
915
916 /* Disable Legacy WRR, Disable EJP, Release from reset */
917 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
918 for (queue = 0; queue < txq_number; queue++) {
919 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
920 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
921 }
922
923 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
924 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
925
926 /* Set Port Acceleration Mode */
927 val = MVNETA_ACC_MODE_EXT;
928 mvreg_write(pp, MVNETA_ACC_MODE, val);
929
930 /* Update val of portCfg register accordingly with all RxQueue types */
931 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
932 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
933
934 val = 0;
935 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
936 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
937
938 /* Build PORT_SDMA_CONFIG_REG */
939 val = 0;
940
941 /* Default burst size */
942 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
943 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
944 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
945
946 #if defined(__BIG_ENDIAN)
947 val |= MVNETA_DESC_SWAP;
948 #endif
949
950 /* Assign port SDMA configuration */
951 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
952
953 /* Disable PHY polling in hardware, since we're using the
954 * kernel phylib to do this.
955 */
956 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
957 val &= ~MVNETA_PHY_POLLING_ENABLE;
958 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
959
960 mvneta_set_ucast_table(pp, -1);
961 mvneta_set_special_mcast_table(pp, -1);
962 mvneta_set_other_mcast_table(pp, -1);
963
964 /* Set port interrupt enable register - default enable all */
965 mvreg_write(pp, MVNETA_INTR_ENABLE,
966 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
967 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
968 }
969
970 /* Set max sizes for tx queues */
971 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
972
973 {
974 u32 val, size, mtu;
975 int queue;
976
977 mtu = max_tx_size * 8;
978 if (mtu > MVNETA_TX_MTU_MAX)
979 mtu = MVNETA_TX_MTU_MAX;
980
981 /* Set MTU */
982 val = mvreg_read(pp, MVNETA_TX_MTU);
983 val &= ~MVNETA_TX_MTU_MAX;
984 val |= mtu;
985 mvreg_write(pp, MVNETA_TX_MTU, val);
986
987 /* TX token size and all TXQs token size must be larger that MTU */
988 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
989
990 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
991 if (size < mtu) {
992 size = mtu;
993 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
994 val |= size;
995 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
996 }
997 for (queue = 0; queue < txq_number; queue++) {
998 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
999
1000 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1001 if (size < mtu) {
1002 size = mtu;
1003 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1004 val |= size;
1005 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1006 }
1007 }
1008 }
1009
1010 /* Set unicast address */
1011 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1012 int queue)
1013 {
1014 unsigned int unicast_reg;
1015 unsigned int tbl_offset;
1016 unsigned int reg_offset;
1017
1018 /* Locate the Unicast table entry */
1019 last_nibble = (0xf & last_nibble);
1020
1021 /* offset from unicast tbl base */
1022 tbl_offset = (last_nibble / 4) * 4;
1023
1024 /* offset within the above reg */
1025 reg_offset = last_nibble % 4;
1026
1027 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1028
1029 if (queue == -1) {
1030 /* Clear accepts frame bit at specified unicast DA tbl entry */
1031 unicast_reg &= ~(0xff << (8 * reg_offset));
1032 } else {
1033 unicast_reg &= ~(0xff << (8 * reg_offset));
1034 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1035 }
1036
1037 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1038 }
1039
1040 /* Set mac address */
1041 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1042 int queue)
1043 {
1044 unsigned int mac_h;
1045 unsigned int mac_l;
1046
1047 if (queue != -1) {
1048 mac_l = (addr[4] << 8) | (addr[5]);
1049 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1050 (addr[2] << 8) | (addr[3] << 0);
1051
1052 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1053 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1054 }
1055
1056 /* Accept frames of this address */
1057 mvneta_set_ucast_addr(pp, addr[5], queue);
1058 }
1059
1060 /* Set the number of packets that will be received before RX interrupt
1061 * will be generated by HW.
1062 */
1063 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1064 struct mvneta_rx_queue *rxq, u32 value)
1065 {
1066 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1067 value | MVNETA_RXQ_NON_OCCUPIED(0));
1068 rxq->pkts_coal = value;
1069 }
1070
1071 /* Set the time delay in usec before RX interrupt will be generated by
1072 * HW.
1073 */
1074 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1075 struct mvneta_rx_queue *rxq, u32 value)
1076 {
1077 u32 val;
1078 unsigned long clk_rate;
1079
1080 clk_rate = clk_get_rate(pp->clk);
1081 val = (clk_rate / 1000000) * value;
1082
1083 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1084 rxq->time_coal = value;
1085 }
1086
1087 /* Set threshold for TX_DONE pkts coalescing */
1088 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1089 struct mvneta_tx_queue *txq, u32 value)
1090 {
1091 u32 val;
1092
1093 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1094
1095 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1096 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1097
1098 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1099
1100 txq->done_pkts_coal = value;
1101 }
1102
1103 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1104 static void mvneta_add_tx_done_timer(struct mvneta_port *pp)
1105 {
1106 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags) == 0) {
1107 pp->tx_done_timer.expires = jiffies +
1108 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD);
1109 add_timer(&pp->tx_done_timer);
1110 }
1111 }
1112
1113
1114 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1115 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1116 u32 phys_addr, u32 cookie)
1117 {
1118 rx_desc->buf_cookie = cookie;
1119 rx_desc->buf_phys_addr = phys_addr;
1120 }
1121
1122 /* Decrement sent descriptors counter */
1123 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1124 struct mvneta_tx_queue *txq,
1125 int sent_desc)
1126 {
1127 u32 val;
1128
1129 /* Only 255 TX descriptors can be updated at once */
1130 while (sent_desc > 0xff) {
1131 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1132 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1133 sent_desc = sent_desc - 0xff;
1134 }
1135
1136 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1137 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1138 }
1139
1140 /* Get number of TX descriptors already sent by HW */
1141 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1142 struct mvneta_tx_queue *txq)
1143 {
1144 u32 val;
1145 int sent_desc;
1146
1147 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1148 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1149 MVNETA_TXQ_SENT_DESC_SHIFT;
1150
1151 return sent_desc;
1152 }
1153
1154 /* Get number of sent descriptors and decrement counter.
1155 * The number of sent descriptors is returned.
1156 */
1157 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1158 struct mvneta_tx_queue *txq)
1159 {
1160 int sent_desc;
1161
1162 /* Get number of sent descriptors */
1163 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1164
1165 /* Decrement sent descriptors counter */
1166 if (sent_desc)
1167 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1168
1169 return sent_desc;
1170 }
1171
1172 /* Set TXQ descriptors fields relevant for CSUM calculation */
1173 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1174 int ip_hdr_len, int l4_proto)
1175 {
1176 u32 command;
1177
1178 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1179 * G_L4_chk, L4_type; required only for checksum
1180 * calculation
1181 */
1182 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1183 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1184
1185 if (l3_proto == swab16(ETH_P_IP))
1186 command |= MVNETA_TXD_IP_CSUM;
1187 else
1188 command |= MVNETA_TX_L3_IP6;
1189
1190 if (l4_proto == IPPROTO_TCP)
1191 command |= MVNETA_TX_L4_CSUM_FULL;
1192 else if (l4_proto == IPPROTO_UDP)
1193 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1194 else
1195 command |= MVNETA_TX_L4_CSUM_NOT;
1196
1197 return command;
1198 }
1199
1200
1201 /* Display more error info */
1202 static void mvneta_rx_error(struct mvneta_port *pp,
1203 struct mvneta_rx_desc *rx_desc)
1204 {
1205 u32 status = rx_desc->status;
1206
1207 if (!mvneta_rxq_desc_is_first_last(rx_desc)) {
1208 netdev_err(pp->dev,
1209 "bad rx status %08x (buffer oversize), size=%d\n",
1210 rx_desc->status, rx_desc->data_size);
1211 return;
1212 }
1213
1214 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1215 case MVNETA_RXD_ERR_CRC:
1216 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1217 status, rx_desc->data_size);
1218 break;
1219 case MVNETA_RXD_ERR_OVERRUN:
1220 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1221 status, rx_desc->data_size);
1222 break;
1223 case MVNETA_RXD_ERR_LEN:
1224 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1225 status, rx_desc->data_size);
1226 break;
1227 case MVNETA_RXD_ERR_RESOURCE:
1228 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1229 status, rx_desc->data_size);
1230 break;
1231 }
1232 }
1233
1234 /* Handle RX checksum offload */
1235 static void mvneta_rx_csum(struct mvneta_port *pp,
1236 struct mvneta_rx_desc *rx_desc,
1237 struct sk_buff *skb)
1238 {
1239 if ((rx_desc->status & MVNETA_RXD_L3_IP4) &&
1240 (rx_desc->status & MVNETA_RXD_L4_CSUM_OK)) {
1241 skb->csum = 0;
1242 skb->ip_summed = CHECKSUM_UNNECESSARY;
1243 return;
1244 }
1245
1246 skb->ip_summed = CHECKSUM_NONE;
1247 }
1248
1249 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1250 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1251 u32 cause)
1252 {
1253 int queue = fls(cause) - 1;
1254
1255 return (queue < 0 || queue >= txq_number) ? NULL : &pp->txqs[queue];
1256 }
1257
1258 /* Free tx queue skbuffs */
1259 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1260 struct mvneta_tx_queue *txq, int num)
1261 {
1262 int i;
1263
1264 for (i = 0; i < num; i++) {
1265 struct mvneta_tx_desc *tx_desc = txq->descs +
1266 txq->txq_get_index;
1267 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1268
1269 mvneta_txq_inc_get(txq);
1270
1271 if (!skb)
1272 continue;
1273
1274 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1275 tx_desc->data_size, DMA_TO_DEVICE);
1276 dev_kfree_skb_any(skb);
1277 }
1278 }
1279
1280 /* Handle end of transmission */
1281 static int mvneta_txq_done(struct mvneta_port *pp,
1282 struct mvneta_tx_queue *txq)
1283 {
1284 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1285 int tx_done;
1286
1287 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1288 if (tx_done == 0)
1289 return tx_done;
1290 mvneta_txq_bufs_free(pp, txq, tx_done);
1291
1292 txq->count -= tx_done;
1293
1294 if (netif_tx_queue_stopped(nq)) {
1295 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1296 netif_tx_wake_queue(nq);
1297 }
1298
1299 return tx_done;
1300 }
1301
1302 /* Refill processing */
1303 static int mvneta_rx_refill(struct mvneta_port *pp,
1304 struct mvneta_rx_desc *rx_desc)
1305
1306 {
1307 dma_addr_t phys_addr;
1308 struct sk_buff *skb;
1309
1310 skb = netdev_alloc_skb(pp->dev, pp->pkt_size);
1311 if (!skb)
1312 return -ENOMEM;
1313
1314 phys_addr = dma_map_single(pp->dev->dev.parent, skb->head,
1315 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1316 DMA_FROM_DEVICE);
1317 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1318 dev_kfree_skb(skb);
1319 return -ENOMEM;
1320 }
1321
1322 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1323
1324 return 0;
1325 }
1326
1327 /* Handle tx checksum */
1328 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1329 {
1330 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1331 int ip_hdr_len = 0;
1332 u8 l4_proto;
1333
1334 if (skb->protocol == htons(ETH_P_IP)) {
1335 struct iphdr *ip4h = ip_hdr(skb);
1336
1337 /* Calculate IPv4 checksum and L4 checksum */
1338 ip_hdr_len = ip4h->ihl;
1339 l4_proto = ip4h->protocol;
1340 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1341 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1342
1343 /* Read l4_protocol from one of IPv6 extra headers */
1344 if (skb_network_header_len(skb) > 0)
1345 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1346 l4_proto = ip6h->nexthdr;
1347 } else
1348 return MVNETA_TX_L4_CSUM_NOT;
1349
1350 return mvneta_txq_desc_csum(skb_network_offset(skb),
1351 skb->protocol, ip_hdr_len, l4_proto);
1352 }
1353
1354 return MVNETA_TX_L4_CSUM_NOT;
1355 }
1356
1357 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1358 * value
1359 */
1360 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1361 u32 cause)
1362 {
1363 int queue = fls(cause >> 8) - 1;
1364
1365 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1366 }
1367
1368 /* Drop packets received by the RXQ and free buffers */
1369 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1370 struct mvneta_rx_queue *rxq)
1371 {
1372 int rx_done, i;
1373
1374 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1375 for (i = 0; i < rxq->size; i++) {
1376 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1377 struct sk_buff *skb = (struct sk_buff *)rx_desc->buf_cookie;
1378
1379 dev_kfree_skb_any(skb);
1380 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1381 rx_desc->data_size, DMA_FROM_DEVICE);
1382 }
1383
1384 if (rx_done)
1385 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1386 }
1387
1388 /* Main rx processing */
1389 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1390 struct mvneta_rx_queue *rxq)
1391 {
1392 struct net_device *dev = pp->dev;
1393 int rx_done, rx_filled;
1394
1395 /* Get number of received packets */
1396 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1397
1398 if (rx_todo > rx_done)
1399 rx_todo = rx_done;
1400
1401 rx_done = 0;
1402 rx_filled = 0;
1403
1404 /* Fairness NAPI loop */
1405 while (rx_done < rx_todo) {
1406 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1407 struct sk_buff *skb;
1408 u32 rx_status;
1409 int rx_bytes, err;
1410
1411 prefetch(rx_desc);
1412 rx_done++;
1413 rx_filled++;
1414 rx_status = rx_desc->status;
1415 skb = (struct sk_buff *)rx_desc->buf_cookie;
1416
1417 if (!mvneta_rxq_desc_is_first_last(rx_desc) ||
1418 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1419 dev->stats.rx_errors++;
1420 mvneta_rx_error(pp, rx_desc);
1421 mvneta_rx_desc_fill(rx_desc, rx_desc->buf_phys_addr,
1422 (u32)skb);
1423 continue;
1424 }
1425
1426 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1427 rx_desc->data_size, DMA_FROM_DEVICE);
1428
1429 rx_bytes = rx_desc->data_size -
1430 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1431 u64_stats_update_begin(&pp->rx_stats.syncp);
1432 pp->rx_stats.packets++;
1433 pp->rx_stats.bytes += rx_bytes;
1434 u64_stats_update_end(&pp->rx_stats.syncp);
1435
1436 /* Linux processing */
1437 skb_reserve(skb, MVNETA_MH_SIZE);
1438 skb_put(skb, rx_bytes);
1439
1440 skb->protocol = eth_type_trans(skb, dev);
1441
1442 mvneta_rx_csum(pp, rx_desc, skb);
1443
1444 napi_gro_receive(&pp->napi, skb);
1445
1446 /* Refill processing */
1447 err = mvneta_rx_refill(pp, rx_desc);
1448 if (err) {
1449 netdev_err(pp->dev, "Linux processing - Can't refill\n");
1450 rxq->missed++;
1451 rx_filled--;
1452 }
1453 }
1454
1455 /* Update rxq management counters */
1456 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1457
1458 return rx_done;
1459 }
1460
1461 /* Handle tx fragmentation processing */
1462 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1463 struct mvneta_tx_queue *txq)
1464 {
1465 struct mvneta_tx_desc *tx_desc;
1466 int i;
1467
1468 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1469 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1470 void *addr = page_address(frag->page.p) + frag->page_offset;
1471
1472 tx_desc = mvneta_txq_next_desc_get(txq);
1473 tx_desc->data_size = frag->size;
1474
1475 tx_desc->buf_phys_addr =
1476 dma_map_single(pp->dev->dev.parent, addr,
1477 tx_desc->data_size, DMA_TO_DEVICE);
1478
1479 if (dma_mapping_error(pp->dev->dev.parent,
1480 tx_desc->buf_phys_addr)) {
1481 mvneta_txq_desc_put(txq);
1482 goto error;
1483 }
1484
1485 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1486 /* Last descriptor */
1487 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1488
1489 txq->tx_skb[txq->txq_put_index] = skb;
1490
1491 mvneta_txq_inc_put(txq);
1492 } else {
1493 /* Descriptor in the middle: Not First, Not Last */
1494 tx_desc->command = 0;
1495
1496 txq->tx_skb[txq->txq_put_index] = NULL;
1497 mvneta_txq_inc_put(txq);
1498 }
1499 }
1500
1501 return 0;
1502
1503 error:
1504 /* Release all descriptors that were used to map fragments of
1505 * this packet, as well as the corresponding DMA mappings
1506 */
1507 for (i = i - 1; i >= 0; i--) {
1508 tx_desc = txq->descs + i;
1509 dma_unmap_single(pp->dev->dev.parent,
1510 tx_desc->buf_phys_addr,
1511 tx_desc->data_size,
1512 DMA_TO_DEVICE);
1513 mvneta_txq_desc_put(txq);
1514 }
1515
1516 return -ENOMEM;
1517 }
1518
1519 /* Main tx processing */
1520 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1521 {
1522 struct mvneta_port *pp = netdev_priv(dev);
1523 u16 txq_id = skb_get_queue_mapping(skb);
1524 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1525 struct mvneta_tx_desc *tx_desc;
1526 struct netdev_queue *nq;
1527 int frags = 0;
1528 u32 tx_cmd;
1529
1530 if (!netif_running(dev))
1531 goto out;
1532
1533 frags = skb_shinfo(skb)->nr_frags + 1;
1534 nq = netdev_get_tx_queue(dev, txq_id);
1535
1536 /* Get a descriptor for the first part of the packet */
1537 tx_desc = mvneta_txq_next_desc_get(txq);
1538
1539 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1540
1541 tx_desc->data_size = skb_headlen(skb);
1542
1543 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1544 tx_desc->data_size,
1545 DMA_TO_DEVICE);
1546 if (unlikely(dma_mapping_error(dev->dev.parent,
1547 tx_desc->buf_phys_addr))) {
1548 mvneta_txq_desc_put(txq);
1549 frags = 0;
1550 goto out;
1551 }
1552
1553 if (frags == 1) {
1554 /* First and Last descriptor */
1555 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1556 tx_desc->command = tx_cmd;
1557 txq->tx_skb[txq->txq_put_index] = skb;
1558 mvneta_txq_inc_put(txq);
1559 } else {
1560 /* First but not Last */
1561 tx_cmd |= MVNETA_TXD_F_DESC;
1562 txq->tx_skb[txq->txq_put_index] = NULL;
1563 mvneta_txq_inc_put(txq);
1564 tx_desc->command = tx_cmd;
1565 /* Continue with other skb fragments */
1566 if (mvneta_tx_frag_process(pp, skb, txq)) {
1567 dma_unmap_single(dev->dev.parent,
1568 tx_desc->buf_phys_addr,
1569 tx_desc->data_size,
1570 DMA_TO_DEVICE);
1571 mvneta_txq_desc_put(txq);
1572 frags = 0;
1573 goto out;
1574 }
1575 }
1576
1577 txq->count += frags;
1578 mvneta_txq_pend_desc_add(pp, txq, frags);
1579
1580 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1581 netif_tx_stop_queue(nq);
1582
1583 out:
1584 if (frags > 0) {
1585 u64_stats_update_begin(&pp->tx_stats.syncp);
1586 pp->tx_stats.packets++;
1587 pp->tx_stats.bytes += skb->len;
1588 u64_stats_update_end(&pp->tx_stats.syncp);
1589
1590 } else {
1591 dev->stats.tx_dropped++;
1592 dev_kfree_skb_any(skb);
1593 }
1594
1595 if (txq->count >= MVNETA_TXDONE_COAL_PKTS)
1596 mvneta_txq_done(pp, txq);
1597
1598 /* If after calling mvneta_txq_done, count equals
1599 * frags, we need to set the timer
1600 */
1601 if (txq->count == frags && frags > 0)
1602 mvneta_add_tx_done_timer(pp);
1603
1604 return NETDEV_TX_OK;
1605 }
1606
1607
1608 /* Free tx resources, when resetting a port */
1609 static void mvneta_txq_done_force(struct mvneta_port *pp,
1610 struct mvneta_tx_queue *txq)
1611
1612 {
1613 int tx_done = txq->count;
1614
1615 mvneta_txq_bufs_free(pp, txq, tx_done);
1616
1617 /* reset txq */
1618 txq->count = 0;
1619 txq->txq_put_index = 0;
1620 txq->txq_get_index = 0;
1621 }
1622
1623 /* handle tx done - called from tx done timer callback */
1624 static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done,
1625 int *tx_todo)
1626 {
1627 struct mvneta_tx_queue *txq;
1628 u32 tx_done = 0;
1629 struct netdev_queue *nq;
1630
1631 *tx_todo = 0;
1632 while (cause_tx_done != 0) {
1633 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1634 if (!txq)
1635 break;
1636
1637 nq = netdev_get_tx_queue(pp->dev, txq->id);
1638 __netif_tx_lock(nq, smp_processor_id());
1639
1640 if (txq->count) {
1641 tx_done += mvneta_txq_done(pp, txq);
1642 *tx_todo += txq->count;
1643 }
1644
1645 __netif_tx_unlock(nq);
1646 cause_tx_done &= ~((1 << txq->id));
1647 }
1648
1649 return tx_done;
1650 }
1651
1652 /* Compute crc8 of the specified address, using a unique algorithm ,
1653 * according to hw spec, different than generic crc8 algorithm
1654 */
1655 static int mvneta_addr_crc(unsigned char *addr)
1656 {
1657 int crc = 0;
1658 int i;
1659
1660 for (i = 0; i < ETH_ALEN; i++) {
1661 int j;
1662
1663 crc = (crc ^ addr[i]) << 8;
1664 for (j = 7; j >= 0; j--) {
1665 if (crc & (0x100 << j))
1666 crc ^= 0x107 << j;
1667 }
1668 }
1669
1670 return crc;
1671 }
1672
1673 /* This method controls the net device special MAC multicast support.
1674 * The Special Multicast Table for MAC addresses supports MAC of the form
1675 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1676 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1677 * Table entries in the DA-Filter table. This method set the Special
1678 * Multicast Table appropriate entry.
1679 */
1680 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1681 unsigned char last_byte,
1682 int queue)
1683 {
1684 unsigned int smc_table_reg;
1685 unsigned int tbl_offset;
1686 unsigned int reg_offset;
1687
1688 /* Register offset from SMC table base */
1689 tbl_offset = (last_byte / 4);
1690 /* Entry offset within the above reg */
1691 reg_offset = last_byte % 4;
1692
1693 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1694 + tbl_offset * 4));
1695
1696 if (queue == -1)
1697 smc_table_reg &= ~(0xff << (8 * reg_offset));
1698 else {
1699 smc_table_reg &= ~(0xff << (8 * reg_offset));
1700 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1701 }
1702
1703 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1704 smc_table_reg);
1705 }
1706
1707 /* This method controls the network device Other MAC multicast support.
1708 * The Other Multicast Table is used for multicast of another type.
1709 * A CRC-8 is used as an index to the Other Multicast Table entries
1710 * in the DA-Filter table.
1711 * The method gets the CRC-8 value from the calling routine and
1712 * sets the Other Multicast Table appropriate entry according to the
1713 * specified CRC-8 .
1714 */
1715 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1716 unsigned char crc8,
1717 int queue)
1718 {
1719 unsigned int omc_table_reg;
1720 unsigned int tbl_offset;
1721 unsigned int reg_offset;
1722
1723 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1724 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1725
1726 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1727
1728 if (queue == -1) {
1729 /* Clear accepts frame bit at specified Other DA table entry */
1730 omc_table_reg &= ~(0xff << (8 * reg_offset));
1731 } else {
1732 omc_table_reg &= ~(0xff << (8 * reg_offset));
1733 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1734 }
1735
1736 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1737 }
1738
1739 /* The network device supports multicast using two tables:
1740 * 1) Special Multicast Table for MAC addresses of the form
1741 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1742 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1743 * Table entries in the DA-Filter table.
1744 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1745 * is used as an index to the Other Multicast Table entries in the
1746 * DA-Filter table.
1747 */
1748 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1749 int queue)
1750 {
1751 unsigned char crc_result = 0;
1752
1753 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1754 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1755 return 0;
1756 }
1757
1758 crc_result = mvneta_addr_crc(p_addr);
1759 if (queue == -1) {
1760 if (pp->mcast_count[crc_result] == 0) {
1761 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1762 crc_result);
1763 return -EINVAL;
1764 }
1765
1766 pp->mcast_count[crc_result]--;
1767 if (pp->mcast_count[crc_result] != 0) {
1768 netdev_info(pp->dev,
1769 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1770 pp->mcast_count[crc_result], crc_result);
1771 return -EINVAL;
1772 }
1773 } else
1774 pp->mcast_count[crc_result]++;
1775
1776 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1777
1778 return 0;
1779 }
1780
1781 /* Configure Fitering mode of Ethernet port */
1782 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1783 int is_promisc)
1784 {
1785 u32 port_cfg_reg, val;
1786
1787 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1788
1789 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1790
1791 /* Set / Clear UPM bit in port configuration register */
1792 if (is_promisc) {
1793 /* Accept all Unicast addresses */
1794 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1795 val |= MVNETA_FORCE_UNI;
1796 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1797 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1798 } else {
1799 /* Reject all Unicast addresses */
1800 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1801 val &= ~MVNETA_FORCE_UNI;
1802 }
1803
1804 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1805 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1806 }
1807
1808 /* register unicast and multicast addresses */
1809 static void mvneta_set_rx_mode(struct net_device *dev)
1810 {
1811 struct mvneta_port *pp = netdev_priv(dev);
1812 struct netdev_hw_addr *ha;
1813
1814 if (dev->flags & IFF_PROMISC) {
1815 /* Accept all: Multicast + Unicast */
1816 mvneta_rx_unicast_promisc_set(pp, 1);
1817 mvneta_set_ucast_table(pp, rxq_def);
1818 mvneta_set_special_mcast_table(pp, rxq_def);
1819 mvneta_set_other_mcast_table(pp, rxq_def);
1820 } else {
1821 /* Accept single Unicast */
1822 mvneta_rx_unicast_promisc_set(pp, 0);
1823 mvneta_set_ucast_table(pp, -1);
1824 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1825
1826 if (dev->flags & IFF_ALLMULTI) {
1827 /* Accept all multicast */
1828 mvneta_set_special_mcast_table(pp, rxq_def);
1829 mvneta_set_other_mcast_table(pp, rxq_def);
1830 } else {
1831 /* Accept only initialized multicast */
1832 mvneta_set_special_mcast_table(pp, -1);
1833 mvneta_set_other_mcast_table(pp, -1);
1834
1835 if (!netdev_mc_empty(dev)) {
1836 netdev_for_each_mc_addr(ha, dev) {
1837 mvneta_mcast_addr_set(pp, ha->addr,
1838 rxq_def);
1839 }
1840 }
1841 }
1842 }
1843 }
1844
1845 /* Interrupt handling - the callback for request_irq() */
1846 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1847 {
1848 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1849
1850 /* Mask all interrupts */
1851 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1852
1853 napi_schedule(&pp->napi);
1854
1855 return IRQ_HANDLED;
1856 }
1857
1858 /* NAPI handler
1859 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1860 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1861 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1862 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1863 * Each CPU has its own causeRxTx register
1864 */
1865 static int mvneta_poll(struct napi_struct *napi, int budget)
1866 {
1867 int rx_done = 0;
1868 u32 cause_rx_tx;
1869 unsigned long flags;
1870 struct mvneta_port *pp = netdev_priv(napi->dev);
1871
1872 if (!netif_running(pp->dev)) {
1873 napi_complete(napi);
1874 return rx_done;
1875 }
1876
1877 /* Read cause register */
1878 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1879 MVNETA_RX_INTR_MASK(rxq_number);
1880
1881 /* For the case where the last mvneta_poll did not process all
1882 * RX packets
1883 */
1884 cause_rx_tx |= pp->cause_rx_tx;
1885 if (rxq_number > 1) {
1886 while ((cause_rx_tx != 0) && (budget > 0)) {
1887 int count;
1888 struct mvneta_rx_queue *rxq;
1889 /* get rx queue number from cause_rx_tx */
1890 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1891 if (!rxq)
1892 break;
1893
1894 /* process the packet in that rx queue */
1895 count = mvneta_rx(pp, budget, rxq);
1896 rx_done += count;
1897 budget -= count;
1898 if (budget > 0) {
1899 /* set off the rx bit of the
1900 * corresponding bit in the cause rx
1901 * tx register, so that next iteration
1902 * will find the next rx queue where
1903 * packets are received on
1904 */
1905 cause_rx_tx &= ~((1 << rxq->id) << 8);
1906 }
1907 }
1908 } else {
1909 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1910 budget -= rx_done;
1911 }
1912
1913 if (budget > 0) {
1914 cause_rx_tx = 0;
1915 napi_complete(napi);
1916 local_irq_save(flags);
1917 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1918 MVNETA_RX_INTR_MASK(rxq_number));
1919 local_irq_restore(flags);
1920 }
1921
1922 pp->cause_rx_tx = cause_rx_tx;
1923 return rx_done;
1924 }
1925
1926 /* tx done timer callback */
1927 static void mvneta_tx_done_timer_callback(unsigned long data)
1928 {
1929 struct net_device *dev = (struct net_device *)data;
1930 struct mvneta_port *pp = netdev_priv(dev);
1931 int tx_done = 0, tx_todo = 0;
1932
1933 if (!netif_running(dev))
1934 return ;
1935
1936 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
1937
1938 tx_done = mvneta_tx_done_gbe(pp,
1939 (((1 << txq_number) - 1) &
1940 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK),
1941 &tx_todo);
1942 if (tx_todo > 0)
1943 mvneta_add_tx_done_timer(pp);
1944 }
1945
1946 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1947 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1948 int num)
1949 {
1950 struct net_device *dev = pp->dev;
1951 int i;
1952
1953 for (i = 0; i < num; i++) {
1954 struct sk_buff *skb;
1955 struct mvneta_rx_desc *rx_desc;
1956 unsigned long phys_addr;
1957
1958 skb = dev_alloc_skb(pp->pkt_size);
1959 if (!skb) {
1960 netdev_err(dev, "%s:rxq %d, %d of %d buffs filled\n",
1961 __func__, rxq->id, i, num);
1962 break;
1963 }
1964
1965 rx_desc = rxq->descs + i;
1966 memset(rx_desc, 0, sizeof(struct mvneta_rx_desc));
1967 phys_addr = dma_map_single(dev->dev.parent, skb->head,
1968 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1969 DMA_FROM_DEVICE);
1970 if (unlikely(dma_mapping_error(dev->dev.parent, phys_addr))) {
1971 dev_kfree_skb(skb);
1972 break;
1973 }
1974
1975 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)skb);
1976 }
1977
1978 /* Add this number of RX descriptors as non occupied (ready to
1979 * get packets)
1980 */
1981 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1982
1983 return i;
1984 }
1985
1986 /* Free all packets pending transmit from all TXQs and reset TX port */
1987 static void mvneta_tx_reset(struct mvneta_port *pp)
1988 {
1989 int queue;
1990
1991 /* free the skb's in the hal tx ring */
1992 for (queue = 0; queue < txq_number; queue++)
1993 mvneta_txq_done_force(pp, &pp->txqs[queue]);
1994
1995 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1996 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1997 }
1998
1999 static void mvneta_rx_reset(struct mvneta_port *pp)
2000 {
2001 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2002 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2003 }
2004
2005 /* Rx/Tx queue initialization/cleanup methods */
2006
2007 /* Create a specified RX queue */
2008 static int mvneta_rxq_init(struct mvneta_port *pp,
2009 struct mvneta_rx_queue *rxq)
2010
2011 {
2012 rxq->size = pp->rx_ring_size;
2013
2014 /* Allocate memory for RX descriptors */
2015 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2016 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2017 &rxq->descs_phys, GFP_KERNEL);
2018 if (rxq->descs == NULL)
2019 return -ENOMEM;
2020
2021 BUG_ON(rxq->descs !=
2022 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2023
2024 rxq->last_desc = rxq->size - 1;
2025
2026 /* Set Rx descriptors queue starting address */
2027 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2028 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2029
2030 /* Set Offset */
2031 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2032
2033 /* Set coalescing pkts and time */
2034 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2035 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2036
2037 /* Fill RXQ with buffers from RX pool */
2038 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2039 mvneta_rxq_bm_disable(pp, rxq);
2040 mvneta_rxq_fill(pp, rxq, rxq->size);
2041
2042 return 0;
2043 }
2044
2045 /* Cleanup Rx queue */
2046 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2047 struct mvneta_rx_queue *rxq)
2048 {
2049 mvneta_rxq_drop_pkts(pp, rxq);
2050
2051 if (rxq->descs)
2052 dma_free_coherent(pp->dev->dev.parent,
2053 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2054 rxq->descs,
2055 rxq->descs_phys);
2056
2057 rxq->descs = NULL;
2058 rxq->last_desc = 0;
2059 rxq->next_desc_to_proc = 0;
2060 rxq->descs_phys = 0;
2061 }
2062
2063 /* Create and initialize a tx queue */
2064 static int mvneta_txq_init(struct mvneta_port *pp,
2065 struct mvneta_tx_queue *txq)
2066 {
2067 txq->size = pp->tx_ring_size;
2068
2069 /* Allocate memory for TX descriptors */
2070 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2071 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2072 &txq->descs_phys, GFP_KERNEL);
2073 if (txq->descs == NULL)
2074 return -ENOMEM;
2075
2076 /* Make sure descriptor address is cache line size aligned */
2077 BUG_ON(txq->descs !=
2078 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2079
2080 txq->last_desc = txq->size - 1;
2081
2082 /* Set maximum bandwidth for enabled TXQs */
2083 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2084 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2085
2086 /* Set Tx descriptors queue starting address */
2087 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2088 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2089
2090 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2091 if (txq->tx_skb == NULL) {
2092 dma_free_coherent(pp->dev->dev.parent,
2093 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2094 txq->descs, txq->descs_phys);
2095 return -ENOMEM;
2096 }
2097 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2098
2099 return 0;
2100 }
2101
2102 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2103 static void mvneta_txq_deinit(struct mvneta_port *pp,
2104 struct mvneta_tx_queue *txq)
2105 {
2106 kfree(txq->tx_skb);
2107
2108 if (txq->descs)
2109 dma_free_coherent(pp->dev->dev.parent,
2110 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2111 txq->descs, txq->descs_phys);
2112
2113 txq->descs = NULL;
2114 txq->last_desc = 0;
2115 txq->next_desc_to_proc = 0;
2116 txq->descs_phys = 0;
2117
2118 /* Set minimum bandwidth for disabled TXQs */
2119 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2120 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2121
2122 /* Set Tx descriptors queue starting address and size */
2123 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2124 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2125 }
2126
2127 /* Cleanup all Tx queues */
2128 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2129 {
2130 int queue;
2131
2132 for (queue = 0; queue < txq_number; queue++)
2133 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2134 }
2135
2136 /* Cleanup all Rx queues */
2137 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2138 {
2139 int queue;
2140
2141 for (queue = 0; queue < rxq_number; queue++)
2142 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2143 }
2144
2145
2146 /* Init all Rx queues */
2147 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2148 {
2149 int queue;
2150
2151 for (queue = 0; queue < rxq_number; queue++) {
2152 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2153 if (err) {
2154 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2155 __func__, queue);
2156 mvneta_cleanup_rxqs(pp);
2157 return err;
2158 }
2159 }
2160
2161 return 0;
2162 }
2163
2164 /* Init all tx queues */
2165 static int mvneta_setup_txqs(struct mvneta_port *pp)
2166 {
2167 int queue;
2168
2169 for (queue = 0; queue < txq_number; queue++) {
2170 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2171 if (err) {
2172 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2173 __func__, queue);
2174 mvneta_cleanup_txqs(pp);
2175 return err;
2176 }
2177 }
2178
2179 return 0;
2180 }
2181
2182 static void mvneta_start_dev(struct mvneta_port *pp)
2183 {
2184 mvneta_max_rx_size_set(pp, pp->pkt_size);
2185 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2186
2187 /* start the Rx/Tx activity */
2188 mvneta_port_enable(pp);
2189
2190 /* Enable polling on the port */
2191 napi_enable(&pp->napi);
2192
2193 /* Unmask interrupts */
2194 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2195 MVNETA_RX_INTR_MASK(rxq_number));
2196
2197 phy_start(pp->phy_dev);
2198 netif_tx_start_all_queues(pp->dev);
2199 }
2200
2201 static void mvneta_stop_dev(struct mvneta_port *pp)
2202 {
2203 phy_stop(pp->phy_dev);
2204
2205 napi_disable(&pp->napi);
2206
2207 netif_carrier_off(pp->dev);
2208
2209 mvneta_port_down(pp);
2210 netif_tx_stop_all_queues(pp->dev);
2211
2212 /* Stop the port activity */
2213 mvneta_port_disable(pp);
2214
2215 /* Clear all ethernet port interrupts */
2216 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2217 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2218
2219 /* Mask all ethernet port interrupts */
2220 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2221 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2222 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2223
2224 mvneta_tx_reset(pp);
2225 mvneta_rx_reset(pp);
2226 }
2227
2228 /* tx timeout callback - display a message and stop/start the network device */
2229 static void mvneta_tx_timeout(struct net_device *dev)
2230 {
2231 struct mvneta_port *pp = netdev_priv(dev);
2232
2233 netdev_info(dev, "tx timeout\n");
2234 mvneta_stop_dev(pp);
2235 mvneta_start_dev(pp);
2236 }
2237
2238 /* Return positive if MTU is valid */
2239 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2240 {
2241 if (mtu < 68) {
2242 netdev_err(dev, "cannot change mtu to less than 68\n");
2243 return -EINVAL;
2244 }
2245
2246 /* 9676 == 9700 - 20 and rounding to 8 */
2247 if (mtu > 9676) {
2248 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2249 mtu = 9676;
2250 }
2251
2252 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2253 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2254 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2255 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2256 }
2257
2258 return mtu;
2259 }
2260
2261 /* Change the device mtu */
2262 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2263 {
2264 struct mvneta_port *pp = netdev_priv(dev);
2265 int ret;
2266
2267 mtu = mvneta_check_mtu_valid(dev, mtu);
2268 if (mtu < 0)
2269 return -EINVAL;
2270
2271 dev->mtu = mtu;
2272
2273 if (!netif_running(dev))
2274 return 0;
2275
2276 /* The interface is running, so we have to force a
2277 * reallocation of the RXQs
2278 */
2279 mvneta_stop_dev(pp);
2280
2281 mvneta_cleanup_txqs(pp);
2282 mvneta_cleanup_rxqs(pp);
2283
2284 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2285
2286 ret = mvneta_setup_rxqs(pp);
2287 if (ret) {
2288 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2289 return ret;
2290 }
2291
2292 mvneta_setup_txqs(pp);
2293
2294 mvneta_start_dev(pp);
2295 mvneta_port_up(pp);
2296
2297 return 0;
2298 }
2299
2300 /* Get mac address */
2301 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2302 {
2303 u32 mac_addr_l, mac_addr_h;
2304
2305 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2306 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2307 addr[0] = (mac_addr_h >> 24) & 0xFF;
2308 addr[1] = (mac_addr_h >> 16) & 0xFF;
2309 addr[2] = (mac_addr_h >> 8) & 0xFF;
2310 addr[3] = mac_addr_h & 0xFF;
2311 addr[4] = (mac_addr_l >> 8) & 0xFF;
2312 addr[5] = mac_addr_l & 0xFF;
2313 }
2314
2315 /* Handle setting mac address */
2316 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2317 {
2318 struct mvneta_port *pp = netdev_priv(dev);
2319 u8 *mac = addr + 2;
2320 int i;
2321
2322 if (netif_running(dev))
2323 return -EBUSY;
2324
2325 /* Remove previous address table entry */
2326 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2327
2328 /* Set new addr in hw */
2329 mvneta_mac_addr_set(pp, mac, rxq_def);
2330
2331 /* Set addr in the device */
2332 for (i = 0; i < ETH_ALEN; i++)
2333 dev->dev_addr[i] = mac[i];
2334
2335 return 0;
2336 }
2337
2338 static void mvneta_adjust_link(struct net_device *ndev)
2339 {
2340 struct mvneta_port *pp = netdev_priv(ndev);
2341 struct phy_device *phydev = pp->phy_dev;
2342 int status_change = 0;
2343
2344 if (phydev->link) {
2345 if ((pp->speed != phydev->speed) ||
2346 (pp->duplex != phydev->duplex)) {
2347 u32 val;
2348
2349 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2350 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2351 MVNETA_GMAC_CONFIG_GMII_SPEED |
2352 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2353 MVNETA_GMAC_AN_SPEED_EN |
2354 MVNETA_GMAC_AN_DUPLEX_EN);
2355
2356 if (phydev->duplex)
2357 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2358
2359 if (phydev->speed == SPEED_1000)
2360 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2361 else if (phydev->speed == SPEED_100)
2362 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2363
2364 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2365
2366 pp->duplex = phydev->duplex;
2367 pp->speed = phydev->speed;
2368 }
2369 }
2370
2371 if (phydev->link != pp->link) {
2372 if (!phydev->link) {
2373 pp->duplex = -1;
2374 pp->speed = 0;
2375 }
2376
2377 pp->link = phydev->link;
2378 status_change = 1;
2379 }
2380
2381 if (status_change) {
2382 if (phydev->link) {
2383 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2384 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2385 MVNETA_GMAC_FORCE_LINK_DOWN);
2386 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2387 mvneta_port_up(pp);
2388 netdev_info(pp->dev, "link up\n");
2389 } else {
2390 mvneta_port_down(pp);
2391 netdev_info(pp->dev, "link down\n");
2392 }
2393 }
2394 }
2395
2396 static int mvneta_mdio_probe(struct mvneta_port *pp)
2397 {
2398 struct phy_device *phy_dev;
2399
2400 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2401 pp->phy_interface);
2402 if (!phy_dev) {
2403 netdev_err(pp->dev, "could not find the PHY\n");
2404 return -ENODEV;
2405 }
2406
2407 phy_dev->supported &= PHY_GBIT_FEATURES;
2408 phy_dev->advertising = phy_dev->supported;
2409
2410 pp->phy_dev = phy_dev;
2411 pp->link = 0;
2412 pp->duplex = 0;
2413 pp->speed = 0;
2414
2415 return 0;
2416 }
2417
2418 static void mvneta_mdio_remove(struct mvneta_port *pp)
2419 {
2420 phy_disconnect(pp->phy_dev);
2421 pp->phy_dev = NULL;
2422 }
2423
2424 static int mvneta_open(struct net_device *dev)
2425 {
2426 struct mvneta_port *pp = netdev_priv(dev);
2427 int ret;
2428
2429 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2430
2431 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2432
2433 ret = mvneta_setup_rxqs(pp);
2434 if (ret)
2435 return ret;
2436
2437 ret = mvneta_setup_txqs(pp);
2438 if (ret)
2439 goto err_cleanup_rxqs;
2440
2441 /* Connect to port interrupt line */
2442 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2443 MVNETA_DRIVER_NAME, pp);
2444 if (ret) {
2445 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2446 goto err_cleanup_txqs;
2447 }
2448
2449 /* In default link is down */
2450 netif_carrier_off(pp->dev);
2451
2452 ret = mvneta_mdio_probe(pp);
2453 if (ret < 0) {
2454 netdev_err(dev, "cannot probe MDIO bus\n");
2455 goto err_free_irq;
2456 }
2457
2458 mvneta_start_dev(pp);
2459
2460 return 0;
2461
2462 err_free_irq:
2463 free_irq(pp->dev->irq, pp);
2464 err_cleanup_txqs:
2465 mvneta_cleanup_txqs(pp);
2466 err_cleanup_rxqs:
2467 mvneta_cleanup_rxqs(pp);
2468 return ret;
2469 }
2470
2471 /* Stop the port, free port interrupt line */
2472 static int mvneta_stop(struct net_device *dev)
2473 {
2474 struct mvneta_port *pp = netdev_priv(dev);
2475
2476 mvneta_stop_dev(pp);
2477 mvneta_mdio_remove(pp);
2478 free_irq(dev->irq, pp);
2479 mvneta_cleanup_rxqs(pp);
2480 mvneta_cleanup_txqs(pp);
2481 del_timer(&pp->tx_done_timer);
2482 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2483
2484 return 0;
2485 }
2486
2487 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2488 {
2489 struct mvneta_port *pp = netdev_priv(dev);
2490 int ret;
2491
2492 if (!pp->phy_dev)
2493 return -ENOTSUPP;
2494
2495 ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2496 if (!ret)
2497 mvneta_adjust_link(dev);
2498
2499 return ret;
2500 }
2501
2502 /* Ethtool methods */
2503
2504 /* Get settings (phy address, speed) for ethtools */
2505 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2506 {
2507 struct mvneta_port *pp = netdev_priv(dev);
2508
2509 if (!pp->phy_dev)
2510 return -ENODEV;
2511
2512 return phy_ethtool_gset(pp->phy_dev, cmd);
2513 }
2514
2515 /* Set settings (phy address, speed) for ethtools */
2516 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2517 {
2518 struct mvneta_port *pp = netdev_priv(dev);
2519
2520 if (!pp->phy_dev)
2521 return -ENODEV;
2522
2523 return phy_ethtool_sset(pp->phy_dev, cmd);
2524 }
2525
2526 /* Set interrupt coalescing for ethtools */
2527 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2528 struct ethtool_coalesce *c)
2529 {
2530 struct mvneta_port *pp = netdev_priv(dev);
2531 int queue;
2532
2533 for (queue = 0; queue < rxq_number; queue++) {
2534 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2535 rxq->time_coal = c->rx_coalesce_usecs;
2536 rxq->pkts_coal = c->rx_max_coalesced_frames;
2537 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2538 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2539 }
2540
2541 for (queue = 0; queue < txq_number; queue++) {
2542 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2543 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2544 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2545 }
2546
2547 return 0;
2548 }
2549
2550 /* get coalescing for ethtools */
2551 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2552 struct ethtool_coalesce *c)
2553 {
2554 struct mvneta_port *pp = netdev_priv(dev);
2555
2556 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2557 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2558
2559 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2560 return 0;
2561 }
2562
2563
2564 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2565 struct ethtool_drvinfo *drvinfo)
2566 {
2567 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2568 sizeof(drvinfo->driver));
2569 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2570 sizeof(drvinfo->version));
2571 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2572 sizeof(drvinfo->bus_info));
2573 }
2574
2575
2576 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2577 struct ethtool_ringparam *ring)
2578 {
2579 struct mvneta_port *pp = netdev_priv(netdev);
2580
2581 ring->rx_max_pending = MVNETA_MAX_RXD;
2582 ring->tx_max_pending = MVNETA_MAX_TXD;
2583 ring->rx_pending = pp->rx_ring_size;
2584 ring->tx_pending = pp->tx_ring_size;
2585 }
2586
2587 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2588 struct ethtool_ringparam *ring)
2589 {
2590 struct mvneta_port *pp = netdev_priv(dev);
2591
2592 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2593 return -EINVAL;
2594 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2595 ring->rx_pending : MVNETA_MAX_RXD;
2596 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2597 ring->tx_pending : MVNETA_MAX_TXD;
2598
2599 if (netif_running(dev)) {
2600 mvneta_stop(dev);
2601 if (mvneta_open(dev)) {
2602 netdev_err(dev,
2603 "error on opening device after ring param change\n");
2604 return -ENOMEM;
2605 }
2606 }
2607
2608 return 0;
2609 }
2610
2611 static const struct net_device_ops mvneta_netdev_ops = {
2612 .ndo_open = mvneta_open,
2613 .ndo_stop = mvneta_stop,
2614 .ndo_start_xmit = mvneta_tx,
2615 .ndo_set_rx_mode = mvneta_set_rx_mode,
2616 .ndo_set_mac_address = mvneta_set_mac_addr,
2617 .ndo_change_mtu = mvneta_change_mtu,
2618 .ndo_tx_timeout = mvneta_tx_timeout,
2619 .ndo_get_stats64 = mvneta_get_stats64,
2620 .ndo_do_ioctl = mvneta_ioctl,
2621 };
2622
2623 const struct ethtool_ops mvneta_eth_tool_ops = {
2624 .get_link = ethtool_op_get_link,
2625 .get_settings = mvneta_ethtool_get_settings,
2626 .set_settings = mvneta_ethtool_set_settings,
2627 .set_coalesce = mvneta_ethtool_set_coalesce,
2628 .get_coalesce = mvneta_ethtool_get_coalesce,
2629 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2630 .get_ringparam = mvneta_ethtool_get_ringparam,
2631 .set_ringparam = mvneta_ethtool_set_ringparam,
2632 };
2633
2634 /* Initialize hw */
2635 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2636 {
2637 int queue;
2638
2639 /* Disable port */
2640 mvneta_port_disable(pp);
2641
2642 /* Set port default values */
2643 mvneta_defaults_set(pp);
2644
2645 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2646 GFP_KERNEL);
2647 if (!pp->txqs)
2648 return -ENOMEM;
2649
2650 /* Initialize TX descriptor rings */
2651 for (queue = 0; queue < txq_number; queue++) {
2652 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2653 txq->id = queue;
2654 txq->size = pp->tx_ring_size;
2655 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2656 }
2657
2658 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2659 GFP_KERNEL);
2660 if (!pp->rxqs) {
2661 kfree(pp->txqs);
2662 return -ENOMEM;
2663 }
2664
2665 /* Create Rx descriptor rings */
2666 for (queue = 0; queue < rxq_number; queue++) {
2667 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2668 rxq->id = queue;
2669 rxq->size = pp->rx_ring_size;
2670 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2671 rxq->time_coal = MVNETA_RX_COAL_USEC;
2672 }
2673
2674 return 0;
2675 }
2676
2677 static void mvneta_deinit(struct mvneta_port *pp)
2678 {
2679 kfree(pp->txqs);
2680 kfree(pp->rxqs);
2681 }
2682
2683 /* platform glue : initialize decoding windows */
2684 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2685 const struct mbus_dram_target_info *dram)
2686 {
2687 u32 win_enable;
2688 u32 win_protect;
2689 int i;
2690
2691 for (i = 0; i < 6; i++) {
2692 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2693 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2694
2695 if (i < 4)
2696 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2697 }
2698
2699 win_enable = 0x3f;
2700 win_protect = 0;
2701
2702 for (i = 0; i < dram->num_cs; i++) {
2703 const struct mbus_dram_window *cs = dram->cs + i;
2704 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2705 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2706
2707 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2708 (cs->size - 1) & 0xffff0000);
2709
2710 win_enable &= ~(1 << i);
2711 win_protect |= 3 << (2 * i);
2712 }
2713
2714 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2715 }
2716
2717 /* Power up the port */
2718 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2719 {
2720 u32 val;
2721
2722 /* MAC Cause register should be cleared */
2723 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2724
2725 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2726 mvneta_port_sgmii_config(pp);
2727
2728 mvneta_gmac_rgmii_set(pp, 1);
2729
2730 /* Cancel Port Reset */
2731 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2732 val &= ~MVNETA_GMAC2_PORT_RESET;
2733 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2734
2735 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2736 MVNETA_GMAC2_PORT_RESET) != 0)
2737 continue;
2738 }
2739
2740 /* Device initialization routine */
2741 static int mvneta_probe(struct platform_device *pdev)
2742 {
2743 const struct mbus_dram_target_info *dram_target_info;
2744 struct device_node *dn = pdev->dev.of_node;
2745 struct device_node *phy_node;
2746 u32 phy_addr;
2747 struct mvneta_port *pp;
2748 struct net_device *dev;
2749 const char *dt_mac_addr;
2750 char hw_mac_addr[ETH_ALEN];
2751 const char *mac_from;
2752 int phy_mode;
2753 int err;
2754
2755 /* Our multiqueue support is not complete, so for now, only
2756 * allow the usage of the first RX queue
2757 */
2758 if (rxq_def != 0) {
2759 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2760 return -EINVAL;
2761 }
2762
2763 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2764 if (!dev)
2765 return -ENOMEM;
2766
2767 dev->irq = irq_of_parse_and_map(dn, 0);
2768 if (dev->irq == 0) {
2769 err = -EINVAL;
2770 goto err_free_netdev;
2771 }
2772
2773 phy_node = of_parse_phandle(dn, "phy", 0);
2774 if (!phy_node) {
2775 dev_err(&pdev->dev, "no associated PHY\n");
2776 err = -ENODEV;
2777 goto err_free_irq;
2778 }
2779
2780 phy_mode = of_get_phy_mode(dn);
2781 if (phy_mode < 0) {
2782 dev_err(&pdev->dev, "incorrect phy-mode\n");
2783 err = -EINVAL;
2784 goto err_free_irq;
2785 }
2786
2787 dev->tx_queue_len = MVNETA_MAX_TXD;
2788 dev->watchdog_timeo = 5 * HZ;
2789 dev->netdev_ops = &mvneta_netdev_ops;
2790
2791 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2792
2793 pp = netdev_priv(dev);
2794
2795 pp->weight = MVNETA_RX_POLL_WEIGHT;
2796 pp->phy_node = phy_node;
2797 pp->phy_interface = phy_mode;
2798
2799 pp->clk = devm_clk_get(&pdev->dev, NULL);
2800 if (IS_ERR(pp->clk)) {
2801 err = PTR_ERR(pp->clk);
2802 goto err_free_irq;
2803 }
2804
2805 clk_prepare_enable(pp->clk);
2806
2807 pp->base = of_iomap(dn, 0);
2808 if (pp->base == NULL) {
2809 err = -ENOMEM;
2810 goto err_clk;
2811 }
2812
2813 dt_mac_addr = of_get_mac_address(dn);
2814 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
2815 mac_from = "device tree";
2816 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
2817 } else {
2818 mvneta_get_mac_addr(pp, hw_mac_addr);
2819 if (is_valid_ether_addr(hw_mac_addr)) {
2820 mac_from = "hardware";
2821 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
2822 } else {
2823 mac_from = "random";
2824 eth_hw_addr_random(dev);
2825 }
2826 }
2827
2828 pp->tx_done_timer.data = (unsigned long)dev;
2829 pp->tx_done_timer.function = mvneta_tx_done_timer_callback;
2830 init_timer(&pp->tx_done_timer);
2831 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
2832
2833 pp->tx_ring_size = MVNETA_MAX_TXD;
2834 pp->rx_ring_size = MVNETA_MAX_RXD;
2835
2836 pp->dev = dev;
2837 SET_NETDEV_DEV(dev, &pdev->dev);
2838
2839 err = mvneta_init(pp, phy_addr);
2840 if (err < 0) {
2841 dev_err(&pdev->dev, "can't init eth hal\n");
2842 goto err_unmap;
2843 }
2844 mvneta_port_power_up(pp, phy_mode);
2845
2846 dram_target_info = mv_mbus_dram_info();
2847 if (dram_target_info)
2848 mvneta_conf_mbus_windows(pp, dram_target_info);
2849
2850 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2851
2852 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2853 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2854 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2855 dev->priv_flags |= IFF_UNICAST_FLT;
2856
2857 err = register_netdev(dev);
2858 if (err < 0) {
2859 dev_err(&pdev->dev, "failed to register\n");
2860 goto err_deinit;
2861 }
2862
2863 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
2864 dev->dev_addr);
2865
2866 platform_set_drvdata(pdev, pp->dev);
2867
2868 return 0;
2869
2870 err_deinit:
2871 mvneta_deinit(pp);
2872 err_unmap:
2873 iounmap(pp->base);
2874 err_clk:
2875 clk_disable_unprepare(pp->clk);
2876 err_free_irq:
2877 irq_dispose_mapping(dev->irq);
2878 err_free_netdev:
2879 free_netdev(dev);
2880 return err;
2881 }
2882
2883 /* Device removal routine */
2884 static int mvneta_remove(struct platform_device *pdev)
2885 {
2886 struct net_device *dev = platform_get_drvdata(pdev);
2887 struct mvneta_port *pp = netdev_priv(dev);
2888
2889 unregister_netdev(dev);
2890 mvneta_deinit(pp);
2891 clk_disable_unprepare(pp->clk);
2892 iounmap(pp->base);
2893 irq_dispose_mapping(dev->irq);
2894 free_netdev(dev);
2895
2896 return 0;
2897 }
2898
2899 static const struct of_device_id mvneta_match[] = {
2900 { .compatible = "marvell,armada-370-neta" },
2901 { }
2902 };
2903 MODULE_DEVICE_TABLE(of, mvneta_match);
2904
2905 static struct platform_driver mvneta_driver = {
2906 .probe = mvneta_probe,
2907 .remove = mvneta_remove,
2908 .driver = {
2909 .name = MVNETA_DRIVER_NAME,
2910 .of_match_table = mvneta_match,
2911 },
2912 };
2913
2914 module_platform_driver(mvneta_driver);
2915
2916 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2917 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2918 MODULE_LICENSE("GPL");
2919
2920 module_param(rxq_number, int, S_IRUGO);
2921 module_param(txq_number, int, S_IRUGO);
2922
2923 module_param(rxq_def, int, S_IRUGO);
Linux with added FPC-III support