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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_hw.c
blob8375cbde996976047475b9c5e6c16f33fd365df4
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26 #include <linux/slab.h>
27 #include "netxen_nic.h"
28 #include "netxen_nic_hw.h"
29
30 #include <net/ip.h>
31
32 #define MASK(n) ((1ULL<<(n))-1)
33 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
35 #define MS_WIN(addr) (addr & 0x0ffc0000)
36
37 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39 #define CRB_BLK(off) ((off >> 20) & 0x3f)
40 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41 #define CRB_WINDOW_2M (0x130060)
42 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43 #define CRB_INDIRECT_2M (0x1e0000UL)
44
45 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49 #ifndef readq
50 static inline u64 readq(void __iomem *addr)
51 {
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
53 }
54 #endif
55
56 #ifndef writeq
57 static inline void writeq(u64 val, void __iomem *addr)
58 {
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
61 }
62 #endif
63
64 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base0 + (off))
66 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
68 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
70
71 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
72 unsigned long off)
73 {
74 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
75 return PCI_OFFSET_FIRST_RANGE(adapter, off);
76
77 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
78 return PCI_OFFSET_SECOND_RANGE(adapter, off);
79
80 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
81 return PCI_OFFSET_THIRD_RANGE(adapter, off);
82
83 return NULL;
84 }
85
86 static crb_128M_2M_block_map_t
87 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
88 {{{0, 0, 0, 0} } }, /* 0: PCI */
89 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
90 {1, 0x0110000, 0x0120000, 0x130000},
91 {1, 0x0120000, 0x0122000, 0x124000},
92 {1, 0x0130000, 0x0132000, 0x126000},
93 {1, 0x0140000, 0x0142000, 0x128000},
94 {1, 0x0150000, 0x0152000, 0x12a000},
95 {1, 0x0160000, 0x0170000, 0x110000},
96 {1, 0x0170000, 0x0172000, 0x12e000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {1, 0x01e0000, 0x01e0800, 0x122000},
104 {0, 0x0000000, 0x0000000, 0x000000} } },
105 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
106 {{{0, 0, 0, 0} } }, /* 3: */
107 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
108 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
109 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
110 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
111 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x08f0000, 0x08f2000, 0x172000} } },
127 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x09f0000, 0x09f2000, 0x176000} } },
143 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
159 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
175 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
176 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
177 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
178 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
179 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
180 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
181 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
182 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
183 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
184 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
185 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
186 {{{0, 0, 0, 0} } }, /* 23: */
187 {{{0, 0, 0, 0} } }, /* 24: */
188 {{{0, 0, 0, 0} } }, /* 25: */
189 {{{0, 0, 0, 0} } }, /* 26: */
190 {{{0, 0, 0, 0} } }, /* 27: */
191 {{{0, 0, 0, 0} } }, /* 28: */
192 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
193 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
194 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
195 {{{0} } }, /* 32: PCI */
196 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
197 {1, 0x2110000, 0x2120000, 0x130000},
198 {1, 0x2120000, 0x2122000, 0x124000},
199 {1, 0x2130000, 0x2132000, 0x126000},
200 {1, 0x2140000, 0x2142000, 0x128000},
201 {1, 0x2150000, 0x2152000, 0x12a000},
202 {1, 0x2160000, 0x2170000, 0x110000},
203 {1, 0x2170000, 0x2172000, 0x12e000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000} } },
212 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
213 {{{0} } }, /* 35: */
214 {{{0} } }, /* 36: */
215 {{{0} } }, /* 37: */
216 {{{0} } }, /* 38: */
217 {{{0} } }, /* 39: */
218 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
219 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
220 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
221 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
222 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
223 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
224 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
225 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
226 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
227 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
228 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
229 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
230 {{{0} } }, /* 52: */
231 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
232 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
233 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
234 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
235 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
236 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
237 {{{0} } }, /* 59: I2C0 */
238 {{{0} } }, /* 60: I2C1 */
239 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
240 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
241 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
242 };
243
244 /*
245 * top 12 bits of crb internal address (hub, agent)
246 */
247 static unsigned crb_hub_agt[64] =
248 {
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
252 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
253 0,
254 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
255 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
256 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
261 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
262 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
263 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
265 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
276 0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
278 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
281 0,
282 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
283 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
284 0,
285 0,
286 0,
287 0,
288 0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
290 0,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
298 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
299 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
300 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
301 0,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
304 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
305 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
306 0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
308 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
310 0,
311 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
312 0,
313 };
314
315 /* PCI Windowing for DDR regions. */
316
317 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
318
319 #define NETXEN_PCIE_SEM_TIMEOUT 10000
320
321 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
322
323 int
324 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
325 {
326 int done = 0, timeout = 0;
327
328 while (!done) {
329 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
330 if (done == 1)
331 break;
332 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
333 return -EIO;
334 msleep(1);
335 }
336
337 if (id_reg)
338 NXWR32(adapter, id_reg, adapter->portnum);
339
340 return 0;
341 }
342
343 void
344 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
345 {
346 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
347 }
348
349 static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
350 {
351 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
352 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
353 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
354 }
355
356 return 0;
357 }
358
359 /* Disable an XG interface */
360 static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
361 {
362 __u32 mac_cfg;
363 u32 port = adapter->physical_port;
364
365 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
366 return 0;
367
368 if (port >= NETXEN_NIU_MAX_XG_PORTS)
369 return -EINVAL;
370
371 mac_cfg = 0;
372 if (NXWR32(adapter,
373 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
374 return -EIO;
375 return 0;
376 }
377
378 #define NETXEN_UNICAST_ADDR(port, index) \
379 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
380 #define NETXEN_MCAST_ADDR(port, index) \
381 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
382 #define MAC_HI(addr) \
383 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
384 #define MAC_LO(addr) \
385 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
386
387 static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
388 {
389 u32 mac_cfg;
390 u32 cnt = 0;
391 __u32 reg = 0x0200;
392 u32 port = adapter->physical_port;
393 u16 board_type = adapter->ahw.board_type;
394
395 if (port >= NETXEN_NIU_MAX_XG_PORTS)
396 return -EINVAL;
397
398 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
399 mac_cfg &= ~0x4;
400 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
401
402 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
403 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
404 reg = (0x20 << port);
405
406 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
407
408 mdelay(10);
409
410 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
411 mdelay(10);
412
413 if (cnt < 20) {
414
415 reg = NXRD32(adapter,
416 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
417
418 if (mode == NETXEN_NIU_PROMISC_MODE)
419 reg = (reg | 0x2000UL);
420 else
421 reg = (reg & ~0x2000UL);
422
423 if (mode == NETXEN_NIU_ALLMULTI_MODE)
424 reg = (reg | 0x1000UL);
425 else
426 reg = (reg & ~0x1000UL);
427
428 NXWR32(adapter,
429 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
430 }
431
432 mac_cfg |= 0x4;
433 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
434
435 return 0;
436 }
437
438 static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
439 {
440 u32 mac_hi, mac_lo;
441 u32 reg_hi, reg_lo;
442
443 u8 phy = adapter->physical_port;
444
445 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
446 return -EINVAL;
447
448 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
449 mac_hi = addr[2] | ((u32)addr[3] << 8) |
450 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
451
452 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
453 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
454
455 /* write twice to flush */
456 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
457 return -EIO;
458 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
459 return -EIO;
460
461 return 0;
462 }
463
464 static int
465 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
466 {
467 u32 val = 0;
468 u16 port = adapter->physical_port;
469 u8 *addr = adapter->mac_addr;
470
471 if (adapter->mc_enabled)
472 return 0;
473
474 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
475 val |= (1UL << (28+port));
476 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
477
478 /* add broadcast addr to filter */
479 val = 0xffffff;
480 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
481 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
482
483 /* add station addr to filter */
484 val = MAC_HI(addr);
485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
486 val = MAC_LO(addr);
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
488
489 adapter->mc_enabled = 1;
490 return 0;
491 }
492
493 static int
494 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
495 {
496 u32 val = 0;
497 u16 port = adapter->physical_port;
498 u8 *addr = adapter->mac_addr;
499
500 if (!adapter->mc_enabled)
501 return 0;
502
503 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
504 val &= ~(1UL << (28+port));
505 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
506
507 val = MAC_HI(addr);
508 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
509 val = MAC_LO(addr);
510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
511
512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
513 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
514
515 adapter->mc_enabled = 0;
516 return 0;
517 }
518
519 static int
520 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
521 int index, u8 *addr)
522 {
523 u32 hi = 0, lo = 0;
524 u16 port = adapter->physical_port;
525
526 lo = MAC_LO(addr);
527 hi = MAC_HI(addr);
528
529 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
530 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
531
532 return 0;
533 }
534
535 static void netxen_p2_nic_set_multi(struct net_device *netdev)
536 {
537 struct netxen_adapter *adapter = netdev_priv(netdev);
538 struct netdev_hw_addr *ha;
539 u8 null_addr[ETH_ALEN];
540 int i;
541
542 memset(null_addr, 0, ETH_ALEN);
543
544 if (netdev->flags & IFF_PROMISC) {
545
546 adapter->set_promisc(adapter,
547 NETXEN_NIU_PROMISC_MODE);
548
549 /* Full promiscuous mode */
550 netxen_nic_disable_mcast_filter(adapter);
551
552 return;
553 }
554
555 if (netdev_mc_empty(netdev)) {
556 adapter->set_promisc(adapter,
557 NETXEN_NIU_NON_PROMISC_MODE);
558 netxen_nic_disable_mcast_filter(adapter);
559 return;
560 }
561
562 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
563 if (netdev->flags & IFF_ALLMULTI ||
564 netdev_mc_count(netdev) > adapter->max_mc_count) {
565 netxen_nic_disable_mcast_filter(adapter);
566 return;
567 }
568
569 netxen_nic_enable_mcast_filter(adapter);
570
571 i = 0;
572 netdev_for_each_mc_addr(ha, netdev)
573 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
574
575 /* Clear out remaining addresses */
576 while (i < adapter->max_mc_count)
577 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
578 }
579
580 static int
581 netxen_send_cmd_descs(struct netxen_adapter *adapter,
582 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
583 {
584 u32 i, producer, consumer;
585 struct netxen_cmd_buffer *pbuf;
586 struct cmd_desc_type0 *cmd_desc;
587 struct nx_host_tx_ring *tx_ring;
588
589 i = 0;
590
591 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
592 return -EIO;
593
594 tx_ring = adapter->tx_ring;
595 __netif_tx_lock_bh(tx_ring->txq);
596
597 producer = tx_ring->producer;
598 consumer = tx_ring->sw_consumer;
599
600 if (nr_desc >= netxen_tx_avail(tx_ring)) {
601 netif_tx_stop_queue(tx_ring->txq);
602 smp_mb();
603 if (netxen_tx_avail(tx_ring) > nr_desc) {
604 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
605 netif_tx_wake_queue(tx_ring->txq);
606 } else {
607 __netif_tx_unlock_bh(tx_ring->txq);
608 return -EBUSY;
609 }
610 }
611
612 do {
613 cmd_desc = &cmd_desc_arr[i];
614
615 pbuf = &tx_ring->cmd_buf_arr[producer];
616 pbuf->skb = NULL;
617 pbuf->frag_count = 0;
618
619 memcpy(&tx_ring->desc_head[producer],
620 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
621
622 producer = get_next_index(producer, tx_ring->num_desc);
623 i++;
624
625 } while (i != nr_desc);
626
627 tx_ring->producer = producer;
628
629 netxen_nic_update_cmd_producer(adapter, tx_ring);
630
631 __netif_tx_unlock_bh(tx_ring->txq);
632
633 return 0;
634 }
635
636 static int
637 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
638 {
639 nx_nic_req_t req;
640 nx_mac_req_t *mac_req;
641 u64 word;
642
643 memset(&req, 0, sizeof(nx_nic_req_t));
644 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
645
646 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
647 req.req_hdr = cpu_to_le64(word);
648
649 mac_req = (nx_mac_req_t *)&req.words[0];
650 mac_req->op = op;
651 memcpy(mac_req->mac_addr, addr, 6);
652
653 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
654 }
655
656 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
657 const u8 *addr, struct list_head *del_list)
658 {
659 struct list_head *head;
660 nx_mac_list_t *cur;
661
662 /* look up if already exists */
663 list_for_each(head, del_list) {
664 cur = list_entry(head, nx_mac_list_t, list);
665
666 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
667 list_move_tail(head, &adapter->mac_list);
668 return 0;
669 }
670 }
671
672 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
673 if (cur == NULL)
674 return -ENOMEM;
675
676 memcpy(cur->mac_addr, addr, ETH_ALEN);
677 list_add_tail(&cur->list, &adapter->mac_list);
678 return nx_p3_sre_macaddr_change(adapter,
679 cur->mac_addr, NETXEN_MAC_ADD);
680 }
681
682 static void netxen_p3_nic_set_multi(struct net_device *netdev)
683 {
684 struct netxen_adapter *adapter = netdev_priv(netdev);
685 struct netdev_hw_addr *ha;
686 static const u8 bcast_addr[ETH_ALEN] = {
687 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
688 };
689 u32 mode = VPORT_MISS_MODE_DROP;
690 LIST_HEAD(del_list);
691 struct list_head *head;
692 nx_mac_list_t *cur;
693
694 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
695 return;
696
697 list_splice_tail_init(&adapter->mac_list, &del_list);
698
699 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
700 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
701
702 if (netdev->flags & IFF_PROMISC) {
703 mode = VPORT_MISS_MODE_ACCEPT_ALL;
704 goto send_fw_cmd;
705 }
706
707 if ((netdev->flags & IFF_ALLMULTI) ||
708 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
709 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
710 goto send_fw_cmd;
711 }
712
713 if (!netdev_mc_empty(netdev)) {
714 netdev_for_each_mc_addr(ha, netdev)
715 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
716 }
717
718 send_fw_cmd:
719 adapter->set_promisc(adapter, mode);
720 head = &del_list;
721 while (!list_empty(head)) {
722 cur = list_entry(head->next, nx_mac_list_t, list);
723
724 nx_p3_sre_macaddr_change(adapter,
725 cur->mac_addr, NETXEN_MAC_DEL);
726 list_del(&cur->list);
727 kfree(cur);
728 }
729 }
730
731 static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
732 {
733 nx_nic_req_t req;
734 u64 word;
735
736 memset(&req, 0, sizeof(nx_nic_req_t));
737
738 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
739
740 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
741 ((u64)adapter->portnum << 16);
742 req.req_hdr = cpu_to_le64(word);
743
744 req.words[0] = cpu_to_le64(mode);
745
746 return netxen_send_cmd_descs(adapter,
747 (struct cmd_desc_type0 *)&req, 1);
748 }
749
750 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
751 {
752 nx_mac_list_t *cur;
753 struct list_head *head = &adapter->mac_list;
754
755 while (!list_empty(head)) {
756 cur = list_entry(head->next, nx_mac_list_t, list);
757 nx_p3_sre_macaddr_change(adapter,
758 cur->mac_addr, NETXEN_MAC_DEL);
759 list_del(&cur->list);
760 kfree(cur);
761 }
762 }
763
764 static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
765 {
766 /* assuming caller has already copied new addr to netdev */
767 netxen_p3_nic_set_multi(adapter->netdev);
768 return 0;
769 }
770
771 #define NETXEN_CONFIG_INTR_COALESCE 3
772
773 /*
774 * Send the interrupt coalescing parameter set by ethtool to the card.
775 */
776 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
777 {
778 nx_nic_req_t req;
779 u64 word[6];
780 int rv, i;
781
782 memset(&req, 0, sizeof(nx_nic_req_t));
783 memset(word, 0, sizeof(word));
784
785 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
786
787 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
788 req.req_hdr = cpu_to_le64(word[0]);
789
790 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
791 for (i = 0; i < 6; i++)
792 req.words[i] = cpu_to_le64(word[i]);
793
794 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
795 if (rv != 0) {
796 printk(KERN_ERR "ERROR. Could not send "
797 "interrupt coalescing parameters\n");
798 }
799
800 return rv;
801 }
802
803 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
804 {
805 nx_nic_req_t req;
806 u64 word;
807 int rv = 0;
808
809 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
810 return 0;
811
812 memset(&req, 0, sizeof(nx_nic_req_t));
813
814 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
815
816 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
817 req.req_hdr = cpu_to_le64(word);
818
819 req.words[0] = cpu_to_le64(enable);
820
821 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
822 if (rv != 0) {
823 printk(KERN_ERR "ERROR. Could not send "
824 "configure hw lro request\n");
825 }
826
827 return rv;
828 }
829
830 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
831 {
832 nx_nic_req_t req;
833 u64 word;
834 int rv = 0;
835
836 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
837 return rv;
838
839 memset(&req, 0, sizeof(nx_nic_req_t));
840
841 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
842
843 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
844 ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
846
847 req.words[0] = cpu_to_le64(enable);
848
849 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
850 if (rv != 0) {
851 printk(KERN_ERR "ERROR. Could not send "
852 "configure bridge mode request\n");
853 }
854
855 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
856
857 return rv;
858 }
859
860
861 #define RSS_HASHTYPE_IP_TCP 0x3
862
863 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
864 {
865 nx_nic_req_t req;
866 u64 word;
867 int i, rv;
868
869 static const u64 key[] = {
870 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
871 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
872 0x255b0ec26d5a56daULL
873 };
874
875
876 memset(&req, 0, sizeof(nx_nic_req_t));
877 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
878
879 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
880 req.req_hdr = cpu_to_le64(word);
881
882 /*
883 * RSS request:
884 * bits 3-0: hash_method
885 * 5-4: hash_type_ipv4
886 * 7-6: hash_type_ipv6
887 * 8: enable
888 * 9: use indirection table
889 * 47-10: reserved
890 * 63-48: indirection table mask
891 */
892 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
893 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
894 ((u64)(enable & 0x1) << 8) |
895 ((0x7ULL) << 48);
896 req.words[0] = cpu_to_le64(word);
897 for (i = 0; i < ARRAY_SIZE(key); i++)
898 req.words[i+1] = cpu_to_le64(key[i]);
899
900
901 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
902 if (rv != 0) {
903 printk(KERN_ERR "%s: could not configure RSS\n",
904 adapter->netdev->name);
905 }
906
907 return rv;
908 }
909
910 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd)
911 {
912 nx_nic_req_t req;
913 u64 word;
914 int rv;
915
916 memset(&req, 0, sizeof(nx_nic_req_t));
917 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
918
919 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
920 req.req_hdr = cpu_to_le64(word);
921
922 req.words[0] = cpu_to_le64(cmd);
923 memcpy(&req.words[1], &ip, sizeof(u32));
924
925 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
926 if (rv != 0) {
927 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
928 adapter->netdev->name,
929 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
930 }
931 return rv;
932 }
933
934 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
935 {
936 nx_nic_req_t req;
937 u64 word;
938 int rv;
939
940 memset(&req, 0, sizeof(nx_nic_req_t));
941 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
942
943 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
944 req.req_hdr = cpu_to_le64(word);
945 req.words[0] = cpu_to_le64(enable | (enable << 8));
946
947 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
948 if (rv != 0) {
949 printk(KERN_ERR "%s: could not configure link notification\n",
950 adapter->netdev->name);
951 }
952
953 return rv;
954 }
955
956 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
957 {
958 nx_nic_req_t req;
959 u64 word;
960 int rv;
961
962 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
963 return 0;
964
965 memset(&req, 0, sizeof(nx_nic_req_t));
966 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
967
968 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
969 ((u64)adapter->portnum << 16) |
970 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
971
972 req.req_hdr = cpu_to_le64(word);
973
974 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
975 if (rv != 0) {
976 printk(KERN_ERR "%s: could not cleanup lro flows\n",
977 adapter->netdev->name);
978 }
979 return rv;
980 }
981
982 /*
983 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
984 * @returns 0 on success, negative on failure
985 */
986
987 #define MTU_FUDGE_FACTOR 100
988
989 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
990 {
991 struct netxen_adapter *adapter = netdev_priv(netdev);
992 int max_mtu;
993 int rc = 0;
994
995 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
996 max_mtu = P3_MAX_MTU;
997 else
998 max_mtu = P2_MAX_MTU;
999
1000 if (mtu > max_mtu) {
1001 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
1002 netdev->name, max_mtu);
1003 return -EINVAL;
1004 }
1005
1006 if (adapter->set_mtu)
1007 rc = adapter->set_mtu(adapter, mtu);
1008
1009 if (!rc)
1010 netdev->mtu = mtu;
1011
1012 return rc;
1013 }
1014
1015 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1016 int size, __le32 * buf)
1017 {
1018 int i, v, addr;
1019 __le32 *ptr32;
1020
1021 addr = base;
1022 ptr32 = buf;
1023 for (i = 0; i < size / sizeof(u32); i++) {
1024 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1025 return -1;
1026 *ptr32 = cpu_to_le32(v);
1027 ptr32++;
1028 addr += sizeof(u32);
1029 }
1030 if ((char *)buf + size > (char *)ptr32) {
1031 __le32 local;
1032 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1033 return -1;
1034 local = cpu_to_le32(v);
1035 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1036 }
1037
1038 return 0;
1039 }
1040
1041 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1042 {
1043 __le32 *pmac = (__le32 *) mac;
1044 u32 offset;
1045
1046 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1047
1048 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1049 return -1;
1050
1051 if (*mac == ~0ULL) {
1052
1053 offset = NX_OLD_MAC_ADDR_OFFSET +
1054 (adapter->portnum * sizeof(u64));
1055
1056 if (netxen_get_flash_block(adapter,
1057 offset, sizeof(u64), pmac) == -1)
1058 return -1;
1059
1060 if (*mac == ~0ULL)
1061 return -1;
1062 }
1063 return 0;
1064 }
1065
1066 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1067 {
1068 uint32_t crbaddr, mac_hi, mac_lo;
1069 int pci_func = adapter->ahw.pci_func;
1070
1071 crbaddr = CRB_MAC_BLOCK_START +
1072 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1073
1074 mac_lo = NXRD32(adapter, crbaddr);
1075 mac_hi = NXRD32(adapter, crbaddr+4);
1076
1077 if (pci_func & 1)
1078 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1079 else
1080 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1081
1082 return 0;
1083 }
1084
1085 /*
1086 * Changes the CRB window to the specified window.
1087 */
1088 static void
1089 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1090 u32 window)
1091 {
1092 void __iomem *offset;
1093 int count = 10;
1094 u8 func = adapter->ahw.pci_func;
1095
1096 if (adapter->ahw.crb_win == window)
1097 return;
1098
1099 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1100 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1101
1102 writel(window, offset);
1103 do {
1104 if (window == readl(offset))
1105 break;
1106
1107 if (printk_ratelimit())
1108 dev_warn(&adapter->pdev->dev,
1109 "failed to set CRB window to %d\n",
1110 (window == NETXEN_WINDOW_ONE));
1111 udelay(1);
1112
1113 } while (--count > 0);
1114
1115 if (count > 0)
1116 adapter->ahw.crb_win = window;
1117 }
1118
1119 /*
1120 * Returns < 0 if off is not valid,
1121 * 1 if window access is needed. 'off' is set to offset from
1122 * CRB space in 128M pci map
1123 * 0 if no window access is needed. 'off' is set to 2M addr
1124 * In: 'off' is offset from base in 128M pci map
1125 */
1126 static int
1127 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1128 ulong off, void __iomem **addr)
1129 {
1130 crb_128M_2M_sub_block_map_t *m;
1131
1132
1133 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1134 return -EINVAL;
1135
1136 off -= NETXEN_PCI_CRBSPACE;
1137
1138 /*
1139 * Try direct map
1140 */
1141 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1142
1143 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1144 *addr = adapter->ahw.pci_base0 + m->start_2M +
1145 (off - m->start_128M);
1146 return 0;
1147 }
1148
1149 /*
1150 * Not in direct map, use crb window
1151 */
1152 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1153 (off & MASK(16));
1154 return 1;
1155 }
1156
1157 /*
1158 * In: 'off' is offset from CRB space in 128M pci map
1159 * Out: 'off' is 2M pci map addr
1160 * side effect: lock crb window
1161 */
1162 static void
1163 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1164 {
1165 u32 window;
1166 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1167
1168 off -= NETXEN_PCI_CRBSPACE;
1169
1170 window = CRB_HI(off);
1171
1172 writel(window, addr);
1173 if (readl(addr) != window) {
1174 if (printk_ratelimit())
1175 dev_warn(&adapter->pdev->dev,
1176 "failed to set CRB window to %d off 0x%lx\n",
1177 window, off);
1178 }
1179 }
1180
1181 static void __iomem *
1182 netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1183 ulong win_off, void __iomem **mem_ptr)
1184 {
1185 ulong off = win_off;
1186 void __iomem *addr;
1187 resource_size_t mem_base;
1188
1189 if (ADDR_IN_WINDOW1(win_off))
1190 off = NETXEN_CRB_NORMAL(win_off);
1191
1192 addr = pci_base_offset(adapter, off);
1193 if (addr)
1194 return addr;
1195
1196 if (adapter->ahw.pci_len0 == 0)
1197 off -= NETXEN_PCI_CRBSPACE;
1198
1199 mem_base = pci_resource_start(adapter->pdev, 0);
1200 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1201 if (*mem_ptr)
1202 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1203
1204 return addr;
1205 }
1206
1207 static int
1208 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1209 {
1210 unsigned long flags;
1211 void __iomem *addr, *mem_ptr = NULL;
1212
1213 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1214 if (!addr)
1215 return -EIO;
1216
1217 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1218 netxen_nic_io_write_128M(adapter, addr, data);
1219 } else { /* Window 0 */
1220 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1221 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1222 writel(data, addr);
1223 netxen_nic_pci_set_crbwindow_128M(adapter,
1224 NETXEN_WINDOW_ONE);
1225 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1226 }
1227
1228 if (mem_ptr)
1229 iounmap(mem_ptr);
1230
1231 return 0;
1232 }
1233
1234 static u32
1235 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1236 {
1237 unsigned long flags;
1238 void __iomem *addr, *mem_ptr = NULL;
1239 u32 data;
1240
1241 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1242 if (!addr)
1243 return -EIO;
1244
1245 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1246 data = netxen_nic_io_read_128M(adapter, addr);
1247 } else { /* Window 0 */
1248 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1249 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1250 data = readl(addr);
1251 netxen_nic_pci_set_crbwindow_128M(adapter,
1252 NETXEN_WINDOW_ONE);
1253 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1254 }
1255
1256 if (mem_ptr)
1257 iounmap(mem_ptr);
1258
1259 return data;
1260 }
1261
1262 static int
1263 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1264 {
1265 unsigned long flags;
1266 int rv;
1267 void __iomem *addr = NULL;
1268
1269 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1270
1271 if (rv == 0) {
1272 writel(data, addr);
1273 return 0;
1274 }
1275
1276 if (rv > 0) {
1277 /* indirect access */
1278 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1279 crb_win_lock(adapter);
1280 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1281 writel(data, addr);
1282 crb_win_unlock(adapter);
1283 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1284 return 0;
1285 }
1286
1287 dev_err(&adapter->pdev->dev,
1288 "%s: invalid offset: 0x%016lx\n", __func__, off);
1289 dump_stack();
1290 return -EIO;
1291 }
1292
1293 static u32
1294 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1295 {
1296 unsigned long flags;
1297 int rv;
1298 u32 data;
1299 void __iomem *addr = NULL;
1300
1301 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1302
1303 if (rv == 0)
1304 return readl(addr);
1305
1306 if (rv > 0) {
1307 /* indirect access */
1308 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1309 crb_win_lock(adapter);
1310 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1311 data = readl(addr);
1312 crb_win_unlock(adapter);
1313 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1314 return data;
1315 }
1316
1317 dev_err(&adapter->pdev->dev,
1318 "%s: invalid offset: 0x%016lx\n", __func__, off);
1319 dump_stack();
1320 return -1;
1321 }
1322
1323 /* window 1 registers only */
1324 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1325 void __iomem *addr, u32 data)
1326 {
1327 read_lock(&adapter->ahw.crb_lock);
1328 writel(data, addr);
1329 read_unlock(&adapter->ahw.crb_lock);
1330 }
1331
1332 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1333 void __iomem *addr)
1334 {
1335 u32 val;
1336
1337 read_lock(&adapter->ahw.crb_lock);
1338 val = readl(addr);
1339 read_unlock(&adapter->ahw.crb_lock);
1340
1341 return val;
1342 }
1343
1344 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1345 void __iomem *addr, u32 data)
1346 {
1347 writel(data, addr);
1348 }
1349
1350 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1351 void __iomem *addr)
1352 {
1353 return readl(addr);
1354 }
1355
1356 void __iomem *
1357 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1358 {
1359 void __iomem *addr = NULL;
1360
1361 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1362 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1363 (offset > NETXEN_CRB_PCIX_HOST))
1364 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1365 else
1366 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1367 } else {
1368 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1369 offset, &addr));
1370 }
1371
1372 return addr;
1373 }
1374
1375 static int
1376 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1377 u64 addr, u32 *start)
1378 {
1379 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1380 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1381 return 0;
1382 } else if (ADDR_IN_RANGE(addr,
1383 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1384 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1385 return 0;
1386 }
1387
1388 return -EIO;
1389 }
1390
1391 static int
1392 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1393 u64 addr, u32 *start)
1394 {
1395 u32 window;
1396
1397 window = OCM_WIN(addr);
1398
1399 writel(window, adapter->ahw.ocm_win_crb);
1400 /* read back to flush */
1401 readl(adapter->ahw.ocm_win_crb);
1402
1403 adapter->ahw.ocm_win = window;
1404 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1405 return 0;
1406 }
1407
1408 static int
1409 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1410 u64 *data, int op)
1411 {
1412 void __iomem *addr, *mem_ptr = NULL;
1413 resource_size_t mem_base;
1414 int ret;
1415 u32 start;
1416
1417 spin_lock(&adapter->ahw.mem_lock);
1418
1419 ret = adapter->pci_set_window(adapter, off, &start);
1420 if (ret != 0)
1421 goto unlock;
1422
1423 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1424 addr = adapter->ahw.pci_base0 + start;
1425 } else {
1426 addr = pci_base_offset(adapter, start);
1427 if (addr)
1428 goto noremap;
1429
1430 mem_base = pci_resource_start(adapter->pdev, 0) +
1431 (start & PAGE_MASK);
1432 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1433 if (mem_ptr == NULL) {
1434 ret = -EIO;
1435 goto unlock;
1436 }
1437
1438 addr = mem_ptr + (start & (PAGE_SIZE-1));
1439 }
1440 noremap:
1441 if (op == 0) /* read */
1442 *data = readq(addr);
1443 else /* write */
1444 writeq(*data, addr);
1445
1446 unlock:
1447 spin_unlock(&adapter->ahw.mem_lock);
1448
1449 if (mem_ptr)
1450 iounmap(mem_ptr);
1451 return ret;
1452 }
1453
1454 void
1455 netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1456 {
1457 void __iomem *addr = adapter->ahw.pci_base0 +
1458 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1459
1460 spin_lock(&adapter->ahw.mem_lock);
1461 *data = readq(addr);
1462 spin_unlock(&adapter->ahw.mem_lock);
1463 }
1464
1465 void
1466 netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1467 {
1468 void __iomem *addr = adapter->ahw.pci_base0 +
1469 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1470
1471 spin_lock(&adapter->ahw.mem_lock);
1472 writeq(data, addr);
1473 spin_unlock(&adapter->ahw.mem_lock);
1474 }
1475
1476 #define MAX_CTL_CHECK 1000
1477
1478 static int
1479 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1480 u64 off, u64 data)
1481 {
1482 int j, ret;
1483 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1484 void __iomem *mem_crb;
1485
1486 /* Only 64-bit aligned access */
1487 if (off & 7)
1488 return -EIO;
1489
1490 /* P2 has different SIU and MIU test agent base addr */
1491 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1492 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1493 mem_crb = pci_base_offset(adapter,
1494 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1495 addr_hi = SIU_TEST_AGT_ADDR_HI;
1496 data_lo = SIU_TEST_AGT_WRDATA_LO;
1497 data_hi = SIU_TEST_AGT_WRDATA_HI;
1498 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1499 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1500 goto correct;
1501 }
1502
1503 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1504 mem_crb = pci_base_offset(adapter,
1505 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1506 addr_hi = MIU_TEST_AGT_ADDR_HI;
1507 data_lo = MIU_TEST_AGT_WRDATA_LO;
1508 data_hi = MIU_TEST_AGT_WRDATA_HI;
1509 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1510 off_hi = 0;
1511 goto correct;
1512 }
1513
1514 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1515 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1516 if (adapter->ahw.pci_len0 != 0) {
1517 return netxen_nic_pci_mem_access_direct(adapter,
1518 off, &data, 1);
1519 }
1520 }
1521
1522 return -EIO;
1523
1524 correct:
1525 spin_lock(&adapter->ahw.mem_lock);
1526 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1527
1528 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1529 writel(off_hi, (mem_crb + addr_hi));
1530 writel(data & 0xffffffff, (mem_crb + data_lo));
1531 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1532 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1533 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1534 (mem_crb + TEST_AGT_CTRL));
1535
1536 for (j = 0; j < MAX_CTL_CHECK; j++) {
1537 temp = readl((mem_crb + TEST_AGT_CTRL));
1538 if ((temp & TA_CTL_BUSY) == 0)
1539 break;
1540 }
1541
1542 if (j >= MAX_CTL_CHECK) {
1543 if (printk_ratelimit())
1544 dev_err(&adapter->pdev->dev,
1545 "failed to write through agent\n");
1546 ret = -EIO;
1547 } else
1548 ret = 0;
1549
1550 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1551 spin_unlock(&adapter->ahw.mem_lock);
1552 return ret;
1553 }
1554
1555 static int
1556 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1557 u64 off, u64 *data)
1558 {
1559 int j, ret;
1560 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1561 u64 val;
1562 void __iomem *mem_crb;
1563
1564 /* Only 64-bit aligned access */
1565 if (off & 7)
1566 return -EIO;
1567
1568 /* P2 has different SIU and MIU test agent base addr */
1569 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1570 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1571 mem_crb = pci_base_offset(adapter,
1572 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1573 addr_hi = SIU_TEST_AGT_ADDR_HI;
1574 data_lo = SIU_TEST_AGT_RDDATA_LO;
1575 data_hi = SIU_TEST_AGT_RDDATA_HI;
1576 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1577 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1578 goto correct;
1579 }
1580
1581 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1582 mem_crb = pci_base_offset(adapter,
1583 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1584 addr_hi = MIU_TEST_AGT_ADDR_HI;
1585 data_lo = MIU_TEST_AGT_RDDATA_LO;
1586 data_hi = MIU_TEST_AGT_RDDATA_HI;
1587 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1588 off_hi = 0;
1589 goto correct;
1590 }
1591
1592 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1593 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1594 if (adapter->ahw.pci_len0 != 0) {
1595 return netxen_nic_pci_mem_access_direct(adapter,
1596 off, data, 0);
1597 }
1598 }
1599
1600 return -EIO;
1601
1602 correct:
1603 spin_lock(&adapter->ahw.mem_lock);
1604 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1605
1606 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1607 writel(off_hi, (mem_crb + addr_hi));
1608 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1609 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1610
1611 for (j = 0; j < MAX_CTL_CHECK; j++) {
1612 temp = readl(mem_crb + TEST_AGT_CTRL);
1613 if ((temp & TA_CTL_BUSY) == 0)
1614 break;
1615 }
1616
1617 if (j >= MAX_CTL_CHECK) {
1618 if (printk_ratelimit())
1619 dev_err(&adapter->pdev->dev,
1620 "failed to read through agent\n");
1621 ret = -EIO;
1622 } else {
1623
1624 temp = readl(mem_crb + data_hi);
1625 val = ((u64)temp << 32);
1626 val |= readl(mem_crb + data_lo);
1627 *data = val;
1628 ret = 0;
1629 }
1630
1631 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1632 spin_unlock(&adapter->ahw.mem_lock);
1633
1634 return ret;
1635 }
1636
1637 static int
1638 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1639 u64 off, u64 data)
1640 {
1641 int j, ret;
1642 u32 temp, off8;
1643 void __iomem *mem_crb;
1644
1645 /* Only 64-bit aligned access */
1646 if (off & 7)
1647 return -EIO;
1648
1649 /* P3 onward, test agent base for MIU and SIU is same */
1650 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1651 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1652 mem_crb = netxen_get_ioaddr(adapter,
1653 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1654 goto correct;
1655 }
1656
1657 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1658 mem_crb = netxen_get_ioaddr(adapter,
1659 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1660 goto correct;
1661 }
1662
1663 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1664 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1665
1666 return -EIO;
1667
1668 correct:
1669 off8 = off & 0xfffffff8;
1670
1671 spin_lock(&adapter->ahw.mem_lock);
1672
1673 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1674 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1675
1676 writel(data & 0xffffffff,
1677 mem_crb + MIU_TEST_AGT_WRDATA_LO);
1678 writel((data >> 32) & 0xffffffff,
1679 mem_crb + MIU_TEST_AGT_WRDATA_HI);
1680
1681 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1682 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1683 (mem_crb + TEST_AGT_CTRL));
1684
1685 for (j = 0; j < MAX_CTL_CHECK; j++) {
1686 temp = readl(mem_crb + TEST_AGT_CTRL);
1687 if ((temp & TA_CTL_BUSY) == 0)
1688 break;
1689 }
1690
1691 if (j >= MAX_CTL_CHECK) {
1692 if (printk_ratelimit())
1693 dev_err(&adapter->pdev->dev,
1694 "failed to write through agent\n");
1695 ret = -EIO;
1696 } else
1697 ret = 0;
1698
1699 spin_unlock(&adapter->ahw.mem_lock);
1700
1701 return ret;
1702 }
1703
1704 static int
1705 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1706 u64 off, u64 *data)
1707 {
1708 int j, ret;
1709 u32 temp, off8;
1710 u64 val;
1711 void __iomem *mem_crb;
1712
1713 /* Only 64-bit aligned access */
1714 if (off & 7)
1715 return -EIO;
1716
1717 /* P3 onward, test agent base for MIU and SIU is same */
1718 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1719 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1720 mem_crb = netxen_get_ioaddr(adapter,
1721 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1722 goto correct;
1723 }
1724
1725 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1726 mem_crb = netxen_get_ioaddr(adapter,
1727 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1728 goto correct;
1729 }
1730
1731 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1732 return netxen_nic_pci_mem_access_direct(adapter,
1733 off, data, 0);
1734 }
1735
1736 return -EIO;
1737
1738 correct:
1739 off8 = off & 0xfffffff8;
1740
1741 spin_lock(&adapter->ahw.mem_lock);
1742
1743 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1744 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1745 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1746 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1747
1748 for (j = 0; j < MAX_CTL_CHECK; j++) {
1749 temp = readl(mem_crb + TEST_AGT_CTRL);
1750 if ((temp & TA_CTL_BUSY) == 0)
1751 break;
1752 }
1753
1754 if (j >= MAX_CTL_CHECK) {
1755 if (printk_ratelimit())
1756 dev_err(&adapter->pdev->dev,
1757 "failed to read through agent\n");
1758 ret = -EIO;
1759 } else {
1760 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1761 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1762 *data = val;
1763 ret = 0;
1764 }
1765
1766 spin_unlock(&adapter->ahw.mem_lock);
1767
1768 return ret;
1769 }
1770
1771 void
1772 netxen_setup_hwops(struct netxen_adapter *adapter)
1773 {
1774 adapter->init_port = netxen_niu_xg_init_port;
1775 adapter->stop_port = netxen_niu_disable_xg_port;
1776
1777 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1778 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1779 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1780 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1781 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1782 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1783 adapter->io_read = netxen_nic_io_read_128M,
1784 adapter->io_write = netxen_nic_io_write_128M,
1785
1786 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1787 adapter->set_multi = netxen_p2_nic_set_multi;
1788 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1789 adapter->set_promisc = netxen_p2_nic_set_promisc;
1790
1791 } else {
1792 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1793 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1794 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1795 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1796 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1797 adapter->io_read = netxen_nic_io_read_2M,
1798 adapter->io_write = netxen_nic_io_write_2M,
1799
1800 adapter->set_mtu = nx_fw_cmd_set_mtu;
1801 adapter->set_promisc = netxen_p3_nic_set_promisc;
1802 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1803 adapter->set_multi = netxen_p3_nic_set_multi;
1804
1805 adapter->phy_read = nx_fw_cmd_query_phy;
1806 adapter->phy_write = nx_fw_cmd_set_phy;
1807 }
1808 }
1809
1810 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1811 {
1812 int offset, board_type, magic;
1813 struct pci_dev *pdev = adapter->pdev;
1814
1815 offset = NX_FW_MAGIC_OFFSET;
1816 if (netxen_rom_fast_read(adapter, offset, &magic))
1817 return -EIO;
1818
1819 if (magic != NETXEN_BDINFO_MAGIC) {
1820 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1821 magic);
1822 return -EIO;
1823 }
1824
1825 offset = NX_BRDTYPE_OFFSET;
1826 if (netxen_rom_fast_read(adapter, offset, &board_type))
1827 return -EIO;
1828
1829 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1830 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1831 if ((gpio & 0x8000) == 0)
1832 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1833 }
1834
1835 adapter->ahw.board_type = board_type;
1836
1837 switch (board_type) {
1838 case NETXEN_BRDTYPE_P2_SB35_4G:
1839 adapter->ahw.port_type = NETXEN_NIC_GBE;
1840 break;
1841 case NETXEN_BRDTYPE_P2_SB31_10G:
1842 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1843 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1844 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1845 case NETXEN_BRDTYPE_P3_HMEZ:
1846 case NETXEN_BRDTYPE_P3_XG_LOM:
1847 case NETXEN_BRDTYPE_P3_10G_CX4:
1848 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1849 case NETXEN_BRDTYPE_P3_IMEZ:
1850 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1851 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1852 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1853 case NETXEN_BRDTYPE_P3_10G_XFP:
1854 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1855 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1856 break;
1857 case NETXEN_BRDTYPE_P1_BD:
1858 case NETXEN_BRDTYPE_P1_SB:
1859 case NETXEN_BRDTYPE_P1_SMAX:
1860 case NETXEN_BRDTYPE_P1_SOCK:
1861 case NETXEN_BRDTYPE_P3_REF_QG:
1862 case NETXEN_BRDTYPE_P3_4_GB:
1863 case NETXEN_BRDTYPE_P3_4_GB_MM:
1864 adapter->ahw.port_type = NETXEN_NIC_GBE;
1865 break;
1866 case NETXEN_BRDTYPE_P3_10G_TP:
1867 adapter->ahw.port_type = (adapter->portnum < 2) ?
1868 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1869 break;
1870 default:
1871 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1872 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1873 break;
1874 }
1875
1876 return 0;
1877 }
1878
1879 /* NIU access sections */
1880 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1881 {
1882 new_mtu += MTU_FUDGE_FACTOR;
1883 if (adapter->physical_port == 0)
1884 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1885 else
1886 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1887 return 0;
1888 }
1889
1890 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1891 {
1892 __u32 status;
1893 __u32 autoneg;
1894 __u32 port_mode;
1895
1896 if (!netif_carrier_ok(adapter->netdev)) {
1897 adapter->link_speed = 0;
1898 adapter->link_duplex = -1;
1899 adapter->link_autoneg = AUTONEG_ENABLE;
1900 return;
1901 }
1902
1903 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1904 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1905 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1906 adapter->link_speed = SPEED_1000;
1907 adapter->link_duplex = DUPLEX_FULL;
1908 adapter->link_autoneg = AUTONEG_DISABLE;
1909 return;
1910 }
1911
1912 if (adapter->phy_read &&
1913 adapter->phy_read(adapter,
1914 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1915 &status) == 0) {
1916 if (netxen_get_phy_link(status)) {
1917 switch (netxen_get_phy_speed(status)) {
1918 case 0:
1919 adapter->link_speed = SPEED_10;
1920 break;
1921 case 1:
1922 adapter->link_speed = SPEED_100;
1923 break;
1924 case 2:
1925 adapter->link_speed = SPEED_1000;
1926 break;
1927 default:
1928 adapter->link_speed = 0;
1929 break;
1930 }
1931 switch (netxen_get_phy_duplex(status)) {
1932 case 0:
1933 adapter->link_duplex = DUPLEX_HALF;
1934 break;
1935 case 1:
1936 adapter->link_duplex = DUPLEX_FULL;
1937 break;
1938 default:
1939 adapter->link_duplex = -1;
1940 break;
1941 }
1942 if (adapter->phy_read &&
1943 adapter->phy_read(adapter,
1944 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1945 &autoneg) != 0)
1946 adapter->link_autoneg = autoneg;
1947 } else
1948 goto link_down;
1949 } else {
1950 link_down:
1951 adapter->link_speed = 0;
1952 adapter->link_duplex = -1;
1953 }
1954 }
1955 }
1956
1957 int
1958 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1959 {
1960 u32 wol_cfg;
1961
1962 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1963 return 0;
1964
1965 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1966 if (wol_cfg & (1UL << adapter->portnum)) {
1967 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1968 if (wol_cfg & (1 << adapter->portnum))
1969 return 1;
1970 }
1971
1972 return 0;
1973 }
1974
1975 static u32 netxen_md_cntrl(struct netxen_adapter *adapter,
1976 struct netxen_minidump_template_hdr *template_hdr,
1977 struct netxen_minidump_entry_crb *crtEntry)
1978 {
1979 int loop_cnt, i, rv = 0, timeout_flag;
1980 u32 op_count, stride;
1981 u32 opcode, read_value, addr;
1982 unsigned long timeout, timeout_jiffies;
1983 addr = crtEntry->addr;
1984 op_count = crtEntry->op_count;
1985 stride = crtEntry->addr_stride;
1986
1987 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
1988 for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) {
1989 opcode = (crtEntry->opcode & (0x1 << i));
1990 if (opcode) {
1991 switch (opcode) {
1992 case NX_DUMP_WCRB:
1993 NX_WR_DUMP_REG(addr,
1994 adapter->ahw.pci_base0,
1995 crtEntry->value_1);
1996 break;
1997 case NX_DUMP_RWCRB:
1998 NX_RD_DUMP_REG(addr,
1999 adapter->ahw.pci_base0,
2000 &read_value);
2001 NX_WR_DUMP_REG(addr,
2002 adapter->ahw.pci_base0,
2003 read_value);
2004 break;
2005 case NX_DUMP_ANDCRB:
2006 NX_RD_DUMP_REG(addr,
2007 adapter->ahw.pci_base0,
2008 &read_value);
2009 read_value &= crtEntry->value_2;
2010 NX_WR_DUMP_REG(addr,
2011 adapter->ahw.pci_base0,
2012 read_value);
2013 break;
2014 case NX_DUMP_ORCRB:
2015 NX_RD_DUMP_REG(addr,
2016 adapter->ahw.pci_base0,
2017 &read_value);
2018 read_value |= crtEntry->value_3;
2019 NX_WR_DUMP_REG(addr,
2020 adapter->ahw.pci_base0,
2021 read_value);
2022 break;
2023 case NX_DUMP_POLLCRB:
2024 timeout = crtEntry->poll_timeout;
2025 NX_RD_DUMP_REG(addr,
2026 adapter->ahw.pci_base0,
2027 &read_value);
2028 timeout_jiffies =
2029 msecs_to_jiffies(timeout) + jiffies;
2030 for (timeout_flag = 0;
2031 !timeout_flag
2032 && ((read_value & crtEntry->value_2)
2033 != crtEntry->value_1);) {
2034 if (time_after(jiffies,
2035 timeout_jiffies))
2036 timeout_flag = 1;
2037 NX_RD_DUMP_REG(addr,
2038 adapter->ahw.pci_base0,
2039 &read_value);
2040 }
2041
2042 if (timeout_flag) {
2043 dev_err(&adapter->pdev->dev, "%s : "
2044 "Timeout in poll_crb control operation.\n"
2045 , __func__);
2046 return -1;
2047 }
2048 break;
2049 case NX_DUMP_RD_SAVE:
2050 /* Decide which address to use */
2051 if (crtEntry->state_index_a)
2052 addr =
2053 template_hdr->saved_state_array
2054 [crtEntry->state_index_a];
2055 NX_RD_DUMP_REG(addr,
2056 adapter->ahw.pci_base0,
2057 &read_value);
2058 template_hdr->saved_state_array
2059 [crtEntry->state_index_v]
2060 = read_value;
2061 break;
2062 case NX_DUMP_WRT_SAVED:
2063 /* Decide which value to use */
2064 if (crtEntry->state_index_v)
2065 read_value =
2066 template_hdr->saved_state_array
2067 [crtEntry->state_index_v];
2068 else
2069 read_value = crtEntry->value_1;
2070
2071 /* Decide which address to use */
2072 if (crtEntry->state_index_a)
2073 addr =
2074 template_hdr->saved_state_array
2075 [crtEntry->state_index_a];
2076
2077 NX_WR_DUMP_REG(addr,
2078 adapter->ahw.pci_base0,
2079 read_value);
2080 break;
2081 case NX_DUMP_MOD_SAVE_ST:
2082 read_value =
2083 template_hdr->saved_state_array
2084 [crtEntry->state_index_v];
2085 read_value <<= crtEntry->shl;
2086 read_value >>= crtEntry->shr;
2087 if (crtEntry->value_2)
2088 read_value &=
2089 crtEntry->value_2;
2090 read_value |= crtEntry->value_3;
2091 read_value += crtEntry->value_1;
2092 /* Write value back to state area.*/
2093 template_hdr->saved_state_array
2094 [crtEntry->state_index_v]
2095 = read_value;
2096 break;
2097 default:
2098 rv = 1;
2099 break;
2100 }
2101 }
2102 }
2103 addr = addr + stride;
2104 }
2105 return rv;
2106 }
2107
2108 /* Read memory or MN */
2109 static u32
2110 netxen_md_rdmem(struct netxen_adapter *adapter,
2111 struct netxen_minidump_entry_rdmem
2112 *memEntry, u64 *data_buff)
2113 {
2114 u64 addr, value = 0;
2115 int i = 0, loop_cnt;
2116
2117 addr = (u64)memEntry->read_addr;
2118 loop_cnt = memEntry->read_data_size; /* This is size in bytes */
2119 loop_cnt /= sizeof(value);
2120
2121 for (i = 0; i < loop_cnt; i++) {
2122 if (netxen_nic_pci_mem_read_2M(adapter, addr, &value))
2123 goto out;
2124 *data_buff++ = value;
2125 addr += sizeof(value);
2126 }
2127 out:
2128 return i * sizeof(value);
2129 }
2130
2131 /* Read CRB operation */
2132 static u32 netxen_md_rd_crb(struct netxen_adapter *adapter,
2133 struct netxen_minidump_entry_crb
2134 *crbEntry, u32 *data_buff)
2135 {
2136 int loop_cnt;
2137 u32 op_count, addr, stride, value;
2138
2139 addr = crbEntry->addr;
2140 op_count = crbEntry->op_count;
2141 stride = crbEntry->addr_stride;
2142
2143 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
2144 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value);
2145 *data_buff++ = addr;
2146 *data_buff++ = value;
2147 addr = addr + stride;
2148 }
2149 return loop_cnt * (2 * sizeof(u32));
2150 }
2151
2152 /* Read ROM */
2153 static u32
2154 netxen_md_rdrom(struct netxen_adapter *adapter,
2155 struct netxen_minidump_entry_rdrom
2156 *romEntry, __le32 *data_buff)
2157 {
2158 int i, count = 0;
2159 u32 size, lck_val;
2160 u32 val;
2161 u32 fl_addr, waddr, raddr;
2162 fl_addr = romEntry->read_addr;
2163 size = romEntry->read_data_size/4;
2164 lock_try:
2165 lck_val = readl((void __iomem *)(adapter->ahw.pci_base0 +
2166 NX_FLASH_SEM2_LK));
2167 if (!lck_val && count < MAX_CTL_CHECK) {
2168 msleep(20);
2169 count++;
2170 goto lock_try;
2171 }
2172 writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 +
2173 NX_FLASH_LOCK_ID));
2174 for (i = 0; i < size; i++) {
2175 waddr = fl_addr & 0xFFFF0000;
2176 NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr);
2177 raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF);
2178 NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val);
2179 *data_buff++ = cpu_to_le32(val);
2180 fl_addr += sizeof(val);
2181 }
2182 readl((void __iomem *)(adapter->ahw.pci_base0 + NX_FLASH_SEM2_ULK));
2183 return romEntry->read_data_size;
2184 }
2185
2186 /* Handle L2 Cache */
2187 static u32
2188 netxen_md_L2Cache(struct netxen_adapter *adapter,
2189 struct netxen_minidump_entry_cache
2190 *cacheEntry, u32 *data_buff)
2191 {
2192 int loop_cnt, i, k, timeout_flag = 0;
2193 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2194 u32 tag_value, read_cnt;
2195 u8 cntl_value_w, cntl_value_r;
2196 unsigned long timeout, timeout_jiffies;
2197
2198 loop_cnt = cacheEntry->op_count;
2199 read_addr = cacheEntry->read_addr;
2200 cntrl_addr = cacheEntry->control_addr;
2201 cntl_value_w = (u32) cacheEntry->write_value;
2202 tag_reg_addr = cacheEntry->tag_reg_addr;
2203 tag_value = cacheEntry->init_tag_value;
2204 read_cnt = cacheEntry->read_addr_cnt;
2205
2206 for (i = 0; i < loop_cnt; i++) {
2207 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2208 if (cntl_value_w)
2209 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2210 (u32)cntl_value_w);
2211 if (cacheEntry->poll_mask) {
2212 timeout = cacheEntry->poll_wait;
2213 NX_RD_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2214 &cntl_value_r);
2215 timeout_jiffies = msecs_to_jiffies(timeout) + jiffies;
2216 for (timeout_flag = 0; !timeout_flag &&
2217 ((cntl_value_r & cacheEntry->poll_mask) != 0);) {
2218 if (time_after(jiffies, timeout_jiffies))
2219 timeout_flag = 1;
2220 NX_RD_DUMP_REG(cntrl_addr,
2221 adapter->ahw.pci_base0,
2222 &cntl_value_r);
2223 }
2224 if (timeout_flag) {
2225 dev_err(&adapter->pdev->dev,
2226 "Timeout in processing L2 Tag poll.\n");
2227 return -1;
2228 }
2229 }
2230 addr = read_addr;
2231 for (k = 0; k < read_cnt; k++) {
2232 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0,
2233 &read_value);
2234 *data_buff++ = read_value;
2235 addr += cacheEntry->read_addr_stride;
2236 }
2237 tag_value += cacheEntry->tag_value_stride;
2238 }
2239 return read_cnt * loop_cnt * sizeof(read_value);
2240 }
2241
2242
2243 /* Handle L1 Cache */
2244 static u32 netxen_md_L1Cache(struct netxen_adapter *adapter,
2245 struct netxen_minidump_entry_cache
2246 *cacheEntry, u32 *data_buff)
2247 {
2248 int i, k, loop_cnt;
2249 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2250 u32 tag_value, read_cnt;
2251 u8 cntl_value_w;
2252
2253 loop_cnt = cacheEntry->op_count;
2254 read_addr = cacheEntry->read_addr;
2255 cntrl_addr = cacheEntry->control_addr;
2256 cntl_value_w = (u32) cacheEntry->write_value;
2257 tag_reg_addr = cacheEntry->tag_reg_addr;
2258 tag_value = cacheEntry->init_tag_value;
2259 read_cnt = cacheEntry->read_addr_cnt;
2260
2261 for (i = 0; i < loop_cnt; i++) {
2262 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2263 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2264 (u32) cntl_value_w);
2265 addr = read_addr;
2266 for (k = 0; k < read_cnt; k++) {
2267 NX_RD_DUMP_REG(addr,
2268 adapter->ahw.pci_base0,
2269 &read_value);
2270 *data_buff++ = read_value;
2271 addr += cacheEntry->read_addr_stride;
2272 }
2273 tag_value += cacheEntry->tag_value_stride;
2274 }
2275 return read_cnt * loop_cnt * sizeof(read_value);
2276 }
2277
2278 /* Reading OCM memory */
2279 static u32
2280 netxen_md_rdocm(struct netxen_adapter *adapter,
2281 struct netxen_minidump_entry_rdocm
2282 *ocmEntry, u32 *data_buff)
2283 {
2284 int i, loop_cnt;
2285 u32 value;
2286 void __iomem *addr;
2287 addr = (ocmEntry->read_addr + adapter->ahw.pci_base0);
2288 loop_cnt = ocmEntry->op_count;
2289
2290 for (i = 0; i < loop_cnt; i++) {
2291 value = readl(addr);
2292 *data_buff++ = value;
2293 addr += ocmEntry->read_addr_stride;
2294 }
2295 return i * sizeof(u32);
2296 }
2297
2298 /* Read MUX data */
2299 static u32
2300 netxen_md_rdmux(struct netxen_adapter *adapter, struct netxen_minidump_entry_mux
2301 *muxEntry, u32 *data_buff)
2302 {
2303 int loop_cnt = 0;
2304 u32 read_addr, read_value, select_addr, sel_value;
2305
2306 read_addr = muxEntry->read_addr;
2307 sel_value = muxEntry->select_value;
2308 select_addr = muxEntry->select_addr;
2309
2310 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
2311 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, sel_value);
2312 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, &read_value);
2313 *data_buff++ = sel_value;
2314 *data_buff++ = read_value;
2315 sel_value += muxEntry->select_value_stride;
2316 }
2317 return loop_cnt * (2 * sizeof(u32));
2318 }
2319
2320 /* Handling Queue State Reads */
2321 static u32
2322 netxen_md_rdqueue(struct netxen_adapter *adapter,
2323 struct netxen_minidump_entry_queue
2324 *queueEntry, u32 *data_buff)
2325 {
2326 int loop_cnt, k;
2327 u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt;
2328
2329 read_cnt = queueEntry->read_addr_cnt;
2330 read_stride = queueEntry->read_addr_stride;
2331 select_addr = queueEntry->select_addr;
2332
2333 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
2334 loop_cnt++) {
2335 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id);
2336 read_addr = queueEntry->read_addr;
2337 for (k = 0; k < read_cnt; k--) {
2338 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0,
2339 &read_value);
2340 *data_buff++ = read_value;
2341 read_addr += read_stride;
2342 }
2343 queue_id += queueEntry->queue_id_stride;
2344 }
2345 return loop_cnt * (read_cnt * sizeof(read_value));
2346 }
2347
2348
2349 /*
2350 * We catch an error where driver does not read
2351 * as much data as we expect from the entry.
2352 */
2353
2354 static int netxen_md_entry_err_chk(struct netxen_adapter *adapter,
2355 struct netxen_minidump_entry *entry, int esize)
2356 {
2357 if (esize < 0) {
2358 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2359 return esize;
2360 }
2361 if (esize != entry->hdr.entry_capture_size) {
2362 entry->hdr.entry_capture_size = esize;
2363 entry->hdr.driver_flags |= NX_DUMP_SIZE_ERR;
2364 dev_info(&adapter->pdev->dev,
2365 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
2366 entry->hdr.entry_type, entry->hdr.entry_capture_mask,
2367 esize, entry->hdr.entry_capture_size);
2368 dev_info(&adapter->pdev->dev, "Aborting further dump capture\n");
2369 }
2370 return 0;
2371 }
2372
2373 static int netxen_parse_md_template(struct netxen_adapter *adapter)
2374 {
2375 int num_of_entries, buff_level, e_cnt, esize;
2376 int end_cnt = 0, rv = 0, sane_start = 0, sane_end = 0;
2377 char *dbuff;
2378 void *template_buff = adapter->mdump.md_template;
2379 char *dump_buff = adapter->mdump.md_capture_buff;
2380 int capture_mask = adapter->mdump.md_capture_mask;
2381 struct netxen_minidump_template_hdr *template_hdr;
2382 struct netxen_minidump_entry *entry;
2383
2384 if ((capture_mask & 0x3) != 0x3) {
2385 dev_err(&adapter->pdev->dev, "Capture mask %02x below minimum needed "
2386 "for valid firmware dump\n", capture_mask);
2387 return -EINVAL;
2388 }
2389 template_hdr = (struct netxen_minidump_template_hdr *) template_buff;
2390 num_of_entries = template_hdr->num_of_entries;
2391 entry = (struct netxen_minidump_entry *) ((char *) template_buff +
2392 template_hdr->first_entry_offset);
2393 memcpy(dump_buff, template_buff, adapter->mdump.md_template_size);
2394 dump_buff = dump_buff + adapter->mdump.md_template_size;
2395
2396 if (template_hdr->entry_type == TLHDR)
2397 sane_start = 1;
2398
2399 for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) {
2400 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
2401 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2402 entry = (struct netxen_minidump_entry *)
2403 ((char *) entry + entry->hdr.entry_size);
2404 continue;
2405 }
2406 switch (entry->hdr.entry_type) {
2407 case RDNOP:
2408 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2409 break;
2410 case RDEND:
2411 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2412 if (!sane_end)
2413 end_cnt = e_cnt;
2414 sane_end += 1;
2415 break;
2416 case CNTRL:
2417 rv = netxen_md_cntrl(adapter,
2418 template_hdr, (void *)entry);
2419 if (rv)
2420 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2421 break;
2422 case RDCRB:
2423 dbuff = dump_buff + buff_level;
2424 esize = netxen_md_rd_crb(adapter,
2425 (void *) entry, (void *) dbuff);
2426 rv = netxen_md_entry_err_chk
2427 (adapter, entry, esize);
2428 if (rv < 0)
2429 break;
2430 buff_level += esize;
2431 break;
2432 case RDMN:
2433 case RDMEM:
2434 dbuff = dump_buff + buff_level;
2435 esize = netxen_md_rdmem(adapter,
2436 (void *) entry, (void *) dbuff);
2437 rv = netxen_md_entry_err_chk
2438 (adapter, entry, esize);
2439 if (rv < 0)
2440 break;
2441 buff_level += esize;
2442 break;
2443 case BOARD:
2444 case RDROM:
2445 dbuff = dump_buff + buff_level;
2446 esize = netxen_md_rdrom(adapter,
2447 (void *) entry, (void *) dbuff);
2448 rv = netxen_md_entry_err_chk
2449 (adapter, entry, esize);
2450 if (rv < 0)
2451 break;
2452 buff_level += esize;
2453 break;
2454 case L2ITG:
2455 case L2DTG:
2456 case L2DAT:
2457 case L2INS:
2458 dbuff = dump_buff + buff_level;
2459 esize = netxen_md_L2Cache(adapter,
2460 (void *) entry, (void *) dbuff);
2461 rv = netxen_md_entry_err_chk
2462 (adapter, entry, esize);
2463 if (rv < 0)
2464 break;
2465 buff_level += esize;
2466 break;
2467 case L1DAT:
2468 case L1INS:
2469 dbuff = dump_buff + buff_level;
2470 esize = netxen_md_L1Cache(adapter,
2471 (void *) entry, (void *) dbuff);
2472 rv = netxen_md_entry_err_chk
2473 (adapter, entry, esize);
2474 if (rv < 0)
2475 break;
2476 buff_level += esize;
2477 break;
2478 case RDOCM:
2479 dbuff = dump_buff + buff_level;
2480 esize = netxen_md_rdocm(adapter,
2481 (void *) entry, (void *) dbuff);
2482 rv = netxen_md_entry_err_chk
2483 (adapter, entry, esize);
2484 if (rv < 0)
2485 break;
2486 buff_level += esize;
2487 break;
2488 case RDMUX:
2489 dbuff = dump_buff + buff_level;
2490 esize = netxen_md_rdmux(adapter,
2491 (void *) entry, (void *) dbuff);
2492 rv = netxen_md_entry_err_chk
2493 (adapter, entry, esize);
2494 if (rv < 0)
2495 break;
2496 buff_level += esize;
2497 break;
2498 case QUEUE:
2499 dbuff = dump_buff + buff_level;
2500 esize = netxen_md_rdqueue(adapter,
2501 (void *) entry, (void *) dbuff);
2502 rv = netxen_md_entry_err_chk
2503 (adapter, entry, esize);
2504 if (rv < 0)
2505 break;
2506 buff_level += esize;
2507 break;
2508 default:
2509 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2510 break;
2511 }
2512 /* Next entry in the template */
2513 entry = (struct netxen_minidump_entry *)
2514 ((char *) entry + entry->hdr.entry_size);
2515 }
2516 if (!sane_start || sane_end > 1) {
2517 dev_err(&adapter->pdev->dev,
2518 "Firmware minidump template configuration error.\n");
2519 }
2520 return 0;
2521 }
2522
2523 static int
2524 netxen_collect_minidump(struct netxen_adapter *adapter)
2525 {
2526 int ret = 0;
2527 struct netxen_minidump_template_hdr *hdr;
2528 struct timespec val;
2529 hdr = (struct netxen_minidump_template_hdr *)
2530 adapter->mdump.md_template;
2531 hdr->driver_capture_mask = adapter->mdump.md_capture_mask;
2532 jiffies_to_timespec(jiffies, &val);
2533 hdr->driver_timestamp = (u32) val.tv_sec;
2534 hdr->driver_info_word2 = adapter->fw_version;
2535 hdr->driver_info_word3 = NXRD32(adapter, CRB_DRIVER_VERSION);
2536 ret = netxen_parse_md_template(adapter);
2537 if (ret)
2538 return ret;
2539
2540 return ret;
2541 }
2542
2543
2544 void
2545 netxen_dump_fw(struct netxen_adapter *adapter)
2546 {
2547 struct netxen_minidump_template_hdr *hdr;
2548 int i, k, data_size = 0;
2549 u32 capture_mask;
2550 hdr = (struct netxen_minidump_template_hdr *)
2551 adapter->mdump.md_template;
2552 capture_mask = adapter->mdump.md_capture_mask;
2553
2554 for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) {
2555 if (i & capture_mask)
2556 data_size += hdr->capture_size_array[k];
2557 }
2558 if (!data_size) {
2559 dev_err(&adapter->pdev->dev,
2560 "Invalid cap sizes for capture_mask=0x%x\n",
2561 adapter->mdump.md_capture_mask);
2562 return;
2563 }
2564 adapter->mdump.md_capture_size = data_size;
2565 adapter->mdump.md_dump_size = adapter->mdump.md_template_size +
2566 adapter->mdump.md_capture_size;
2567 if (!adapter->mdump.md_capture_buff) {
2568 adapter->mdump.md_capture_buff =
2569 vzalloc(adapter->mdump.md_dump_size);
2570 if (!adapter->mdump.md_capture_buff)
2571 return;
2572
2573 if (netxen_collect_minidump(adapter)) {
2574 adapter->mdump.has_valid_dump = 0;
2575 adapter->mdump.md_dump_size = 0;
2576 vfree(adapter->mdump.md_capture_buff);
2577 adapter->mdump.md_capture_buff = NULL;
2578 dev_err(&adapter->pdev->dev,
2579 "Error in collecting firmware minidump.\n");
2580 } else {
2581 adapter->mdump.md_timestamp = jiffies;
2582 adapter->mdump.has_valid_dump = 1;
2583 adapter->fw_mdump_rdy = 1;
2584 dev_info(&adapter->pdev->dev, "%s Successfully "
2585 "collected fw dump.\n", adapter->netdev->name);
2586 }
2587
2588 } else {
2589 dev_info(&adapter->pdev->dev,
2590 "Cannot overwrite previously collected "
2591 "firmware minidump.\n");
2592 adapter->fw_mdump_rdy = 1;
2593 return;
2594 }
2595 }
Linux with added FPC-III support