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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / ethernet / renesas / sh_eth.c
blob36119b3303d7cf64705cd4c84318a6664d02051c
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/mdio-bitbang.h>
34 #include <linux/netdevice.h>
35 #include <linux/phy.h>
36 #include <linux/cache.h>
37 #include <linux/io.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/slab.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <linux/clk.h>
43 #include <linux/sh_eth.h>
44
45 #include "sh_eth.h"
46
47 #define SH_ETH_DEF_MSG_ENABLE \
48 (NETIF_MSG_LINK | \
49 NETIF_MSG_TIMER | \
50 NETIF_MSG_RX_ERR| \
51 NETIF_MSG_TX_ERR)
52
53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
54 [EDSR] = 0x0000,
55 [EDMR] = 0x0400,
56 [EDTRR] = 0x0408,
57 [EDRRR] = 0x0410,
58 [EESR] = 0x0428,
59 [EESIPR] = 0x0430,
60 [TDLAR] = 0x0010,
61 [TDFAR] = 0x0014,
62 [TDFXR] = 0x0018,
63 [TDFFR] = 0x001c,
64 [RDLAR] = 0x0030,
65 [RDFAR] = 0x0034,
66 [RDFXR] = 0x0038,
67 [RDFFR] = 0x003c,
68 [TRSCER] = 0x0438,
69 [RMFCR] = 0x0440,
70 [TFTR] = 0x0448,
71 [FDR] = 0x0450,
72 [RMCR] = 0x0458,
73 [RPADIR] = 0x0460,
74 [FCFTR] = 0x0468,
75 [CSMR] = 0x04E4,
76
77 [ECMR] = 0x0500,
78 [ECSR] = 0x0510,
79 [ECSIPR] = 0x0518,
80 [PIR] = 0x0520,
81 [PSR] = 0x0528,
82 [PIPR] = 0x052c,
83 [RFLR] = 0x0508,
84 [APR] = 0x0554,
85 [MPR] = 0x0558,
86 [PFTCR] = 0x055c,
87 [PFRCR] = 0x0560,
88 [TPAUSER] = 0x0564,
89 [GECMR] = 0x05b0,
90 [BCULR] = 0x05b4,
91 [MAHR] = 0x05c0,
92 [MALR] = 0x05c8,
93 [TROCR] = 0x0700,
94 [CDCR] = 0x0708,
95 [LCCR] = 0x0710,
96 [CEFCR] = 0x0740,
97 [FRECR] = 0x0748,
98 [TSFRCR] = 0x0750,
99 [TLFRCR] = 0x0758,
100 [RFCR] = 0x0760,
101 [CERCR] = 0x0768,
102 [CEECR] = 0x0770,
103 [MAFCR] = 0x0778,
104 [RMII_MII] = 0x0790,
105
106 [ARSTR] = 0x0000,
107 [TSU_CTRST] = 0x0004,
108 [TSU_FWEN0] = 0x0010,
109 [TSU_FWEN1] = 0x0014,
110 [TSU_FCM] = 0x0018,
111 [TSU_BSYSL0] = 0x0020,
112 [TSU_BSYSL1] = 0x0024,
113 [TSU_PRISL0] = 0x0028,
114 [TSU_PRISL1] = 0x002c,
115 [TSU_FWSL0] = 0x0030,
116 [TSU_FWSL1] = 0x0034,
117 [TSU_FWSLC] = 0x0038,
118 [TSU_QTAG0] = 0x0040,
119 [TSU_QTAG1] = 0x0044,
120 [TSU_FWSR] = 0x0050,
121 [TSU_FWINMK] = 0x0054,
122 [TSU_ADQT0] = 0x0048,
123 [TSU_ADQT1] = 0x004c,
124 [TSU_VTAG0] = 0x0058,
125 [TSU_VTAG1] = 0x005c,
126 [TSU_ADSBSY] = 0x0060,
127 [TSU_TEN] = 0x0064,
128 [TSU_POST1] = 0x0070,
129 [TSU_POST2] = 0x0074,
130 [TSU_POST3] = 0x0078,
131 [TSU_POST4] = 0x007c,
132 [TSU_ADRH0] = 0x0100,
133 [TSU_ADRL0] = 0x0104,
134 [TSU_ADRH31] = 0x01f8,
135 [TSU_ADRL31] = 0x01fc,
136
137 [TXNLCR0] = 0x0080,
138 [TXALCR0] = 0x0084,
139 [RXNLCR0] = 0x0088,
140 [RXALCR0] = 0x008c,
141 [FWNLCR0] = 0x0090,
142 [FWALCR0] = 0x0094,
143 [TXNLCR1] = 0x00a0,
144 [TXALCR1] = 0x00a0,
145 [RXNLCR1] = 0x00a8,
146 [RXALCR1] = 0x00ac,
147 [FWNLCR1] = 0x00b0,
148 [FWALCR1] = 0x00b4,
149 };
150
151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
152 [ECMR] = 0x0300,
153 [RFLR] = 0x0308,
154 [ECSR] = 0x0310,
155 [ECSIPR] = 0x0318,
156 [PIR] = 0x0320,
157 [PSR] = 0x0328,
158 [RDMLR] = 0x0340,
159 [IPGR] = 0x0350,
160 [APR] = 0x0354,
161 [MPR] = 0x0358,
162 [RFCF] = 0x0360,
163 [TPAUSER] = 0x0364,
164 [TPAUSECR] = 0x0368,
165 [MAHR] = 0x03c0,
166 [MALR] = 0x03c8,
167 [TROCR] = 0x03d0,
168 [CDCR] = 0x03d4,
169 [LCCR] = 0x03d8,
170 [CNDCR] = 0x03dc,
171 [CEFCR] = 0x03e4,
172 [FRECR] = 0x03e8,
173 [TSFRCR] = 0x03ec,
174 [TLFRCR] = 0x03f0,
175 [RFCR] = 0x03f4,
176 [MAFCR] = 0x03f8,
177
178 [EDMR] = 0x0200,
179 [EDTRR] = 0x0208,
180 [EDRRR] = 0x0210,
181 [TDLAR] = 0x0218,
182 [RDLAR] = 0x0220,
183 [EESR] = 0x0228,
184 [EESIPR] = 0x0230,
185 [TRSCER] = 0x0238,
186 [RMFCR] = 0x0240,
187 [TFTR] = 0x0248,
188 [FDR] = 0x0250,
189 [RMCR] = 0x0258,
190 [TFUCR] = 0x0264,
191 [RFOCR] = 0x0268,
192 [RMIIMODE] = 0x026c,
193 [FCFTR] = 0x0270,
194 [TRIMD] = 0x027c,
195 };
196
197 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
198 [ECMR] = 0x0100,
199 [RFLR] = 0x0108,
200 [ECSR] = 0x0110,
201 [ECSIPR] = 0x0118,
202 [PIR] = 0x0120,
203 [PSR] = 0x0128,
204 [RDMLR] = 0x0140,
205 [IPGR] = 0x0150,
206 [APR] = 0x0154,
207 [MPR] = 0x0158,
208 [TPAUSER] = 0x0164,
209 [RFCF] = 0x0160,
210 [TPAUSECR] = 0x0168,
211 [BCFRR] = 0x016c,
212 [MAHR] = 0x01c0,
213 [MALR] = 0x01c8,
214 [TROCR] = 0x01d0,
215 [CDCR] = 0x01d4,
216 [LCCR] = 0x01d8,
217 [CNDCR] = 0x01dc,
218 [CEFCR] = 0x01e4,
219 [FRECR] = 0x01e8,
220 [TSFRCR] = 0x01ec,
221 [TLFRCR] = 0x01f0,
222 [RFCR] = 0x01f4,
223 [MAFCR] = 0x01f8,
224 [RTRATE] = 0x01fc,
225
226 [EDMR] = 0x0000,
227 [EDTRR] = 0x0008,
228 [EDRRR] = 0x0010,
229 [TDLAR] = 0x0018,
230 [RDLAR] = 0x0020,
231 [EESR] = 0x0028,
232 [EESIPR] = 0x0030,
233 [TRSCER] = 0x0038,
234 [RMFCR] = 0x0040,
235 [TFTR] = 0x0048,
236 [FDR] = 0x0050,
237 [RMCR] = 0x0058,
238 [TFUCR] = 0x0064,
239 [RFOCR] = 0x0068,
240 [FCFTR] = 0x0070,
241 [RPADIR] = 0x0078,
242 [TRIMD] = 0x007c,
243 [RBWAR] = 0x00c8,
244 [RDFAR] = 0x00cc,
245 [TBRAR] = 0x00d4,
246 [TDFAR] = 0x00d8,
247 };
248
249 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
250 [EDMR] = 0x0000,
251 [EDTRR] = 0x0004,
252 [EDRRR] = 0x0008,
253 [TDLAR] = 0x000c,
254 [RDLAR] = 0x0010,
255 [EESR] = 0x0014,
256 [EESIPR] = 0x0018,
257 [TRSCER] = 0x001c,
258 [RMFCR] = 0x0020,
259 [TFTR] = 0x0024,
260 [FDR] = 0x0028,
261 [RMCR] = 0x002c,
262 [EDOCR] = 0x0030,
263 [FCFTR] = 0x0034,
264 [RPADIR] = 0x0038,
265 [TRIMD] = 0x003c,
266 [RBWAR] = 0x0040,
267 [RDFAR] = 0x0044,
268 [TBRAR] = 0x004c,
269 [TDFAR] = 0x0050,
270
271 [ECMR] = 0x0160,
272 [ECSR] = 0x0164,
273 [ECSIPR] = 0x0168,
274 [PIR] = 0x016c,
275 [MAHR] = 0x0170,
276 [MALR] = 0x0174,
277 [RFLR] = 0x0178,
278 [PSR] = 0x017c,
279 [TROCR] = 0x0180,
280 [CDCR] = 0x0184,
281 [LCCR] = 0x0188,
282 [CNDCR] = 0x018c,
283 [CEFCR] = 0x0194,
284 [FRECR] = 0x0198,
285 [TSFRCR] = 0x019c,
286 [TLFRCR] = 0x01a0,
287 [RFCR] = 0x01a4,
288 [MAFCR] = 0x01a8,
289 [IPGR] = 0x01b4,
290 [APR] = 0x01b8,
291 [MPR] = 0x01bc,
292 [TPAUSER] = 0x01c4,
293 [BCFR] = 0x01cc,
294
295 [ARSTR] = 0x0000,
296 [TSU_CTRST] = 0x0004,
297 [TSU_FWEN0] = 0x0010,
298 [TSU_FWEN1] = 0x0014,
299 [TSU_FCM] = 0x0018,
300 [TSU_BSYSL0] = 0x0020,
301 [TSU_BSYSL1] = 0x0024,
302 [TSU_PRISL0] = 0x0028,
303 [TSU_PRISL1] = 0x002c,
304 [TSU_FWSL0] = 0x0030,
305 [TSU_FWSL1] = 0x0034,
306 [TSU_FWSLC] = 0x0038,
307 [TSU_QTAGM0] = 0x0040,
308 [TSU_QTAGM1] = 0x0044,
309 [TSU_ADQT0] = 0x0048,
310 [TSU_ADQT1] = 0x004c,
311 [TSU_FWSR] = 0x0050,
312 [TSU_FWINMK] = 0x0054,
313 [TSU_ADSBSY] = 0x0060,
314 [TSU_TEN] = 0x0064,
315 [TSU_POST1] = 0x0070,
316 [TSU_POST2] = 0x0074,
317 [TSU_POST3] = 0x0078,
318 [TSU_POST4] = 0x007c,
319
320 [TXNLCR0] = 0x0080,
321 [TXALCR0] = 0x0084,
322 [RXNLCR0] = 0x0088,
323 [RXALCR0] = 0x008c,
324 [FWNLCR0] = 0x0090,
325 [FWALCR0] = 0x0094,
326 [TXNLCR1] = 0x00a0,
327 [TXALCR1] = 0x00a0,
328 [RXNLCR1] = 0x00a8,
329 [RXALCR1] = 0x00ac,
330 [FWNLCR1] = 0x00b0,
331 [FWALCR1] = 0x00b4,
332
333 [TSU_ADRH0] = 0x0100,
334 [TSU_ADRL0] = 0x0104,
335 [TSU_ADRL31] = 0x01fc,
336 };
337
338 static int sh_eth_is_gether(struct sh_eth_private *mdp)
339 {
340 if (mdp->reg_offset == sh_eth_offset_gigabit)
341 return 1;
342 else
343 return 0;
344 }
345
346 static void sh_eth_select_mii(struct net_device *ndev)
347 {
348 u32 value = 0x0;
349 struct sh_eth_private *mdp = netdev_priv(ndev);
350
351 switch (mdp->phy_interface) {
352 case PHY_INTERFACE_MODE_GMII:
353 value = 0x2;
354 break;
355 case PHY_INTERFACE_MODE_MII:
356 value = 0x1;
357 break;
358 case PHY_INTERFACE_MODE_RMII:
359 value = 0x0;
360 break;
361 default:
362 pr_warn("PHY interface mode was not setup. Set to MII.\n");
363 value = 0x1;
364 break;
365 }
366
367 sh_eth_write(ndev, value, RMII_MII);
368 }
369
370 static void sh_eth_set_duplex(struct net_device *ndev)
371 {
372 struct sh_eth_private *mdp = netdev_priv(ndev);
373
374 if (mdp->duplex) /* Full */
375 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
376 else /* Half */
377 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
378 }
379
380 /* There is CPU dependent code */
381 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
382 {
383 struct sh_eth_private *mdp = netdev_priv(ndev);
384
385 switch (mdp->speed) {
386 case 10: /* 10BASE */
387 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
388 break;
389 case 100:/* 100BASE */
390 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
391 break;
392 default:
393 break;
394 }
395 }
396
397 /* R8A7778/9 */
398 static struct sh_eth_cpu_data r8a777x_data = {
399 .set_duplex = sh_eth_set_duplex,
400 .set_rate = sh_eth_set_rate_r8a777x,
401
402 .register_type = SH_ETH_REG_FAST_RCAR,
403
404 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
405 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
406 .eesipr_value = 0x01ff009f,
407
408 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
409 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
410 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
411 EESR_ECI,
412
413 .apr = 1,
414 .mpr = 1,
415 .tpauser = 1,
416 .hw_swap = 1,
417 };
418
419 /* R8A7790 */
420 static struct sh_eth_cpu_data r8a7790_data = {
421 .set_duplex = sh_eth_set_duplex,
422 .set_rate = sh_eth_set_rate_r8a777x,
423
424 .register_type = SH_ETH_REG_FAST_RCAR,
425
426 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
427 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
428 .eesipr_value = 0x01ff009f,
429
430 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
431 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
432 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
433 EESR_ECI,
434
435 .apr = 1,
436 .mpr = 1,
437 .tpauser = 1,
438 .hw_swap = 1,
439 .rmiimode = 1,
440 .shift_rd0 = 1,
441 };
442
443 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
444 {
445 struct sh_eth_private *mdp = netdev_priv(ndev);
446
447 switch (mdp->speed) {
448 case 10: /* 10BASE */
449 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
450 break;
451 case 100:/* 100BASE */
452 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
453 break;
454 default:
455 break;
456 }
457 }
458
459 /* SH7724 */
460 static struct sh_eth_cpu_data sh7724_data = {
461 .set_duplex = sh_eth_set_duplex,
462 .set_rate = sh_eth_set_rate_sh7724,
463
464 .register_type = SH_ETH_REG_FAST_SH4,
465
466 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
467 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
468 .eesipr_value = 0x01ff009f,
469
470 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
471 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
472 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
473 EESR_ECI,
474
475 .apr = 1,
476 .mpr = 1,
477 .tpauser = 1,
478 .hw_swap = 1,
479 .rpadir = 1,
480 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
481 };
482
483 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
484 {
485 struct sh_eth_private *mdp = netdev_priv(ndev);
486
487 switch (mdp->speed) {
488 case 10: /* 10BASE */
489 sh_eth_write(ndev, 0, RTRATE);
490 break;
491 case 100:/* 100BASE */
492 sh_eth_write(ndev, 1, RTRATE);
493 break;
494 default:
495 break;
496 }
497 }
498
499 /* SH7757 */
500 static struct sh_eth_cpu_data sh7757_data = {
501 .set_duplex = sh_eth_set_duplex,
502 .set_rate = sh_eth_set_rate_sh7757,
503
504 .register_type = SH_ETH_REG_FAST_SH4,
505
506 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
507
508 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
509 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
510 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
511 EESR_ECI,
512
513 .irq_flags = IRQF_SHARED,
514 .apr = 1,
515 .mpr = 1,
516 .tpauser = 1,
517 .hw_swap = 1,
518 .no_ade = 1,
519 .rpadir = 1,
520 .rpadir_value = 2 << 16,
521 };
522
523 #define SH_GIGA_ETH_BASE 0xfee00000UL
524 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
525 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
526 static void sh_eth_chip_reset_giga(struct net_device *ndev)
527 {
528 int i;
529 unsigned long mahr[2], malr[2];
530
531 /* save MAHR and MALR */
532 for (i = 0; i < 2; i++) {
533 malr[i] = ioread32((void *)GIGA_MALR(i));
534 mahr[i] = ioread32((void *)GIGA_MAHR(i));
535 }
536
537 /* reset device */
538 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
539 mdelay(1);
540
541 /* restore MAHR and MALR */
542 for (i = 0; i < 2; i++) {
543 iowrite32(malr[i], (void *)GIGA_MALR(i));
544 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
545 }
546 }
547
548 static void sh_eth_set_rate_giga(struct net_device *ndev)
549 {
550 struct sh_eth_private *mdp = netdev_priv(ndev);
551
552 switch (mdp->speed) {
553 case 10: /* 10BASE */
554 sh_eth_write(ndev, 0x00000000, GECMR);
555 break;
556 case 100:/* 100BASE */
557 sh_eth_write(ndev, 0x00000010, GECMR);
558 break;
559 case 1000: /* 1000BASE */
560 sh_eth_write(ndev, 0x00000020, GECMR);
561 break;
562 default:
563 break;
564 }
565 }
566
567 /* SH7757(GETHERC) */
568 static struct sh_eth_cpu_data sh7757_data_giga = {
569 .chip_reset = sh_eth_chip_reset_giga,
570 .set_duplex = sh_eth_set_duplex,
571 .set_rate = sh_eth_set_rate_giga,
572
573 .register_type = SH_ETH_REG_GIGABIT,
574
575 .ecsr_value = ECSR_ICD | ECSR_MPD,
576 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
577 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
578
579 .tx_check = EESR_TC1 | EESR_FTC,
580 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
581 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
582 EESR_TDE | EESR_ECI,
583 .fdr_value = 0x0000072f,
584
585 .irq_flags = IRQF_SHARED,
586 .apr = 1,
587 .mpr = 1,
588 .tpauser = 1,
589 .bculr = 1,
590 .hw_swap = 1,
591 .rpadir = 1,
592 .rpadir_value = 2 << 16,
593 .no_trimd = 1,
594 .no_ade = 1,
595 .tsu = 1,
596 };
597
598 static void sh_eth_chip_reset(struct net_device *ndev)
599 {
600 struct sh_eth_private *mdp = netdev_priv(ndev);
601
602 /* reset device */
603 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
604 mdelay(1);
605 }
606
607 static void sh_eth_set_rate_gether(struct net_device *ndev)
608 {
609 struct sh_eth_private *mdp = netdev_priv(ndev);
610
611 switch (mdp->speed) {
612 case 10: /* 10BASE */
613 sh_eth_write(ndev, GECMR_10, GECMR);
614 break;
615 case 100:/* 100BASE */
616 sh_eth_write(ndev, GECMR_100, GECMR);
617 break;
618 case 1000: /* 1000BASE */
619 sh_eth_write(ndev, GECMR_1000, GECMR);
620 break;
621 default:
622 break;
623 }
624 }
625
626 /* SH7734 */
627 static struct sh_eth_cpu_data sh7734_data = {
628 .chip_reset = sh_eth_chip_reset,
629 .set_duplex = sh_eth_set_duplex,
630 .set_rate = sh_eth_set_rate_gether,
631
632 .register_type = SH_ETH_REG_GIGABIT,
633
634 .ecsr_value = ECSR_ICD | ECSR_MPD,
635 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
636 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
637
638 .tx_check = EESR_TC1 | EESR_FTC,
639 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
640 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
641 EESR_TDE | EESR_ECI,
642
643 .apr = 1,
644 .mpr = 1,
645 .tpauser = 1,
646 .bculr = 1,
647 .hw_swap = 1,
648 .no_trimd = 1,
649 .no_ade = 1,
650 .tsu = 1,
651 .hw_crc = 1,
652 .select_mii = 1,
653 };
654
655 /* SH7763 */
656 static struct sh_eth_cpu_data sh7763_data = {
657 .chip_reset = sh_eth_chip_reset,
658 .set_duplex = sh_eth_set_duplex,
659 .set_rate = sh_eth_set_rate_gether,
660
661 .register_type = SH_ETH_REG_GIGABIT,
662
663 .ecsr_value = ECSR_ICD | ECSR_MPD,
664 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
665 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
666
667 .tx_check = EESR_TC1 | EESR_FTC,
668 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
669 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
670 EESR_ECI,
671
672 .apr = 1,
673 .mpr = 1,
674 .tpauser = 1,
675 .bculr = 1,
676 .hw_swap = 1,
677 .no_trimd = 1,
678 .no_ade = 1,
679 .tsu = 1,
680 .irq_flags = IRQF_SHARED,
681 };
682
683 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
684 {
685 struct sh_eth_private *mdp = netdev_priv(ndev);
686
687 /* reset device */
688 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
689 mdelay(1);
690
691 sh_eth_select_mii(ndev);
692 }
693
694 /* R8A7740 */
695 static struct sh_eth_cpu_data r8a7740_data = {
696 .chip_reset = sh_eth_chip_reset_r8a7740,
697 .set_duplex = sh_eth_set_duplex,
698 .set_rate = sh_eth_set_rate_gether,
699
700 .register_type = SH_ETH_REG_GIGABIT,
701
702 .ecsr_value = ECSR_ICD | ECSR_MPD,
703 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
704 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
705
706 .tx_check = EESR_TC1 | EESR_FTC,
707 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
708 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
709 EESR_TDE | EESR_ECI,
710 .fdr_value = 0x0000070f,
711
712 .apr = 1,
713 .mpr = 1,
714 .tpauser = 1,
715 .bculr = 1,
716 .hw_swap = 1,
717 .rpadir = 1,
718 .rpadir_value = 2 << 16,
719 .no_trimd = 1,
720 .no_ade = 1,
721 .tsu = 1,
722 .select_mii = 1,
723 .shift_rd0 = 1,
724 };
725
726 static struct sh_eth_cpu_data sh7619_data = {
727 .register_type = SH_ETH_REG_FAST_SH3_SH2,
728
729 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
730
731 .apr = 1,
732 .mpr = 1,
733 .tpauser = 1,
734 .hw_swap = 1,
735 };
736
737 static struct sh_eth_cpu_data sh771x_data = {
738 .register_type = SH_ETH_REG_FAST_SH3_SH2,
739
740 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
741 .tsu = 1,
742 };
743
744 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
745 {
746 if (!cd->ecsr_value)
747 cd->ecsr_value = DEFAULT_ECSR_INIT;
748
749 if (!cd->ecsipr_value)
750 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
751
752 if (!cd->fcftr_value)
753 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
754 DEFAULT_FIFO_F_D_RFD;
755
756 if (!cd->fdr_value)
757 cd->fdr_value = DEFAULT_FDR_INIT;
758
759 if (!cd->tx_check)
760 cd->tx_check = DEFAULT_TX_CHECK;
761
762 if (!cd->eesr_err_check)
763 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
764 }
765
766 static int sh_eth_check_reset(struct net_device *ndev)
767 {
768 int ret = 0;
769 int cnt = 100;
770
771 while (cnt > 0) {
772 if (!(sh_eth_read(ndev, EDMR) & 0x3))
773 break;
774 mdelay(1);
775 cnt--;
776 }
777 if (cnt <= 0) {
778 pr_err("Device reset failed\n");
779 ret = -ETIMEDOUT;
780 }
781 return ret;
782 }
783
784 static int sh_eth_reset(struct net_device *ndev)
785 {
786 struct sh_eth_private *mdp = netdev_priv(ndev);
787 int ret = 0;
788
789 if (sh_eth_is_gether(mdp)) {
790 sh_eth_write(ndev, EDSR_ENALL, EDSR);
791 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
792 EDMR);
793
794 ret = sh_eth_check_reset(ndev);
795 if (ret)
796 goto out;
797
798 /* Table Init */
799 sh_eth_write(ndev, 0x0, TDLAR);
800 sh_eth_write(ndev, 0x0, TDFAR);
801 sh_eth_write(ndev, 0x0, TDFXR);
802 sh_eth_write(ndev, 0x0, TDFFR);
803 sh_eth_write(ndev, 0x0, RDLAR);
804 sh_eth_write(ndev, 0x0, RDFAR);
805 sh_eth_write(ndev, 0x0, RDFXR);
806 sh_eth_write(ndev, 0x0, RDFFR);
807
808 /* Reset HW CRC register */
809 if (mdp->cd->hw_crc)
810 sh_eth_write(ndev, 0x0, CSMR);
811
812 /* Select MII mode */
813 if (mdp->cd->select_mii)
814 sh_eth_select_mii(ndev);
815 } else {
816 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
817 EDMR);
818 mdelay(3);
819 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
820 EDMR);
821 }
822
823 out:
824 return ret;
825 }
826
827 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
828 static void sh_eth_set_receive_align(struct sk_buff *skb)
829 {
830 int reserve;
831
832 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
833 if (reserve)
834 skb_reserve(skb, reserve);
835 }
836 #else
837 static void sh_eth_set_receive_align(struct sk_buff *skb)
838 {
839 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
840 }
841 #endif
842
843
844 /* CPU <-> EDMAC endian convert */
845 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
846 {
847 switch (mdp->edmac_endian) {
848 case EDMAC_LITTLE_ENDIAN:
849 return cpu_to_le32(x);
850 case EDMAC_BIG_ENDIAN:
851 return cpu_to_be32(x);
852 }
853 return x;
854 }
855
856 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
857 {
858 switch (mdp->edmac_endian) {
859 case EDMAC_LITTLE_ENDIAN:
860 return le32_to_cpu(x);
861 case EDMAC_BIG_ENDIAN:
862 return be32_to_cpu(x);
863 }
864 return x;
865 }
866
867 /*
868 * Program the hardware MAC address from dev->dev_addr.
869 */
870 static void update_mac_address(struct net_device *ndev)
871 {
872 sh_eth_write(ndev,
873 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
874 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
875 sh_eth_write(ndev,
876 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
877 }
878
879 /*
880 * Get MAC address from SuperH MAC address register
881 *
882 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
883 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
884 * When you want use this device, you must set MAC address in bootloader.
885 *
886 */
887 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
888 {
889 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
890 memcpy(ndev->dev_addr, mac, 6);
891 } else {
892 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
893 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
894 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
895 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
896 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
897 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
898 }
899 }
900
901 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
902 {
903 if (sh_eth_is_gether(mdp))
904 return EDTRR_TRNS_GETHER;
905 else
906 return EDTRR_TRNS_ETHER;
907 }
908
909 struct bb_info {
910 void (*set_gate)(void *addr);
911 struct mdiobb_ctrl ctrl;
912 void *addr;
913 u32 mmd_msk;/* MMD */
914 u32 mdo_msk;
915 u32 mdi_msk;
916 u32 mdc_msk;
917 };
918
919 /* PHY bit set */
920 static void bb_set(void *addr, u32 msk)
921 {
922 iowrite32(ioread32(addr) | msk, addr);
923 }
924
925 /* PHY bit clear */
926 static void bb_clr(void *addr, u32 msk)
927 {
928 iowrite32((ioread32(addr) & ~msk), addr);
929 }
930
931 /* PHY bit read */
932 static int bb_read(void *addr, u32 msk)
933 {
934 return (ioread32(addr) & msk) != 0;
935 }
936
937 /* Data I/O pin control */
938 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
939 {
940 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
941
942 if (bitbang->set_gate)
943 bitbang->set_gate(bitbang->addr);
944
945 if (bit)
946 bb_set(bitbang->addr, bitbang->mmd_msk);
947 else
948 bb_clr(bitbang->addr, bitbang->mmd_msk);
949 }
950
951 /* Set bit data*/
952 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
953 {
954 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
955
956 if (bitbang->set_gate)
957 bitbang->set_gate(bitbang->addr);
958
959 if (bit)
960 bb_set(bitbang->addr, bitbang->mdo_msk);
961 else
962 bb_clr(bitbang->addr, bitbang->mdo_msk);
963 }
964
965 /* Get bit data*/
966 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
967 {
968 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
969
970 if (bitbang->set_gate)
971 bitbang->set_gate(bitbang->addr);
972
973 return bb_read(bitbang->addr, bitbang->mdi_msk);
974 }
975
976 /* MDC pin control */
977 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
978 {
979 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
980
981 if (bitbang->set_gate)
982 bitbang->set_gate(bitbang->addr);
983
984 if (bit)
985 bb_set(bitbang->addr, bitbang->mdc_msk);
986 else
987 bb_clr(bitbang->addr, bitbang->mdc_msk);
988 }
989
990 /* mdio bus control struct */
991 static struct mdiobb_ops bb_ops = {
992 .owner = THIS_MODULE,
993 .set_mdc = sh_mdc_ctrl,
994 .set_mdio_dir = sh_mmd_ctrl,
995 .set_mdio_data = sh_set_mdio,
996 .get_mdio_data = sh_get_mdio,
997 };
998
999 /* free skb and descriptor buffer */
1000 static void sh_eth_ring_free(struct net_device *ndev)
1001 {
1002 struct sh_eth_private *mdp = netdev_priv(ndev);
1003 int i;
1004
1005 /* Free Rx skb ringbuffer */
1006 if (mdp->rx_skbuff) {
1007 for (i = 0; i < mdp->num_rx_ring; i++) {
1008 if (mdp->rx_skbuff[i])
1009 dev_kfree_skb(mdp->rx_skbuff[i]);
1010 }
1011 }
1012 kfree(mdp->rx_skbuff);
1013 mdp->rx_skbuff = NULL;
1014
1015 /* Free Tx skb ringbuffer */
1016 if (mdp->tx_skbuff) {
1017 for (i = 0; i < mdp->num_tx_ring; i++) {
1018 if (mdp->tx_skbuff[i])
1019 dev_kfree_skb(mdp->tx_skbuff[i]);
1020 }
1021 }
1022 kfree(mdp->tx_skbuff);
1023 mdp->tx_skbuff = NULL;
1024 }
1025
1026 /* format skb and descriptor buffer */
1027 static void sh_eth_ring_format(struct net_device *ndev)
1028 {
1029 struct sh_eth_private *mdp = netdev_priv(ndev);
1030 int i;
1031 struct sk_buff *skb;
1032 struct sh_eth_rxdesc *rxdesc = NULL;
1033 struct sh_eth_txdesc *txdesc = NULL;
1034 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1035 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1036
1037 mdp->cur_rx = mdp->cur_tx = 0;
1038 mdp->dirty_rx = mdp->dirty_tx = 0;
1039
1040 memset(mdp->rx_ring, 0, rx_ringsize);
1041
1042 /* build Rx ring buffer */
1043 for (i = 0; i < mdp->num_rx_ring; i++) {
1044 /* skb */
1045 mdp->rx_skbuff[i] = NULL;
1046 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1047 mdp->rx_skbuff[i] = skb;
1048 if (skb == NULL)
1049 break;
1050 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1051 DMA_FROM_DEVICE);
1052 sh_eth_set_receive_align(skb);
1053
1054 /* RX descriptor */
1055 rxdesc = &mdp->rx_ring[i];
1056 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1057 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1058
1059 /* The size of the buffer is 16 byte boundary. */
1060 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1061 /* Rx descriptor address set */
1062 if (i == 0) {
1063 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1064 if (sh_eth_is_gether(mdp))
1065 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1066 }
1067 }
1068
1069 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1070
1071 /* Mark the last entry as wrapping the ring. */
1072 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1073
1074 memset(mdp->tx_ring, 0, tx_ringsize);
1075
1076 /* build Tx ring buffer */
1077 for (i = 0; i < mdp->num_tx_ring; i++) {
1078 mdp->tx_skbuff[i] = NULL;
1079 txdesc = &mdp->tx_ring[i];
1080 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1081 txdesc->buffer_length = 0;
1082 if (i == 0) {
1083 /* Tx descriptor address set */
1084 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1085 if (sh_eth_is_gether(mdp))
1086 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1087 }
1088 }
1089
1090 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1091 }
1092
1093 /* Get skb and descriptor buffer */
1094 static int sh_eth_ring_init(struct net_device *ndev)
1095 {
1096 struct sh_eth_private *mdp = netdev_priv(ndev);
1097 int rx_ringsize, tx_ringsize, ret = 0;
1098
1099 /*
1100 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1101 * card needs room to do 8 byte alignment, +2 so we can reserve
1102 * the first 2 bytes, and +16 gets room for the status word from the
1103 * card.
1104 */
1105 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1106 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1107 if (mdp->cd->rpadir)
1108 mdp->rx_buf_sz += NET_IP_ALIGN;
1109
1110 /* Allocate RX and TX skb rings */
1111 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1112 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1113 if (!mdp->rx_skbuff) {
1114 ret = -ENOMEM;
1115 return ret;
1116 }
1117
1118 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1119 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1120 if (!mdp->tx_skbuff) {
1121 ret = -ENOMEM;
1122 goto skb_ring_free;
1123 }
1124
1125 /* Allocate all Rx descriptors. */
1126 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1127 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1128 GFP_KERNEL);
1129 if (!mdp->rx_ring) {
1130 ret = -ENOMEM;
1131 goto desc_ring_free;
1132 }
1133
1134 mdp->dirty_rx = 0;
1135
1136 /* Allocate all Tx descriptors. */
1137 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1138 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1139 GFP_KERNEL);
1140 if (!mdp->tx_ring) {
1141 ret = -ENOMEM;
1142 goto desc_ring_free;
1143 }
1144 return ret;
1145
1146 desc_ring_free:
1147 /* free DMA buffer */
1148 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1149
1150 skb_ring_free:
1151 /* Free Rx and Tx skb ring buffer */
1152 sh_eth_ring_free(ndev);
1153 mdp->tx_ring = NULL;
1154 mdp->rx_ring = NULL;
1155
1156 return ret;
1157 }
1158
1159 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1160 {
1161 int ringsize;
1162
1163 if (mdp->rx_ring) {
1164 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1165 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1166 mdp->rx_desc_dma);
1167 mdp->rx_ring = NULL;
1168 }
1169
1170 if (mdp->tx_ring) {
1171 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1172 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1173 mdp->tx_desc_dma);
1174 mdp->tx_ring = NULL;
1175 }
1176 }
1177
1178 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1179 {
1180 int ret = 0;
1181 struct sh_eth_private *mdp = netdev_priv(ndev);
1182 u32 val;
1183
1184 /* Soft Reset */
1185 ret = sh_eth_reset(ndev);
1186 if (ret)
1187 goto out;
1188
1189 if (mdp->cd->rmiimode)
1190 sh_eth_write(ndev, 0x1, RMIIMODE);
1191
1192 /* Descriptor format */
1193 sh_eth_ring_format(ndev);
1194 if (mdp->cd->rpadir)
1195 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1196
1197 /* all sh_eth int mask */
1198 sh_eth_write(ndev, 0, EESIPR);
1199
1200 #if defined(__LITTLE_ENDIAN)
1201 if (mdp->cd->hw_swap)
1202 sh_eth_write(ndev, EDMR_EL, EDMR);
1203 else
1204 #endif
1205 sh_eth_write(ndev, 0, EDMR);
1206
1207 /* FIFO size set */
1208 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1209 sh_eth_write(ndev, 0, TFTR);
1210
1211 /* Frame recv control (enable multiple-packets per rx irq) */
1212 sh_eth_write(ndev, 0x00000001, RMCR);
1213
1214 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1215
1216 if (mdp->cd->bculr)
1217 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1218
1219 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1220
1221 if (!mdp->cd->no_trimd)
1222 sh_eth_write(ndev, 0, TRIMD);
1223
1224 /* Recv frame limit set register */
1225 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1226 RFLR);
1227
1228 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1229 if (start)
1230 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1231
1232 /* PAUSE Prohibition */
1233 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1234 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1235
1236 sh_eth_write(ndev, val, ECMR);
1237
1238 if (mdp->cd->set_rate)
1239 mdp->cd->set_rate(ndev);
1240
1241 /* E-MAC Status Register clear */
1242 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1243
1244 /* E-MAC Interrupt Enable register */
1245 if (start)
1246 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1247
1248 /* Set MAC address */
1249 update_mac_address(ndev);
1250
1251 /* mask reset */
1252 if (mdp->cd->apr)
1253 sh_eth_write(ndev, APR_AP, APR);
1254 if (mdp->cd->mpr)
1255 sh_eth_write(ndev, MPR_MP, MPR);
1256 if (mdp->cd->tpauser)
1257 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1258
1259 if (start) {
1260 /* Setting the Rx mode will start the Rx process. */
1261 sh_eth_write(ndev, EDRRR_R, EDRRR);
1262
1263 netif_start_queue(ndev);
1264 }
1265
1266 out:
1267 return ret;
1268 }
1269
1270 /* free Tx skb function */
1271 static int sh_eth_txfree(struct net_device *ndev)
1272 {
1273 struct sh_eth_private *mdp = netdev_priv(ndev);
1274 struct sh_eth_txdesc *txdesc;
1275 int freeNum = 0;
1276 int entry = 0;
1277
1278 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1279 entry = mdp->dirty_tx % mdp->num_tx_ring;
1280 txdesc = &mdp->tx_ring[entry];
1281 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1282 break;
1283 /* Free the original skb. */
1284 if (mdp->tx_skbuff[entry]) {
1285 dma_unmap_single(&ndev->dev, txdesc->addr,
1286 txdesc->buffer_length, DMA_TO_DEVICE);
1287 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1288 mdp->tx_skbuff[entry] = NULL;
1289 freeNum++;
1290 }
1291 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1292 if (entry >= mdp->num_tx_ring - 1)
1293 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1294
1295 ndev->stats.tx_packets++;
1296 ndev->stats.tx_bytes += txdesc->buffer_length;
1297 }
1298 return freeNum;
1299 }
1300
1301 /* Packet receive function */
1302 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1303 {
1304 struct sh_eth_private *mdp = netdev_priv(ndev);
1305 struct sh_eth_rxdesc *rxdesc;
1306
1307 int entry = mdp->cur_rx % mdp->num_rx_ring;
1308 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1309 struct sk_buff *skb;
1310 int exceeded = 0;
1311 u16 pkt_len = 0;
1312 u32 desc_status;
1313
1314 rxdesc = &mdp->rx_ring[entry];
1315 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1316 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1317 pkt_len = rxdesc->frame_length;
1318
1319 if (--boguscnt < 0)
1320 break;
1321
1322 if (*quota <= 0) {
1323 exceeded = 1;
1324 break;
1325 }
1326 (*quota)--;
1327
1328 if (!(desc_status & RDFEND))
1329 ndev->stats.rx_length_errors++;
1330
1331 /*
1332 * In case of almost all GETHER/ETHERs, the Receive Frame State
1333 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1334 * bit 0. However, in case of the R8A7740's GETHER, the RFS
1335 * bits are from bit 25 to bit 16. So, the driver needs right
1336 * shifting by 16.
1337 */
1338 if (mdp->cd->shift_rd0)
1339 desc_status >>= 16;
1340
1341 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1342 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1343 ndev->stats.rx_errors++;
1344 if (desc_status & RD_RFS1)
1345 ndev->stats.rx_crc_errors++;
1346 if (desc_status & RD_RFS2)
1347 ndev->stats.rx_frame_errors++;
1348 if (desc_status & RD_RFS3)
1349 ndev->stats.rx_length_errors++;
1350 if (desc_status & RD_RFS4)
1351 ndev->stats.rx_length_errors++;
1352 if (desc_status & RD_RFS6)
1353 ndev->stats.rx_missed_errors++;
1354 if (desc_status & RD_RFS10)
1355 ndev->stats.rx_over_errors++;
1356 } else {
1357 if (!mdp->cd->hw_swap)
1358 sh_eth_soft_swap(
1359 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1360 pkt_len + 2);
1361 skb = mdp->rx_skbuff[entry];
1362 mdp->rx_skbuff[entry] = NULL;
1363 if (mdp->cd->rpadir)
1364 skb_reserve(skb, NET_IP_ALIGN);
1365 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1366 mdp->rx_buf_sz,
1367 DMA_FROM_DEVICE);
1368 skb_put(skb, pkt_len);
1369 skb->protocol = eth_type_trans(skb, ndev);
1370 netif_receive_skb(skb);
1371 ndev->stats.rx_packets++;
1372 ndev->stats.rx_bytes += pkt_len;
1373 }
1374 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1375 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1376 rxdesc = &mdp->rx_ring[entry];
1377 }
1378
1379 /* Refill the Rx ring buffers. */
1380 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1381 entry = mdp->dirty_rx % mdp->num_rx_ring;
1382 rxdesc = &mdp->rx_ring[entry];
1383 /* The size of the buffer is 16 byte boundary. */
1384 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1385
1386 if (mdp->rx_skbuff[entry] == NULL) {
1387 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1388 mdp->rx_skbuff[entry] = skb;
1389 if (skb == NULL)
1390 break; /* Better luck next round. */
1391 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1392 DMA_FROM_DEVICE);
1393 sh_eth_set_receive_align(skb);
1394
1395 skb_checksum_none_assert(skb);
1396 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1397 }
1398 if (entry >= mdp->num_rx_ring - 1)
1399 rxdesc->status |=
1400 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1401 else
1402 rxdesc->status |=
1403 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1404 }
1405
1406 /* Restart Rx engine if stopped. */
1407 /* If we don't need to check status, don't. -KDU */
1408 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1409 /* fix the values for the next receiving if RDE is set */
1410 if (intr_status & EESR_RDE)
1411 mdp->cur_rx = mdp->dirty_rx =
1412 (sh_eth_read(ndev, RDFAR) -
1413 sh_eth_read(ndev, RDLAR)) >> 4;
1414 sh_eth_write(ndev, EDRRR_R, EDRRR);
1415 }
1416
1417 return exceeded;
1418 }
1419
1420 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1421 {
1422 /* disable tx and rx */
1423 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1424 ~(ECMR_RE | ECMR_TE), ECMR);
1425 }
1426
1427 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1428 {
1429 /* enable tx and rx */
1430 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1431 (ECMR_RE | ECMR_TE), ECMR);
1432 }
1433
1434 /* error control function */
1435 static void sh_eth_error(struct net_device *ndev, int intr_status)
1436 {
1437 struct sh_eth_private *mdp = netdev_priv(ndev);
1438 u32 felic_stat;
1439 u32 link_stat;
1440 u32 mask;
1441
1442 if (intr_status & EESR_ECI) {
1443 felic_stat = sh_eth_read(ndev, ECSR);
1444 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1445 if (felic_stat & ECSR_ICD)
1446 ndev->stats.tx_carrier_errors++;
1447 if (felic_stat & ECSR_LCHNG) {
1448 /* Link Changed */
1449 if (mdp->cd->no_psr || mdp->no_ether_link) {
1450 goto ignore_link;
1451 } else {
1452 link_stat = (sh_eth_read(ndev, PSR));
1453 if (mdp->ether_link_active_low)
1454 link_stat = ~link_stat;
1455 }
1456 if (!(link_stat & PHY_ST_LINK))
1457 sh_eth_rcv_snd_disable(ndev);
1458 else {
1459 /* Link Up */
1460 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1461 ~DMAC_M_ECI, EESIPR);
1462 /*clear int */
1463 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1464 ECSR);
1465 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1466 DMAC_M_ECI, EESIPR);
1467 /* enable tx and rx */
1468 sh_eth_rcv_snd_enable(ndev);
1469 }
1470 }
1471 }
1472
1473 ignore_link:
1474 if (intr_status & EESR_TWB) {
1475 /* Unused write back interrupt */
1476 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1477 ndev->stats.tx_aborted_errors++;
1478 if (netif_msg_tx_err(mdp))
1479 dev_err(&ndev->dev, "Transmit Abort\n");
1480 }
1481 }
1482
1483 if (intr_status & EESR_RABT) {
1484 /* Receive Abort int */
1485 if (intr_status & EESR_RFRMER) {
1486 /* Receive Frame Overflow int */
1487 ndev->stats.rx_frame_errors++;
1488 if (netif_msg_rx_err(mdp))
1489 dev_err(&ndev->dev, "Receive Abort\n");
1490 }
1491 }
1492
1493 if (intr_status & EESR_TDE) {
1494 /* Transmit Descriptor Empty int */
1495 ndev->stats.tx_fifo_errors++;
1496 if (netif_msg_tx_err(mdp))
1497 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1498 }
1499
1500 if (intr_status & EESR_TFE) {
1501 /* FIFO under flow */
1502 ndev->stats.tx_fifo_errors++;
1503 if (netif_msg_tx_err(mdp))
1504 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1505 }
1506
1507 if (intr_status & EESR_RDE) {
1508 /* Receive Descriptor Empty int */
1509 ndev->stats.rx_over_errors++;
1510
1511 if (netif_msg_rx_err(mdp))
1512 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1513 }
1514
1515 if (intr_status & EESR_RFE) {
1516 /* Receive FIFO Overflow int */
1517 ndev->stats.rx_fifo_errors++;
1518 if (netif_msg_rx_err(mdp))
1519 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1520 }
1521
1522 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1523 /* Address Error */
1524 ndev->stats.tx_fifo_errors++;
1525 if (netif_msg_tx_err(mdp))
1526 dev_err(&ndev->dev, "Address Error\n");
1527 }
1528
1529 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1530 if (mdp->cd->no_ade)
1531 mask &= ~EESR_ADE;
1532 if (intr_status & mask) {
1533 /* Tx error */
1534 u32 edtrr = sh_eth_read(ndev, EDTRR);
1535 /* dmesg */
1536 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1537 intr_status, mdp->cur_tx);
1538 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1539 mdp->dirty_tx, (u32) ndev->state, edtrr);
1540 /* dirty buffer free */
1541 sh_eth_txfree(ndev);
1542
1543 /* SH7712 BUG */
1544 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1545 /* tx dma start */
1546 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1547 }
1548 /* wakeup */
1549 netif_wake_queue(ndev);
1550 }
1551 }
1552
1553 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1554 {
1555 struct net_device *ndev = netdev;
1556 struct sh_eth_private *mdp = netdev_priv(ndev);
1557 struct sh_eth_cpu_data *cd = mdp->cd;
1558 irqreturn_t ret = IRQ_NONE;
1559 unsigned long intr_status, intr_enable;
1560
1561 spin_lock(&mdp->lock);
1562
1563 /* Get interrupt status */
1564 intr_status = sh_eth_read(ndev, EESR);
1565 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1566 * enabled since it's the one that comes thru regardless of the mask,
1567 * and we need to fully handle it in sh_eth_error() in order to quench
1568 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1569 */
1570 intr_enable = sh_eth_read(ndev, EESIPR);
1571 intr_status &= intr_enable | DMAC_M_ECI;
1572 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1573 ret = IRQ_HANDLED;
1574 else
1575 goto other_irq;
1576
1577 if (intr_status & EESR_RX_CHECK) {
1578 if (napi_schedule_prep(&mdp->napi)) {
1579 /* Mask Rx interrupts */
1580 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1581 EESIPR);
1582 __napi_schedule(&mdp->napi);
1583 } else {
1584 dev_warn(&ndev->dev,
1585 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1586 intr_status, intr_enable);
1587 }
1588 }
1589
1590 /* Tx Check */
1591 if (intr_status & cd->tx_check) {
1592 /* Clear Tx interrupts */
1593 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1594
1595 sh_eth_txfree(ndev);
1596 netif_wake_queue(ndev);
1597 }
1598
1599 if (intr_status & cd->eesr_err_check) {
1600 /* Clear error interrupts */
1601 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1602
1603 sh_eth_error(ndev, intr_status);
1604 }
1605
1606 other_irq:
1607 spin_unlock(&mdp->lock);
1608
1609 return ret;
1610 }
1611
1612 static int sh_eth_poll(struct napi_struct *napi, int budget)
1613 {
1614 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1615 napi);
1616 struct net_device *ndev = napi->dev;
1617 int quota = budget;
1618 unsigned long intr_status;
1619
1620 for (;;) {
1621 intr_status = sh_eth_read(ndev, EESR);
1622 if (!(intr_status & EESR_RX_CHECK))
1623 break;
1624 /* Clear Rx interrupts */
1625 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1626
1627 if (sh_eth_rx(ndev, intr_status, &quota))
1628 goto out;
1629 }
1630
1631 napi_complete(napi);
1632
1633 /* Reenable Rx interrupts */
1634 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1635 out:
1636 return budget - quota;
1637 }
1638
1639 /* PHY state control function */
1640 static void sh_eth_adjust_link(struct net_device *ndev)
1641 {
1642 struct sh_eth_private *mdp = netdev_priv(ndev);
1643 struct phy_device *phydev = mdp->phydev;
1644 int new_state = 0;
1645
1646 if (phydev->link) {
1647 if (phydev->duplex != mdp->duplex) {
1648 new_state = 1;
1649 mdp->duplex = phydev->duplex;
1650 if (mdp->cd->set_duplex)
1651 mdp->cd->set_duplex(ndev);
1652 }
1653
1654 if (phydev->speed != mdp->speed) {
1655 new_state = 1;
1656 mdp->speed = phydev->speed;
1657 if (mdp->cd->set_rate)
1658 mdp->cd->set_rate(ndev);
1659 }
1660 if (!mdp->link) {
1661 sh_eth_write(ndev,
1662 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1663 new_state = 1;
1664 mdp->link = phydev->link;
1665 if (mdp->cd->no_psr || mdp->no_ether_link)
1666 sh_eth_rcv_snd_enable(ndev);
1667 }
1668 } else if (mdp->link) {
1669 new_state = 1;
1670 mdp->link = 0;
1671 mdp->speed = 0;
1672 mdp->duplex = -1;
1673 if (mdp->cd->no_psr || mdp->no_ether_link)
1674 sh_eth_rcv_snd_disable(ndev);
1675 }
1676
1677 if (new_state && netif_msg_link(mdp))
1678 phy_print_status(phydev);
1679 }
1680
1681 /* PHY init function */
1682 static int sh_eth_phy_init(struct net_device *ndev)
1683 {
1684 struct sh_eth_private *mdp = netdev_priv(ndev);
1685 char phy_id[MII_BUS_ID_SIZE + 3];
1686 struct phy_device *phydev = NULL;
1687
1688 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1689 mdp->mii_bus->id , mdp->phy_id);
1690
1691 mdp->link = 0;
1692 mdp->speed = 0;
1693 mdp->duplex = -1;
1694
1695 /* Try connect to PHY */
1696 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1697 mdp->phy_interface);
1698 if (IS_ERR(phydev)) {
1699 dev_err(&ndev->dev, "phy_connect failed\n");
1700 return PTR_ERR(phydev);
1701 }
1702
1703 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1704 phydev->addr, phydev->drv->name);
1705
1706 mdp->phydev = phydev;
1707
1708 return 0;
1709 }
1710
1711 /* PHY control start function */
1712 static int sh_eth_phy_start(struct net_device *ndev)
1713 {
1714 struct sh_eth_private *mdp = netdev_priv(ndev);
1715 int ret;
1716
1717 ret = sh_eth_phy_init(ndev);
1718 if (ret)
1719 return ret;
1720
1721 /* reset phy - this also wakes it from PDOWN */
1722 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1723 phy_start(mdp->phydev);
1724
1725 return 0;
1726 }
1727
1728 static int sh_eth_get_settings(struct net_device *ndev,
1729 struct ethtool_cmd *ecmd)
1730 {
1731 struct sh_eth_private *mdp = netdev_priv(ndev);
1732 unsigned long flags;
1733 int ret;
1734
1735 spin_lock_irqsave(&mdp->lock, flags);
1736 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1737 spin_unlock_irqrestore(&mdp->lock, flags);
1738
1739 return ret;
1740 }
1741
1742 static int sh_eth_set_settings(struct net_device *ndev,
1743 struct ethtool_cmd *ecmd)
1744 {
1745 struct sh_eth_private *mdp = netdev_priv(ndev);
1746 unsigned long flags;
1747 int ret;
1748
1749 spin_lock_irqsave(&mdp->lock, flags);
1750
1751 /* disable tx and rx */
1752 sh_eth_rcv_snd_disable(ndev);
1753
1754 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1755 if (ret)
1756 goto error_exit;
1757
1758 if (ecmd->duplex == DUPLEX_FULL)
1759 mdp->duplex = 1;
1760 else
1761 mdp->duplex = 0;
1762
1763 if (mdp->cd->set_duplex)
1764 mdp->cd->set_duplex(ndev);
1765
1766 error_exit:
1767 mdelay(1);
1768
1769 /* enable tx and rx */
1770 sh_eth_rcv_snd_enable(ndev);
1771
1772 spin_unlock_irqrestore(&mdp->lock, flags);
1773
1774 return ret;
1775 }
1776
1777 static int sh_eth_nway_reset(struct net_device *ndev)
1778 {
1779 struct sh_eth_private *mdp = netdev_priv(ndev);
1780 unsigned long flags;
1781 int ret;
1782
1783 spin_lock_irqsave(&mdp->lock, flags);
1784 ret = phy_start_aneg(mdp->phydev);
1785 spin_unlock_irqrestore(&mdp->lock, flags);
1786
1787 return ret;
1788 }
1789
1790 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1791 {
1792 struct sh_eth_private *mdp = netdev_priv(ndev);
1793 return mdp->msg_enable;
1794 }
1795
1796 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1797 {
1798 struct sh_eth_private *mdp = netdev_priv(ndev);
1799 mdp->msg_enable = value;
1800 }
1801
1802 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1803 "rx_current", "tx_current",
1804 "rx_dirty", "tx_dirty",
1805 };
1806 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1807
1808 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1809 {
1810 switch (sset) {
1811 case ETH_SS_STATS:
1812 return SH_ETH_STATS_LEN;
1813 default:
1814 return -EOPNOTSUPP;
1815 }
1816 }
1817
1818 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1819 struct ethtool_stats *stats, u64 *data)
1820 {
1821 struct sh_eth_private *mdp = netdev_priv(ndev);
1822 int i = 0;
1823
1824 /* device-specific stats */
1825 data[i++] = mdp->cur_rx;
1826 data[i++] = mdp->cur_tx;
1827 data[i++] = mdp->dirty_rx;
1828 data[i++] = mdp->dirty_tx;
1829 }
1830
1831 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1832 {
1833 switch (stringset) {
1834 case ETH_SS_STATS:
1835 memcpy(data, *sh_eth_gstrings_stats,
1836 sizeof(sh_eth_gstrings_stats));
1837 break;
1838 }
1839 }
1840
1841 static void sh_eth_get_ringparam(struct net_device *ndev,
1842 struct ethtool_ringparam *ring)
1843 {
1844 struct sh_eth_private *mdp = netdev_priv(ndev);
1845
1846 ring->rx_max_pending = RX_RING_MAX;
1847 ring->tx_max_pending = TX_RING_MAX;
1848 ring->rx_pending = mdp->num_rx_ring;
1849 ring->tx_pending = mdp->num_tx_ring;
1850 }
1851
1852 static int sh_eth_set_ringparam(struct net_device *ndev,
1853 struct ethtool_ringparam *ring)
1854 {
1855 struct sh_eth_private *mdp = netdev_priv(ndev);
1856 int ret;
1857
1858 if (ring->tx_pending > TX_RING_MAX ||
1859 ring->rx_pending > RX_RING_MAX ||
1860 ring->tx_pending < TX_RING_MIN ||
1861 ring->rx_pending < RX_RING_MIN)
1862 return -EINVAL;
1863 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1864 return -EINVAL;
1865
1866 if (netif_running(ndev)) {
1867 netif_tx_disable(ndev);
1868 /* Disable interrupts by clearing the interrupt mask. */
1869 sh_eth_write(ndev, 0x0000, EESIPR);
1870 /* Stop the chip's Tx and Rx processes. */
1871 sh_eth_write(ndev, 0, EDTRR);
1872 sh_eth_write(ndev, 0, EDRRR);
1873 synchronize_irq(ndev->irq);
1874 }
1875
1876 /* Free all the skbuffs in the Rx queue. */
1877 sh_eth_ring_free(ndev);
1878 /* Free DMA buffer */
1879 sh_eth_free_dma_buffer(mdp);
1880
1881 /* Set new parameters */
1882 mdp->num_rx_ring = ring->rx_pending;
1883 mdp->num_tx_ring = ring->tx_pending;
1884
1885 ret = sh_eth_ring_init(ndev);
1886 if (ret < 0) {
1887 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1888 return ret;
1889 }
1890 ret = sh_eth_dev_init(ndev, false);
1891 if (ret < 0) {
1892 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1893 return ret;
1894 }
1895
1896 if (netif_running(ndev)) {
1897 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1898 /* Setting the Rx mode will start the Rx process. */
1899 sh_eth_write(ndev, EDRRR_R, EDRRR);
1900 netif_wake_queue(ndev);
1901 }
1902
1903 return 0;
1904 }
1905
1906 static const struct ethtool_ops sh_eth_ethtool_ops = {
1907 .get_settings = sh_eth_get_settings,
1908 .set_settings = sh_eth_set_settings,
1909 .nway_reset = sh_eth_nway_reset,
1910 .get_msglevel = sh_eth_get_msglevel,
1911 .set_msglevel = sh_eth_set_msglevel,
1912 .get_link = ethtool_op_get_link,
1913 .get_strings = sh_eth_get_strings,
1914 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1915 .get_sset_count = sh_eth_get_sset_count,
1916 .get_ringparam = sh_eth_get_ringparam,
1917 .set_ringparam = sh_eth_set_ringparam,
1918 };
1919
1920 /* network device open function */
1921 static int sh_eth_open(struct net_device *ndev)
1922 {
1923 int ret = 0;
1924 struct sh_eth_private *mdp = netdev_priv(ndev);
1925
1926 pm_runtime_get_sync(&mdp->pdev->dev);
1927
1928 napi_enable(&mdp->napi);
1929
1930 ret = request_irq(ndev->irq, sh_eth_interrupt,
1931 mdp->cd->irq_flags, ndev->name, ndev);
1932 if (ret) {
1933 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1934 goto out_napi_off;
1935 }
1936
1937 /* Descriptor set */
1938 ret = sh_eth_ring_init(ndev);
1939 if (ret)
1940 goto out_free_irq;
1941
1942 /* device init */
1943 ret = sh_eth_dev_init(ndev, true);
1944 if (ret)
1945 goto out_free_irq;
1946
1947 /* PHY control start*/
1948 ret = sh_eth_phy_start(ndev);
1949 if (ret)
1950 goto out_free_irq;
1951
1952 return ret;
1953
1954 out_free_irq:
1955 free_irq(ndev->irq, ndev);
1956 out_napi_off:
1957 napi_disable(&mdp->napi);
1958 pm_runtime_put_sync(&mdp->pdev->dev);
1959 return ret;
1960 }
1961
1962 /* Timeout function */
1963 static void sh_eth_tx_timeout(struct net_device *ndev)
1964 {
1965 struct sh_eth_private *mdp = netdev_priv(ndev);
1966 struct sh_eth_rxdesc *rxdesc;
1967 int i;
1968
1969 netif_stop_queue(ndev);
1970
1971 if (netif_msg_timer(mdp))
1972 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1973 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1974
1975 /* tx_errors count up */
1976 ndev->stats.tx_errors++;
1977
1978 /* Free all the skbuffs in the Rx queue. */
1979 for (i = 0; i < mdp->num_rx_ring; i++) {
1980 rxdesc = &mdp->rx_ring[i];
1981 rxdesc->status = 0;
1982 rxdesc->addr = 0xBADF00D0;
1983 if (mdp->rx_skbuff[i])
1984 dev_kfree_skb(mdp->rx_skbuff[i]);
1985 mdp->rx_skbuff[i] = NULL;
1986 }
1987 for (i = 0; i < mdp->num_tx_ring; i++) {
1988 if (mdp->tx_skbuff[i])
1989 dev_kfree_skb(mdp->tx_skbuff[i]);
1990 mdp->tx_skbuff[i] = NULL;
1991 }
1992
1993 /* device init */
1994 sh_eth_dev_init(ndev, true);
1995 }
1996
1997 /* Packet transmit function */
1998 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1999 {
2000 struct sh_eth_private *mdp = netdev_priv(ndev);
2001 struct sh_eth_txdesc *txdesc;
2002 u32 entry;
2003 unsigned long flags;
2004
2005 spin_lock_irqsave(&mdp->lock, flags);
2006 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2007 if (!sh_eth_txfree(ndev)) {
2008 if (netif_msg_tx_queued(mdp))
2009 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2010 netif_stop_queue(ndev);
2011 spin_unlock_irqrestore(&mdp->lock, flags);
2012 return NETDEV_TX_BUSY;
2013 }
2014 }
2015 spin_unlock_irqrestore(&mdp->lock, flags);
2016
2017 entry = mdp->cur_tx % mdp->num_tx_ring;
2018 mdp->tx_skbuff[entry] = skb;
2019 txdesc = &mdp->tx_ring[entry];
2020 /* soft swap. */
2021 if (!mdp->cd->hw_swap)
2022 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2023 skb->len + 2);
2024 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2025 DMA_TO_DEVICE);
2026 if (skb->len < ETHERSMALL)
2027 txdesc->buffer_length = ETHERSMALL;
2028 else
2029 txdesc->buffer_length = skb->len;
2030
2031 if (entry >= mdp->num_tx_ring - 1)
2032 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2033 else
2034 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2035
2036 mdp->cur_tx++;
2037
2038 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2039 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2040
2041 return NETDEV_TX_OK;
2042 }
2043
2044 /* device close function */
2045 static int sh_eth_close(struct net_device *ndev)
2046 {
2047 struct sh_eth_private *mdp = netdev_priv(ndev);
2048
2049 netif_stop_queue(ndev);
2050
2051 /* Disable interrupts by clearing the interrupt mask. */
2052 sh_eth_write(ndev, 0x0000, EESIPR);
2053
2054 /* Stop the chip's Tx and Rx processes. */
2055 sh_eth_write(ndev, 0, EDTRR);
2056 sh_eth_write(ndev, 0, EDRRR);
2057
2058 /* PHY Disconnect */
2059 if (mdp->phydev) {
2060 phy_stop(mdp->phydev);
2061 phy_disconnect(mdp->phydev);
2062 }
2063
2064 free_irq(ndev->irq, ndev);
2065
2066 napi_disable(&mdp->napi);
2067
2068 /* Free all the skbuffs in the Rx queue. */
2069 sh_eth_ring_free(ndev);
2070
2071 /* free DMA buffer */
2072 sh_eth_free_dma_buffer(mdp);
2073
2074 pm_runtime_put_sync(&mdp->pdev->dev);
2075
2076 return 0;
2077 }
2078
2079 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2080 {
2081 struct sh_eth_private *mdp = netdev_priv(ndev);
2082
2083 pm_runtime_get_sync(&mdp->pdev->dev);
2084
2085 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2086 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2087 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2088 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2089 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2090 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2091 if (sh_eth_is_gether(mdp)) {
2092 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2093 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2094 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2095 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2096 } else {
2097 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2098 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2099 }
2100 pm_runtime_put_sync(&mdp->pdev->dev);
2101
2102 return &ndev->stats;
2103 }
2104
2105 /* ioctl to device function */
2106 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2107 int cmd)
2108 {
2109 struct sh_eth_private *mdp = netdev_priv(ndev);
2110 struct phy_device *phydev = mdp->phydev;
2111
2112 if (!netif_running(ndev))
2113 return -EINVAL;
2114
2115 if (!phydev)
2116 return -ENODEV;
2117
2118 return phy_mii_ioctl(phydev, rq, cmd);
2119 }
2120
2121 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2122 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2123 int entry)
2124 {
2125 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2126 }
2127
2128 static u32 sh_eth_tsu_get_post_mask(int entry)
2129 {
2130 return 0x0f << (28 - ((entry % 8) * 4));
2131 }
2132
2133 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2134 {
2135 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2136 }
2137
2138 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2139 int entry)
2140 {
2141 struct sh_eth_private *mdp = netdev_priv(ndev);
2142 u32 tmp;
2143 void *reg_offset;
2144
2145 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2146 tmp = ioread32(reg_offset);
2147 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2148 }
2149
2150 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2151 int entry)
2152 {
2153 struct sh_eth_private *mdp = netdev_priv(ndev);
2154 u32 post_mask, ref_mask, tmp;
2155 void *reg_offset;
2156
2157 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2158 post_mask = sh_eth_tsu_get_post_mask(entry);
2159 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2160
2161 tmp = ioread32(reg_offset);
2162 iowrite32(tmp & ~post_mask, reg_offset);
2163
2164 /* If other port enables, the function returns "true" */
2165 return tmp & ref_mask;
2166 }
2167
2168 static int sh_eth_tsu_busy(struct net_device *ndev)
2169 {
2170 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2171 struct sh_eth_private *mdp = netdev_priv(ndev);
2172
2173 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2174 udelay(10);
2175 timeout--;
2176 if (timeout <= 0) {
2177 dev_err(&ndev->dev, "%s: timeout\n", __func__);
2178 return -ETIMEDOUT;
2179 }
2180 }
2181
2182 return 0;
2183 }
2184
2185 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2186 const u8 *addr)
2187 {
2188 u32 val;
2189
2190 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2191 iowrite32(val, reg);
2192 if (sh_eth_tsu_busy(ndev) < 0)
2193 return -EBUSY;
2194
2195 val = addr[4] << 8 | addr[5];
2196 iowrite32(val, reg + 4);
2197 if (sh_eth_tsu_busy(ndev) < 0)
2198 return -EBUSY;
2199
2200 return 0;
2201 }
2202
2203 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2204 {
2205 u32 val;
2206
2207 val = ioread32(reg);
2208 addr[0] = (val >> 24) & 0xff;
2209 addr[1] = (val >> 16) & 0xff;
2210 addr[2] = (val >> 8) & 0xff;
2211 addr[3] = val & 0xff;
2212 val = ioread32(reg + 4);
2213 addr[4] = (val >> 8) & 0xff;
2214 addr[5] = val & 0xff;
2215 }
2216
2217
2218 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2219 {
2220 struct sh_eth_private *mdp = netdev_priv(ndev);
2221 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2222 int i;
2223 u8 c_addr[ETH_ALEN];
2224
2225 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2226 sh_eth_tsu_read_entry(reg_offset, c_addr);
2227 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2228 return i;
2229 }
2230
2231 return -ENOENT;
2232 }
2233
2234 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2235 {
2236 u8 blank[ETH_ALEN];
2237 int entry;
2238
2239 memset(blank, 0, sizeof(blank));
2240 entry = sh_eth_tsu_find_entry(ndev, blank);
2241 return (entry < 0) ? -ENOMEM : entry;
2242 }
2243
2244 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2245 int entry)
2246 {
2247 struct sh_eth_private *mdp = netdev_priv(ndev);
2248 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2249 int ret;
2250 u8 blank[ETH_ALEN];
2251
2252 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2253 ~(1 << (31 - entry)), TSU_TEN);
2254
2255 memset(blank, 0, sizeof(blank));
2256 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2257 if (ret < 0)
2258 return ret;
2259 return 0;
2260 }
2261
2262 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2263 {
2264 struct sh_eth_private *mdp = netdev_priv(ndev);
2265 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2266 int i, ret;
2267
2268 if (!mdp->cd->tsu)
2269 return 0;
2270
2271 i = sh_eth_tsu_find_entry(ndev, addr);
2272 if (i < 0) {
2273 /* No entry found, create one */
2274 i = sh_eth_tsu_find_empty(ndev);
2275 if (i < 0)
2276 return -ENOMEM;
2277 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2278 if (ret < 0)
2279 return ret;
2280
2281 /* Enable the entry */
2282 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2283 (1 << (31 - i)), TSU_TEN);
2284 }
2285
2286 /* Entry found or created, enable POST */
2287 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2288
2289 return 0;
2290 }
2291
2292 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2293 {
2294 struct sh_eth_private *mdp = netdev_priv(ndev);
2295 int i, ret;
2296
2297 if (!mdp->cd->tsu)
2298 return 0;
2299
2300 i = sh_eth_tsu_find_entry(ndev, addr);
2301 if (i) {
2302 /* Entry found */
2303 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2304 goto done;
2305
2306 /* Disable the entry if both ports was disabled */
2307 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2308 if (ret < 0)
2309 return ret;
2310 }
2311 done:
2312 return 0;
2313 }
2314
2315 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2316 {
2317 struct sh_eth_private *mdp = netdev_priv(ndev);
2318 int i, ret;
2319
2320 if (unlikely(!mdp->cd->tsu))
2321 return 0;
2322
2323 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2324 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2325 continue;
2326
2327 /* Disable the entry if both ports was disabled */
2328 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2329 if (ret < 0)
2330 return ret;
2331 }
2332
2333 return 0;
2334 }
2335
2336 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2337 {
2338 struct sh_eth_private *mdp = netdev_priv(ndev);
2339 u8 addr[ETH_ALEN];
2340 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2341 int i;
2342
2343 if (unlikely(!mdp->cd->tsu))
2344 return;
2345
2346 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2347 sh_eth_tsu_read_entry(reg_offset, addr);
2348 if (is_multicast_ether_addr(addr))
2349 sh_eth_tsu_del_entry(ndev, addr);
2350 }
2351 }
2352
2353 /* Multicast reception directions set */
2354 static void sh_eth_set_multicast_list(struct net_device *ndev)
2355 {
2356 struct sh_eth_private *mdp = netdev_priv(ndev);
2357 u32 ecmr_bits;
2358 int mcast_all = 0;
2359 unsigned long flags;
2360
2361 spin_lock_irqsave(&mdp->lock, flags);
2362 /*
2363 * Initial condition is MCT = 1, PRM = 0.
2364 * Depending on ndev->flags, set PRM or clear MCT
2365 */
2366 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2367
2368 if (!(ndev->flags & IFF_MULTICAST)) {
2369 sh_eth_tsu_purge_mcast(ndev);
2370 mcast_all = 1;
2371 }
2372 if (ndev->flags & IFF_ALLMULTI) {
2373 sh_eth_tsu_purge_mcast(ndev);
2374 ecmr_bits &= ~ECMR_MCT;
2375 mcast_all = 1;
2376 }
2377
2378 if (ndev->flags & IFF_PROMISC) {
2379 sh_eth_tsu_purge_all(ndev);
2380 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2381 } else if (mdp->cd->tsu) {
2382 struct netdev_hw_addr *ha;
2383 netdev_for_each_mc_addr(ha, ndev) {
2384 if (mcast_all && is_multicast_ether_addr(ha->addr))
2385 continue;
2386
2387 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2388 if (!mcast_all) {
2389 sh_eth_tsu_purge_mcast(ndev);
2390 ecmr_bits &= ~ECMR_MCT;
2391 mcast_all = 1;
2392 }
2393 }
2394 }
2395 } else {
2396 /* Normal, unicast/broadcast-only mode. */
2397 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2398 }
2399
2400 /* update the ethernet mode */
2401 sh_eth_write(ndev, ecmr_bits, ECMR);
2402
2403 spin_unlock_irqrestore(&mdp->lock, flags);
2404 }
2405
2406 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2407 {
2408 if (!mdp->port)
2409 return TSU_VTAG0;
2410 else
2411 return TSU_VTAG1;
2412 }
2413
2414 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2415 __be16 proto, u16 vid)
2416 {
2417 struct sh_eth_private *mdp = netdev_priv(ndev);
2418 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2419
2420 if (unlikely(!mdp->cd->tsu))
2421 return -EPERM;
2422
2423 /* No filtering if vid = 0 */
2424 if (!vid)
2425 return 0;
2426
2427 mdp->vlan_num_ids++;
2428
2429 /*
2430 * The controller has one VLAN tag HW filter. So, if the filter is
2431 * already enabled, the driver disables it and the filte
2432 */
2433 if (mdp->vlan_num_ids > 1) {
2434 /* disable VLAN filter */
2435 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2436 return 0;
2437 }
2438
2439 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2440 vtag_reg_index);
2441
2442 return 0;
2443 }
2444
2445 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2446 __be16 proto, u16 vid)
2447 {
2448 struct sh_eth_private *mdp = netdev_priv(ndev);
2449 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2450
2451 if (unlikely(!mdp->cd->tsu))
2452 return -EPERM;
2453
2454 /* No filtering if vid = 0 */
2455 if (!vid)
2456 return 0;
2457
2458 mdp->vlan_num_ids--;
2459 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2460
2461 return 0;
2462 }
2463
2464 /* SuperH's TSU register init function */
2465 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2466 {
2467 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2468 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2469 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2470 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2471 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2472 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2473 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2474 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2475 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2476 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2477 if (sh_eth_is_gether(mdp)) {
2478 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2479 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2480 } else {
2481 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2482 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2483 }
2484 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2485 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2486 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2487 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2488 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2489 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2490 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2491 }
2492
2493 /* MDIO bus release function */
2494 static int sh_mdio_release(struct net_device *ndev)
2495 {
2496 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2497
2498 /* unregister mdio bus */
2499 mdiobus_unregister(bus);
2500
2501 /* remove mdio bus info from net_device */
2502 dev_set_drvdata(&ndev->dev, NULL);
2503
2504 /* free bitbang info */
2505 free_mdio_bitbang(bus);
2506
2507 return 0;
2508 }
2509
2510 /* MDIO bus init function */
2511 static int sh_mdio_init(struct net_device *ndev, int id,
2512 struct sh_eth_plat_data *pd)
2513 {
2514 int ret, i;
2515 struct bb_info *bitbang;
2516 struct sh_eth_private *mdp = netdev_priv(ndev);
2517
2518 /* create bit control struct for PHY */
2519 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2520 GFP_KERNEL);
2521 if (!bitbang) {
2522 ret = -ENOMEM;
2523 goto out;
2524 }
2525
2526 /* bitbang init */
2527 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2528 bitbang->set_gate = pd->set_mdio_gate;
2529 bitbang->mdi_msk = PIR_MDI;
2530 bitbang->mdo_msk = PIR_MDO;
2531 bitbang->mmd_msk = PIR_MMD;
2532 bitbang->mdc_msk = PIR_MDC;
2533 bitbang->ctrl.ops = &bb_ops;
2534
2535 /* MII controller setting */
2536 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2537 if (!mdp->mii_bus) {
2538 ret = -ENOMEM;
2539 goto out;
2540 }
2541
2542 /* Hook up MII support for ethtool */
2543 mdp->mii_bus->name = "sh_mii";
2544 mdp->mii_bus->parent = &ndev->dev;
2545 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2546 mdp->pdev->name, id);
2547
2548 /* PHY IRQ */
2549 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2550 sizeof(int) * PHY_MAX_ADDR,
2551 GFP_KERNEL);
2552 if (!mdp->mii_bus->irq) {
2553 ret = -ENOMEM;
2554 goto out_free_bus;
2555 }
2556
2557 for (i = 0; i < PHY_MAX_ADDR; i++)
2558 mdp->mii_bus->irq[i] = PHY_POLL;
2559
2560 /* register mdio bus */
2561 ret = mdiobus_register(mdp->mii_bus);
2562 if (ret)
2563 goto out_free_bus;
2564
2565 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2566
2567 return 0;
2568
2569 out_free_bus:
2570 free_mdio_bitbang(mdp->mii_bus);
2571
2572 out:
2573 return ret;
2574 }
2575
2576 static const u16 *sh_eth_get_register_offset(int register_type)
2577 {
2578 const u16 *reg_offset = NULL;
2579
2580 switch (register_type) {
2581 case SH_ETH_REG_GIGABIT:
2582 reg_offset = sh_eth_offset_gigabit;
2583 break;
2584 case SH_ETH_REG_FAST_RCAR:
2585 reg_offset = sh_eth_offset_fast_rcar;
2586 break;
2587 case SH_ETH_REG_FAST_SH4:
2588 reg_offset = sh_eth_offset_fast_sh4;
2589 break;
2590 case SH_ETH_REG_FAST_SH3_SH2:
2591 reg_offset = sh_eth_offset_fast_sh3_sh2;
2592 break;
2593 default:
2594 pr_err("Unknown register type (%d)\n", register_type);
2595 break;
2596 }
2597
2598 return reg_offset;
2599 }
2600
2601 static const struct net_device_ops sh_eth_netdev_ops = {
2602 .ndo_open = sh_eth_open,
2603 .ndo_stop = sh_eth_close,
2604 .ndo_start_xmit = sh_eth_start_xmit,
2605 .ndo_get_stats = sh_eth_get_stats,
2606 .ndo_tx_timeout = sh_eth_tx_timeout,
2607 .ndo_do_ioctl = sh_eth_do_ioctl,
2608 .ndo_validate_addr = eth_validate_addr,
2609 .ndo_set_mac_address = eth_mac_addr,
2610 .ndo_change_mtu = eth_change_mtu,
2611 };
2612
2613 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2614 .ndo_open = sh_eth_open,
2615 .ndo_stop = sh_eth_close,
2616 .ndo_start_xmit = sh_eth_start_xmit,
2617 .ndo_get_stats = sh_eth_get_stats,
2618 .ndo_set_rx_mode = sh_eth_set_multicast_list,
2619 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2620 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2621 .ndo_tx_timeout = sh_eth_tx_timeout,
2622 .ndo_do_ioctl = sh_eth_do_ioctl,
2623 .ndo_validate_addr = eth_validate_addr,
2624 .ndo_set_mac_address = eth_mac_addr,
2625 .ndo_change_mtu = eth_change_mtu,
2626 };
2627
2628 static int sh_eth_drv_probe(struct platform_device *pdev)
2629 {
2630 int ret, devno = 0;
2631 struct resource *res;
2632 struct net_device *ndev = NULL;
2633 struct sh_eth_private *mdp = NULL;
2634 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2635 const struct platform_device_id *id = platform_get_device_id(pdev);
2636
2637 /* get base addr */
2638 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2639 if (unlikely(res == NULL)) {
2640 dev_err(&pdev->dev, "invalid resource\n");
2641 ret = -EINVAL;
2642 goto out;
2643 }
2644
2645 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2646 if (!ndev) {
2647 ret = -ENOMEM;
2648 goto out;
2649 }
2650
2651 /* The sh Ether-specific entries in the device structure. */
2652 ndev->base_addr = res->start;
2653 devno = pdev->id;
2654 if (devno < 0)
2655 devno = 0;
2656
2657 ndev->dma = -1;
2658 ret = platform_get_irq(pdev, 0);
2659 if (ret < 0) {
2660 ret = -ENODEV;
2661 goto out_release;
2662 }
2663 ndev->irq = ret;
2664
2665 SET_NETDEV_DEV(ndev, &pdev->dev);
2666
2667 mdp = netdev_priv(ndev);
2668 mdp->num_tx_ring = TX_RING_SIZE;
2669 mdp->num_rx_ring = RX_RING_SIZE;
2670 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2671 if (IS_ERR(mdp->addr)) {
2672 ret = PTR_ERR(mdp->addr);
2673 goto out_release;
2674 }
2675
2676 spin_lock_init(&mdp->lock);
2677 mdp->pdev = pdev;
2678 pm_runtime_enable(&pdev->dev);
2679 pm_runtime_resume(&pdev->dev);
2680
2681 /* get PHY ID */
2682 mdp->phy_id = pd->phy;
2683 mdp->phy_interface = pd->phy_interface;
2684 /* EDMAC endian */
2685 mdp->edmac_endian = pd->edmac_endian;
2686 mdp->no_ether_link = pd->no_ether_link;
2687 mdp->ether_link_active_low = pd->ether_link_active_low;
2688
2689 /* set cpu data */
2690 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2691 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2692 sh_eth_set_default_cpu_data(mdp->cd);
2693
2694 /* set function */
2695 if (mdp->cd->tsu)
2696 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2697 else
2698 ndev->netdev_ops = &sh_eth_netdev_ops;
2699 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2700 ndev->watchdog_timeo = TX_TIMEOUT;
2701
2702 /* debug message level */
2703 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2704
2705 /* read and set MAC address */
2706 read_mac_address(ndev, pd->mac_addr);
2707 if (!is_valid_ether_addr(ndev->dev_addr)) {
2708 dev_warn(&pdev->dev,
2709 "no valid MAC address supplied, using a random one.\n");
2710 eth_hw_addr_random(ndev);
2711 }
2712
2713 /* ioremap the TSU registers */
2714 if (mdp->cd->tsu) {
2715 struct resource *rtsu;
2716 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2717 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2718 if (IS_ERR(mdp->tsu_addr)) {
2719 ret = PTR_ERR(mdp->tsu_addr);
2720 goto out_release;
2721 }
2722 mdp->port = devno % 2;
2723 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2724 }
2725
2726 /* initialize first or needed device */
2727 if (!devno || pd->needs_init) {
2728 if (mdp->cd->chip_reset)
2729 mdp->cd->chip_reset(ndev);
2730
2731 if (mdp->cd->tsu) {
2732 /* TSU init (Init only)*/
2733 sh_eth_tsu_init(mdp);
2734 }
2735 }
2736
2737 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2738
2739 /* network device register */
2740 ret = register_netdev(ndev);
2741 if (ret)
2742 goto out_napi_del;
2743
2744 /* mdio bus init */
2745 ret = sh_mdio_init(ndev, pdev->id, pd);
2746 if (ret)
2747 goto out_unregister;
2748
2749 /* print device information */
2750 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2751 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2752
2753 platform_set_drvdata(pdev, ndev);
2754
2755 return ret;
2756
2757 out_unregister:
2758 unregister_netdev(ndev);
2759
2760 out_napi_del:
2761 netif_napi_del(&mdp->napi);
2762
2763 out_release:
2764 /* net_dev free */
2765 if (ndev)
2766 free_netdev(ndev);
2767
2768 out:
2769 return ret;
2770 }
2771
2772 static int sh_eth_drv_remove(struct platform_device *pdev)
2773 {
2774 struct net_device *ndev = platform_get_drvdata(pdev);
2775 struct sh_eth_private *mdp = netdev_priv(ndev);
2776
2777 sh_mdio_release(ndev);
2778 unregister_netdev(ndev);
2779 netif_napi_del(&mdp->napi);
2780 pm_runtime_disable(&pdev->dev);
2781 free_netdev(ndev);
2782
2783 return 0;
2784 }
2785
2786 #ifdef CONFIG_PM
2787 static int sh_eth_runtime_nop(struct device *dev)
2788 {
2789 /*
2790 * Runtime PM callback shared between ->runtime_suspend()
2791 * and ->runtime_resume(). Simply returns success.
2792 *
2793 * This driver re-initializes all registers after
2794 * pm_runtime_get_sync() anyway so there is no need
2795 * to save and restore registers here.
2796 */
2797 return 0;
2798 }
2799
2800 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2801 .runtime_suspend = sh_eth_runtime_nop,
2802 .runtime_resume = sh_eth_runtime_nop,
2803 };
2804 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2805 #else
2806 #define SH_ETH_PM_OPS NULL
2807 #endif
2808
2809 static struct platform_device_id sh_eth_id_table[] = {
2810 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2811 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2812 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2813 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2814 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2815 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2816 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2817 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2818 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2819 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data },
2820 { }
2821 };
2822 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2823
2824 static struct platform_driver sh_eth_driver = {
2825 .probe = sh_eth_drv_probe,
2826 .remove = sh_eth_drv_remove,
2827 .id_table = sh_eth_id_table,
2828 .driver = {
2829 .name = CARDNAME,
2830 .pm = SH_ETH_PM_OPS,
2831 },
2832 };
2833
2834 module_platform_driver(sh_eth_driver);
2835
2836 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2837 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2838 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support