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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / init.c
blobc9887cb60650857f787f0b4ad7934dab2d75da29
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
25
26 #include "ath9k.h"
27
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
30 struct ath_hw *ah;
31 };
32
33 static char *dev_info = "ath9k";
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
43
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
47
48 int led_blink;
49 module_param_named(blink, led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
51
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
55
56 static int ath9k_bt_ant_diversity;
57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
59
60 static int ath9k_ps_enable;
61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
63
64 bool is_ath9k_unloaded;
65 /* We use the hw_value as an index into our private channel structure */
66
67 #define CHAN2G(_freq, _idx) { \
68 .band = IEEE80211_BAND_2GHZ, \
69 .center_freq = (_freq), \
70 .hw_value = (_idx), \
71 .max_power = 20, \
72 }
73
74 #define CHAN5G(_freq, _idx) { \
75 .band = IEEE80211_BAND_5GHZ, \
76 .center_freq = (_freq), \
77 .hw_value = (_idx), \
78 .max_power = 20, \
79 }
80
81 /* Some 2 GHz radios are actually tunable on 2312-2732
82 * on 5 MHz steps, we support the channels which we know
83 * we have calibration data for all cards though to make
84 * this static */
85 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
86 CHAN2G(2412, 0), /* Channel 1 */
87 CHAN2G(2417, 1), /* Channel 2 */
88 CHAN2G(2422, 2), /* Channel 3 */
89 CHAN2G(2427, 3), /* Channel 4 */
90 CHAN2G(2432, 4), /* Channel 5 */
91 CHAN2G(2437, 5), /* Channel 6 */
92 CHAN2G(2442, 6), /* Channel 7 */
93 CHAN2G(2447, 7), /* Channel 8 */
94 CHAN2G(2452, 8), /* Channel 9 */
95 CHAN2G(2457, 9), /* Channel 10 */
96 CHAN2G(2462, 10), /* Channel 11 */
97 CHAN2G(2467, 11), /* Channel 12 */
98 CHAN2G(2472, 12), /* Channel 13 */
99 CHAN2G(2484, 13), /* Channel 14 */
100 };
101
102 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
103 * on 5 MHz steps, we support the channels which we know
104 * we have calibration data for all cards though to make
105 * this static */
106 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
107 /* _We_ call this UNII 1 */
108 CHAN5G(5180, 14), /* Channel 36 */
109 CHAN5G(5200, 15), /* Channel 40 */
110 CHAN5G(5220, 16), /* Channel 44 */
111 CHAN5G(5240, 17), /* Channel 48 */
112 /* _We_ call this UNII 2 */
113 CHAN5G(5260, 18), /* Channel 52 */
114 CHAN5G(5280, 19), /* Channel 56 */
115 CHAN5G(5300, 20), /* Channel 60 */
116 CHAN5G(5320, 21), /* Channel 64 */
117 /* _We_ call this "Middle band" */
118 CHAN5G(5500, 22), /* Channel 100 */
119 CHAN5G(5520, 23), /* Channel 104 */
120 CHAN5G(5540, 24), /* Channel 108 */
121 CHAN5G(5560, 25), /* Channel 112 */
122 CHAN5G(5580, 26), /* Channel 116 */
123 CHAN5G(5600, 27), /* Channel 120 */
124 CHAN5G(5620, 28), /* Channel 124 */
125 CHAN5G(5640, 29), /* Channel 128 */
126 CHAN5G(5660, 30), /* Channel 132 */
127 CHAN5G(5680, 31), /* Channel 136 */
128 CHAN5G(5700, 32), /* Channel 140 */
129 /* _We_ call this UNII 3 */
130 CHAN5G(5745, 33), /* Channel 149 */
131 CHAN5G(5765, 34), /* Channel 153 */
132 CHAN5G(5785, 35), /* Channel 157 */
133 CHAN5G(5805, 36), /* Channel 161 */
134 CHAN5G(5825, 37), /* Channel 165 */
135 };
136
137 /* Atheros hardware rate code addition for short premble */
138 #define SHPCHECK(__hw_rate, __flags) \
139 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
140
141 #define RATE(_bitrate, _hw_rate, _flags) { \
142 .bitrate = (_bitrate), \
143 .flags = (_flags), \
144 .hw_value = (_hw_rate), \
145 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
146 }
147
148 static struct ieee80211_rate ath9k_legacy_rates[] = {
149 RATE(10, 0x1b, 0),
150 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
151 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
152 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
153 RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ |
154 IEEE80211_RATE_SUPPORTS_10MHZ)),
155 RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ |
156 IEEE80211_RATE_SUPPORTS_10MHZ)),
157 RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ |
158 IEEE80211_RATE_SUPPORTS_10MHZ)),
159 RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ |
160 IEEE80211_RATE_SUPPORTS_10MHZ)),
161 RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ |
162 IEEE80211_RATE_SUPPORTS_10MHZ)),
163 RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ |
164 IEEE80211_RATE_SUPPORTS_10MHZ)),
165 RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ |
166 IEEE80211_RATE_SUPPORTS_10MHZ)),
167 RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ |
168 IEEE80211_RATE_SUPPORTS_10MHZ)),
169 };
170
171 #ifdef CONFIG_MAC80211_LEDS
172 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
173 { .throughput = 0 * 1024, .blink_time = 334 },
174 { .throughput = 1 * 1024, .blink_time = 260 },
175 { .throughput = 5 * 1024, .blink_time = 220 },
176 { .throughput = 10 * 1024, .blink_time = 190 },
177 { .throughput = 20 * 1024, .blink_time = 170 },
178 { .throughput = 50 * 1024, .blink_time = 150 },
179 { .throughput = 70 * 1024, .blink_time = 130 },
180 { .throughput = 100 * 1024, .blink_time = 110 },
181 { .throughput = 200 * 1024, .blink_time = 80 },
182 { .throughput = 300 * 1024, .blink_time = 50 },
183 };
184 #endif
185
186 static void ath9k_deinit_softc(struct ath_softc *sc);
187
188 /*
189 * Read and write, they both share the same lock. We do this to serialize
190 * reads and writes on Atheros 802.11n PCI devices only. This is required
191 * as the FIFO on these devices can only accept sanely 2 requests.
192 */
193
194 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
195 {
196 struct ath_hw *ah = (struct ath_hw *) hw_priv;
197 struct ath_common *common = ath9k_hw_common(ah);
198 struct ath_softc *sc = (struct ath_softc *) common->priv;
199
200 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
201 unsigned long flags;
202 spin_lock_irqsave(&sc->sc_serial_rw, flags);
203 iowrite32(val, sc->mem + reg_offset);
204 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
205 } else
206 iowrite32(val, sc->mem + reg_offset);
207 }
208
209 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
210 {
211 struct ath_hw *ah = (struct ath_hw *) hw_priv;
212 struct ath_common *common = ath9k_hw_common(ah);
213 struct ath_softc *sc = (struct ath_softc *) common->priv;
214 u32 val;
215
216 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
217 unsigned long flags;
218 spin_lock_irqsave(&sc->sc_serial_rw, flags);
219 val = ioread32(sc->mem + reg_offset);
220 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
221 } else
222 val = ioread32(sc->mem + reg_offset);
223 return val;
224 }
225
226 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
227 u32 set, u32 clr)
228 {
229 u32 val;
230
231 val = ioread32(sc->mem + reg_offset);
232 val &= ~clr;
233 val |= set;
234 iowrite32(val, sc->mem + reg_offset);
235
236 return val;
237 }
238
239 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
240 {
241 struct ath_hw *ah = (struct ath_hw *) hw_priv;
242 struct ath_common *common = ath9k_hw_common(ah);
243 struct ath_softc *sc = (struct ath_softc *) common->priv;
244 unsigned long uninitialized_var(flags);
245 u32 val;
246
247 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
248 spin_lock_irqsave(&sc->sc_serial_rw, flags);
249 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
250 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
251 } else
252 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
253
254 return val;
255 }
256
257 /**************************/
258 /* Initialization */
259 /**************************/
260
261 static void setup_ht_cap(struct ath_softc *sc,
262 struct ieee80211_sta_ht_cap *ht_info)
263 {
264 struct ath_hw *ah = sc->sc_ah;
265 struct ath_common *common = ath9k_hw_common(ah);
266 u8 tx_streams, rx_streams;
267 int i, max_streams;
268
269 ht_info->ht_supported = true;
270 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
271 IEEE80211_HT_CAP_SM_PS |
272 IEEE80211_HT_CAP_SGI_40 |
273 IEEE80211_HT_CAP_DSSSCCK40;
274
275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
276 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
277
278 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
279 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
280
281 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
282 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
283
284 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
285 max_streams = 1;
286 else if (AR_SREV_9462(ah))
287 max_streams = 2;
288 else if (AR_SREV_9300_20_OR_LATER(ah))
289 max_streams = 3;
290 else
291 max_streams = 2;
292
293 if (AR_SREV_9280_20_OR_LATER(ah)) {
294 if (max_streams >= 2)
295 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
296 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
297 }
298
299 /* set up supported mcs set */
300 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
301 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
302 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
303
304 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
305 tx_streams, rx_streams);
306
307 if (tx_streams != rx_streams) {
308 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
309 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
310 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
311 }
312
313 for (i = 0; i < rx_streams; i++)
314 ht_info->mcs.rx_mask[i] = 0xff;
315
316 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
317 }
318
319 static void ath9k_reg_notifier(struct wiphy *wiphy,
320 struct regulatory_request *request)
321 {
322 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
323 struct ath_softc *sc = hw->priv;
324 struct ath_hw *ah = sc->sc_ah;
325 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
326
327 ath_reg_notifier_apply(wiphy, request, reg);
328
329 /* Set tx power */
330 if (ah->curchan) {
331 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
332 ath9k_ps_wakeup(sc);
333 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
334 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
335 /* synchronize DFS detector if regulatory domain changed */
336 if (sc->dfs_detector != NULL)
337 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
338 request->dfs_region);
339 ath9k_ps_restore(sc);
340 }
341 }
342
343 /*
344 * This function will allocate both the DMA descriptor structure, and the
345 * buffers it contains. These are used to contain the descriptors used
346 * by the system.
347 */
348 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
349 struct list_head *head, const char *name,
350 int nbuf, int ndesc, bool is_tx)
351 {
352 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
353 u8 *ds;
354 struct ath_buf *bf;
355 int i, bsize, desc_len;
356
357 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
358 name, nbuf, ndesc);
359
360 INIT_LIST_HEAD(head);
361
362 if (is_tx)
363 desc_len = sc->sc_ah->caps.tx_desc_len;
364 else
365 desc_len = sizeof(struct ath_desc);
366
367 /* ath_desc must be a multiple of DWORDs */
368 if ((desc_len % 4) != 0) {
369 ath_err(common, "ath_desc not DWORD aligned\n");
370 BUG_ON((desc_len % 4) != 0);
371 return -ENOMEM;
372 }
373
374 dd->dd_desc_len = desc_len * nbuf * ndesc;
375
376 /*
377 * Need additional DMA memory because we can't use
378 * descriptors that cross the 4K page boundary. Assume
379 * one skipped descriptor per 4K page.
380 */
381 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
382 u32 ndesc_skipped =
383 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
384 u32 dma_len;
385
386 while (ndesc_skipped) {
387 dma_len = ndesc_skipped * desc_len;
388 dd->dd_desc_len += dma_len;
389
390 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
391 }
392 }
393
394 /* allocate descriptors */
395 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
396 &dd->dd_desc_paddr, GFP_KERNEL);
397 if (!dd->dd_desc)
398 return -ENOMEM;
399
400 ds = (u8 *) dd->dd_desc;
401 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
402 name, ds, (u32) dd->dd_desc_len,
403 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
404
405 /* allocate buffers */
406 bsize = sizeof(struct ath_buf) * nbuf;
407 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
408 if (!bf)
409 return -ENOMEM;
410
411 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
412 bf->bf_desc = ds;
413 bf->bf_daddr = DS2PHYS(dd, ds);
414
415 if (!(sc->sc_ah->caps.hw_caps &
416 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
417 /*
418 * Skip descriptor addresses which can cause 4KB
419 * boundary crossing (addr + length) with a 32 dword
420 * descriptor fetch.
421 */
422 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
423 BUG_ON((caddr_t) bf->bf_desc >=
424 ((caddr_t) dd->dd_desc +
425 dd->dd_desc_len));
426
427 ds += (desc_len * ndesc);
428 bf->bf_desc = ds;
429 bf->bf_daddr = DS2PHYS(dd, ds);
430 }
431 }
432 list_add_tail(&bf->list, head);
433 }
434 return 0;
435 }
436
437 static int ath9k_init_queues(struct ath_softc *sc)
438 {
439 int i = 0;
440
441 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
442 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
443
444 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
445 ath_cabq_update(sc);
446
447 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
448
449 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
450 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
451 sc->tx.txq_map[i]->mac80211_qnum = i;
452 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
453 }
454 return 0;
455 }
456
457 static int ath9k_init_channels_rates(struct ath_softc *sc)
458 {
459 void *channels;
460
461 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
462 ARRAY_SIZE(ath9k_5ghz_chantable) !=
463 ATH9K_NUM_CHANNELS);
464
465 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
466 channels = devm_kzalloc(sc->dev,
467 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
468 if (!channels)
469 return -ENOMEM;
470
471 memcpy(channels, ath9k_2ghz_chantable,
472 sizeof(ath9k_2ghz_chantable));
473 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
474 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
475 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
476 ARRAY_SIZE(ath9k_2ghz_chantable);
477 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
478 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
479 ARRAY_SIZE(ath9k_legacy_rates);
480 }
481
482 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
483 channels = devm_kzalloc(sc->dev,
484 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
485 if (!channels)
486 return -ENOMEM;
487
488 memcpy(channels, ath9k_5ghz_chantable,
489 sizeof(ath9k_5ghz_chantable));
490 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
491 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
492 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
493 ARRAY_SIZE(ath9k_5ghz_chantable);
494 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
495 ath9k_legacy_rates + 4;
496 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
497 ARRAY_SIZE(ath9k_legacy_rates) - 4;
498 }
499 return 0;
500 }
501
502 static void ath9k_init_misc(struct ath_softc *sc)
503 {
504 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
505 int i = 0;
506
507 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
508
509 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
510 sc->config.txpowlimit = ATH_TXPOWER_MAX;
511 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
512 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
513
514 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
515 sc->beacon.bslot[i] = NULL;
516
517 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
518 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
519
520 sc->spec_config.enabled = 0;
521 sc->spec_config.short_repeat = true;
522 sc->spec_config.count = 8;
523 sc->spec_config.endless = false;
524 sc->spec_config.period = 0xFF;
525 sc->spec_config.fft_period = 0xF;
526 }
527
528 static void ath9k_init_platform(struct ath_softc *sc)
529 {
530 struct ath_hw *ah = sc->sc_ah;
531 struct ath9k_hw_capabilities *pCap = &ah->caps;
532 struct ath_common *common = ath9k_hw_common(ah);
533
534 if (common->bus_ops->ath_bus_type != ATH_PCI)
535 return;
536
537 if (sc->driver_data & (ATH9K_PCI_CUS198 |
538 ATH9K_PCI_CUS230)) {
539 ah->config.xlna_gpio = 9;
540 ah->config.xatten_margin_cfg = true;
541 ah->config.alt_mingainidx = true;
542 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
543 sc->ant_comb.low_rssi_thresh = 20;
544 sc->ant_comb.fast_div_bias = 3;
545
546 ath_info(common, "Set parameters for %s\n",
547 (sc->driver_data & ATH9K_PCI_CUS198) ?
548 "CUS198" : "CUS230");
549 }
550
551 if (sc->driver_data & ATH9K_PCI_CUS217)
552 ath_info(common, "CUS217 card detected\n");
553
554 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
555 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
556 ath_info(common, "Set BT/WLAN RX diversity capability\n");
557 }
558
559 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
560 ah->config.pcie_waen = 0x0040473b;
561 ath_info(common, "Enable WAR for ASPM D3/L1\n");
562 }
563 }
564
565 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
566 void *ctx)
567 {
568 struct ath9k_eeprom_ctx *ec = ctx;
569
570 if (eeprom_blob)
571 ec->ah->eeprom_blob = eeprom_blob;
572
573 complete(&ec->complete);
574 }
575
576 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
577 {
578 struct ath9k_eeprom_ctx ec;
579 struct ath_hw *ah = ah = sc->sc_ah;
580 int err;
581
582 /* try to load the EEPROM content asynchronously */
583 init_completion(&ec.complete);
584 ec.ah = sc->sc_ah;
585
586 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
587 &ec, ath9k_eeprom_request_cb);
588 if (err < 0) {
589 ath_err(ath9k_hw_common(ah),
590 "EEPROM request failed\n");
591 return err;
592 }
593
594 wait_for_completion(&ec.complete);
595
596 if (!ah->eeprom_blob) {
597 ath_err(ath9k_hw_common(ah),
598 "Unable to load EEPROM file %s\n", name);
599 return -EINVAL;
600 }
601
602 return 0;
603 }
604
605 static void ath9k_eeprom_release(struct ath_softc *sc)
606 {
607 release_firmware(sc->sc_ah->eeprom_blob);
608 }
609
610 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
611 const struct ath_bus_ops *bus_ops)
612 {
613 struct ath9k_platform_data *pdata = sc->dev->platform_data;
614 struct ath_hw *ah = NULL;
615 struct ath9k_hw_capabilities *pCap;
616 struct ath_common *common;
617 int ret = 0, i;
618 int csz = 0;
619
620 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
621 if (!ah)
622 return -ENOMEM;
623
624 ah->dev = sc->dev;
625 ah->hw = sc->hw;
626 ah->hw_version.devid = devid;
627 ah->reg_ops.read = ath9k_ioread32;
628 ah->reg_ops.write = ath9k_iowrite32;
629 ah->reg_ops.rmw = ath9k_reg_rmw;
630 atomic_set(&ah->intr_ref_cnt, -1);
631 sc->sc_ah = ah;
632 pCap = &ah->caps;
633
634 sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET);
635
636 if (!pdata) {
637 ah->ah_flags |= AH_USE_EEPROM;
638 sc->sc_ah->led_pin = -1;
639 } else {
640 sc->sc_ah->gpio_mask = pdata->gpio_mask;
641 sc->sc_ah->gpio_val = pdata->gpio_val;
642 sc->sc_ah->led_pin = pdata->led_pin;
643 ah->is_clk_25mhz = pdata->is_clk_25mhz;
644 ah->get_mac_revision = pdata->get_mac_revision;
645 ah->external_reset = pdata->external_reset;
646 }
647
648 common = ath9k_hw_common(ah);
649 common->ops = &ah->reg_ops;
650 common->bus_ops = bus_ops;
651 common->ah = ah;
652 common->hw = sc->hw;
653 common->priv = sc;
654 common->debug_mask = ath9k_debug;
655 common->btcoex_enabled = ath9k_btcoex_enable == 1;
656 common->disable_ani = false;
657
658 /*
659 * Platform quirks.
660 */
661 ath9k_init_platform(sc);
662
663 /*
664 * Enable WLAN/BT RX Antenna diversity only when:
665 *
666 * - BTCOEX is disabled.
667 * - the user manually requests the feature.
668 * - the HW cap is set using the platform data.
669 */
670 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
671 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
672 common->bt_ant_diversity = 1;
673
674 spin_lock_init(&common->cc_lock);
675
676 spin_lock_init(&sc->sc_serial_rw);
677 spin_lock_init(&sc->sc_pm_lock);
678 mutex_init(&sc->mutex);
679 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
680 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
681 (unsigned long)sc);
682
683 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
684 INIT_WORK(&sc->hw_check_work, ath_hw_check);
685 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
686 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
687 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
688
689 /*
690 * Cache line size is used to size and align various
691 * structures used to communicate with the hardware.
692 */
693 ath_read_cachesize(common, &csz);
694 common->cachelsz = csz << 2; /* convert to bytes */
695
696 if (pdata && pdata->eeprom_name) {
697 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
698 if (ret)
699 return ret;
700 }
701
702 /* Initializes the hardware for all supported chipsets */
703 ret = ath9k_hw_init(ah);
704 if (ret)
705 goto err_hw;
706
707 if (pdata && pdata->macaddr)
708 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
709
710 ret = ath9k_init_queues(sc);
711 if (ret)
712 goto err_queues;
713
714 ret = ath9k_init_btcoex(sc);
715 if (ret)
716 goto err_btcoex;
717
718 ret = ath9k_init_channels_rates(sc);
719 if (ret)
720 goto err_btcoex;
721
722 ath9k_cmn_init_crypto(sc->sc_ah);
723 ath9k_init_misc(sc);
724 ath_fill_led_pin(sc);
725
726 if (common->bus_ops->aspm_init)
727 common->bus_ops->aspm_init(common);
728
729 return 0;
730
731 err_btcoex:
732 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
733 if (ATH_TXQ_SETUP(sc, i))
734 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
735 err_queues:
736 ath9k_hw_deinit(ah);
737 err_hw:
738 ath9k_eeprom_release(sc);
739 return ret;
740 }
741
742 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
743 {
744 struct ieee80211_supported_band *sband;
745 struct ieee80211_channel *chan;
746 struct ath_hw *ah = sc->sc_ah;
747 struct cfg80211_chan_def chandef;
748 int i;
749
750 sband = &sc->sbands[band];
751 for (i = 0; i < sband->n_channels; i++) {
752 chan = &sband->channels[i];
753 ah->curchan = &ah->channels[chan->hw_value];
754 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
755 ath9k_cmn_update_ichannel(ah->curchan, &chandef);
756 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
757 }
758 }
759
760 static void ath9k_init_txpower_limits(struct ath_softc *sc)
761 {
762 struct ath_hw *ah = sc->sc_ah;
763 struct ath9k_channel *curchan = ah->curchan;
764
765 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
766 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
767 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
768 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
769
770 ah->curchan = curchan;
771 }
772
773 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
774 {
775 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
776 return;
777
778 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
779 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
780 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
781 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
782 }
783
784 static const struct ieee80211_iface_limit if_limits[] = {
785 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
786 BIT(NL80211_IFTYPE_P2P_CLIENT) |
787 BIT(NL80211_IFTYPE_WDS) },
788 { .max = 8, .types =
789 #ifdef CONFIG_MAC80211_MESH
790 BIT(NL80211_IFTYPE_MESH_POINT) |
791 #endif
792 BIT(NL80211_IFTYPE_AP) |
793 BIT(NL80211_IFTYPE_P2P_GO) },
794 };
795
796
797 static const struct ieee80211_iface_limit if_dfs_limits[] = {
798 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) },
799 };
800
801 static const struct ieee80211_iface_combination if_comb[] = {
802 {
803 .limits = if_limits,
804 .n_limits = ARRAY_SIZE(if_limits),
805 .max_interfaces = 2048,
806 .num_different_channels = 1,
807 .beacon_int_infra_match = true,
808 },
809 {
810 .limits = if_dfs_limits,
811 .n_limits = ARRAY_SIZE(if_dfs_limits),
812 .max_interfaces = 1,
813 .num_different_channels = 1,
814 .beacon_int_infra_match = true,
815 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
816 BIT(NL80211_CHAN_HT20),
817 }
818 };
819
820 #ifdef CONFIG_PM
821 static const struct wiphy_wowlan_support ath9k_wowlan_support = {
822 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
823 .n_patterns = MAX_NUM_USER_PATTERN,
824 .pattern_min_len = 1,
825 .pattern_max_len = MAX_PATTERN_SIZE,
826 };
827 #endif
828
829 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
830 {
831 struct ath_hw *ah = sc->sc_ah;
832 struct ath_common *common = ath9k_hw_common(ah);
833
834 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
835 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
836 IEEE80211_HW_SIGNAL_DBM |
837 IEEE80211_HW_PS_NULLFUNC_STACK |
838 IEEE80211_HW_SPECTRUM_MGMT |
839 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
840 IEEE80211_HW_SUPPORTS_RC_TABLE |
841 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
842
843 if (ath9k_ps_enable)
844 hw->flags |= IEEE80211_HW_SUPPORTS_PS;
845
846 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
847 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
848
849 if (AR_SREV_9280_20_OR_LATER(ah))
850 hw->radiotap_mcs_details |=
851 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
852 }
853
854 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
855 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
856
857 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
858
859 hw->wiphy->interface_modes =
860 BIT(NL80211_IFTYPE_P2P_GO) |
861 BIT(NL80211_IFTYPE_P2P_CLIENT) |
862 BIT(NL80211_IFTYPE_AP) |
863 BIT(NL80211_IFTYPE_WDS) |
864 BIT(NL80211_IFTYPE_STATION) |
865 BIT(NL80211_IFTYPE_ADHOC) |
866 BIT(NL80211_IFTYPE_MESH_POINT);
867
868 hw->wiphy->iface_combinations = if_comb;
869 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
870
871 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
872
873 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
874 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
875 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
876 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
877 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
878
879 #ifdef CONFIG_PM_SLEEP
880 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
881 (sc->driver_data & ATH9K_PCI_WOW) &&
882 device_can_wakeup(sc->dev))
883 hw->wiphy->wowlan = &ath9k_wowlan_support;
884
885 atomic_set(&sc->wow_sleep_proc_intr, -1);
886 atomic_set(&sc->wow_got_bmiss_intr, -1);
887 #endif
888
889 hw->queues = 4;
890 hw->max_rates = 4;
891 hw->channel_change_time = 5000;
892 hw->max_listen_interval = 1;
893 hw->max_rate_tries = 10;
894 hw->sta_data_size = sizeof(struct ath_node);
895 hw->vif_data_size = sizeof(struct ath_vif);
896
897 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
898 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
899
900 /* single chain devices with rx diversity */
901 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
902 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
903
904 sc->ant_rx = hw->wiphy->available_antennas_rx;
905 sc->ant_tx = hw->wiphy->available_antennas_tx;
906
907 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
908 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
909 &sc->sbands[IEEE80211_BAND_2GHZ];
910 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
911 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
912 &sc->sbands[IEEE80211_BAND_5GHZ];
913
914 ath9k_reload_chainmask_settings(sc);
915
916 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
917 }
918
919 int ath9k_init_device(u16 devid, struct ath_softc *sc,
920 const struct ath_bus_ops *bus_ops)
921 {
922 struct ieee80211_hw *hw = sc->hw;
923 struct ath_common *common;
924 struct ath_hw *ah;
925 int error = 0;
926 struct ath_regulatory *reg;
927
928 /* Bring up device */
929 error = ath9k_init_softc(devid, sc, bus_ops);
930 if (error)
931 return error;
932
933 ah = sc->sc_ah;
934 common = ath9k_hw_common(ah);
935 ath9k_set_hw_capab(sc, hw);
936
937 /* Initialize regulatory */
938 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
939 ath9k_reg_notifier);
940 if (error)
941 goto deinit;
942
943 reg = &common->regulatory;
944
945 /* Setup TX DMA */
946 error = ath_tx_init(sc, ATH_TXBUF);
947 if (error != 0)
948 goto deinit;
949
950 /* Setup RX DMA */
951 error = ath_rx_init(sc, ATH_RXBUF);
952 if (error != 0)
953 goto deinit;
954
955 ath9k_init_txpower_limits(sc);
956
957 #ifdef CONFIG_MAC80211_LEDS
958 /* must be initialized before ieee80211_register_hw */
959 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
960 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
961 ARRAY_SIZE(ath9k_tpt_blink));
962 #endif
963
964 /* Register with mac80211 */
965 error = ieee80211_register_hw(hw);
966 if (error)
967 goto rx_cleanup;
968
969 error = ath9k_init_debug(ah);
970 if (error) {
971 ath_err(common, "Unable to create debugfs files\n");
972 goto unregister;
973 }
974
975 /* Handle world regulatory */
976 if (!ath_is_world_regd(reg)) {
977 error = regulatory_hint(hw->wiphy, reg->alpha2);
978 if (error)
979 goto debug_cleanup;
980 }
981
982 ath_init_leds(sc);
983 ath_start_rfkill_poll(sc);
984
985 return 0;
986
987 debug_cleanup:
988 ath9k_deinit_debug(sc);
989 unregister:
990 ieee80211_unregister_hw(hw);
991 rx_cleanup:
992 ath_rx_cleanup(sc);
993 deinit:
994 ath9k_deinit_softc(sc);
995 return error;
996 }
997
998 /*****************************/
999 /* De-Initialization */
1000 /*****************************/
1001
1002 static void ath9k_deinit_softc(struct ath_softc *sc)
1003 {
1004 int i = 0;
1005
1006 ath9k_deinit_btcoex(sc);
1007
1008 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1009 if (ATH_TXQ_SETUP(sc, i))
1010 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1011
1012 ath9k_hw_deinit(sc->sc_ah);
1013 if (sc->dfs_detector != NULL)
1014 sc->dfs_detector->exit(sc->dfs_detector);
1015
1016 ath9k_eeprom_release(sc);
1017 }
1018
1019 void ath9k_deinit_device(struct ath_softc *sc)
1020 {
1021 struct ieee80211_hw *hw = sc->hw;
1022
1023 ath9k_ps_wakeup(sc);
1024
1025 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1026 ath_deinit_leds(sc);
1027
1028 ath9k_ps_restore(sc);
1029
1030 ath9k_deinit_debug(sc);
1031 ieee80211_unregister_hw(hw);
1032 ath_rx_cleanup(sc);
1033 ath9k_deinit_softc(sc);
1034 }
1035
1036 /************************/
1037 /* Module Hooks */
1038 /************************/
1039
1040 static int __init ath9k_init(void)
1041 {
1042 int error;
1043
1044 /* Register rate control algorithm */
1045 error = ath_rate_control_register();
1046 if (error != 0) {
1047 pr_err("Unable to register rate control algorithm: %d\n",
1048 error);
1049 goto err_out;
1050 }
1051
1052 error = ath_pci_init();
1053 if (error < 0) {
1054 pr_err("No PCI devices found, driver not installed\n");
1055 error = -ENODEV;
1056 goto err_rate_unregister;
1057 }
1058
1059 error = ath_ahb_init();
1060 if (error < 0) {
1061 error = -ENODEV;
1062 goto err_pci_exit;
1063 }
1064
1065 return 0;
1066
1067 err_pci_exit:
1068 ath_pci_exit();
1069
1070 err_rate_unregister:
1071 ath_rate_control_unregister();
1072 err_out:
1073 return error;
1074 }
1075 module_init(ath9k_init);
1076
1077 static void __exit ath9k_exit(void)
1078 {
1079 is_ath9k_unloaded = true;
1080 ath_ahb_exit();
1081 ath_pci_exit();
1082 ath_rate_control_unregister();
1083 pr_info("%s: Driver unloaded\n", dev_info);
1084 }
1085 module_exit(ath9k_exit);
Linux with added FPC-III support