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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobd92c6ff461dc617563ef71411d0daeba14316d95
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70
71 enum {
72 MCS_HT20,
73 MCS_HT20_SGI,
74 MCS_HT40,
75 MCS_HT40_SGI,
76 };
77
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
81
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
84 {
85 spin_lock_bh(&txq->axq_lock);
86 }
87
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
90 {
91 spin_unlock_bh(&txq->axq_lock);
92 }
93
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
96 {
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106 }
107
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 {
110 struct ath_atx_ac *ac = tid->ac;
111
112 if (tid->paused)
113 return;
114
115 if (tid->sched)
116 return;
117
118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
120
121 if (ac->sched)
122 return;
123
124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126 }
127
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
129 {
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
134 }
135
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137 {
138 if (!tid->an->sta)
139 return;
140
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143 }
144
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 struct ath_buf *bf)
147 {
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
150 }
151
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
153 struct sk_buff *skb)
154 {
155 int q;
156
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
160
161 if (txq != sc->tx.txq_map[q])
162 return;
163
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
166
167 if (txq->stopped &&
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
171 }
172 }
173
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
176 {
177 struct ieee80211_hdr *hdr;
178 u8 tidno = 0;
179
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
183
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
186 }
187
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189 {
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
191 }
192
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 {
195 struct sk_buff *skb;
196
197 skb = __skb_dequeue(&tid->retry_q);
198 if (!skb)
199 skb = __skb_dequeue(&tid->buf_q);
200
201 return skb;
202 }
203
204 /*
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
208 */
209 static void
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211 {
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
215 struct ath_buf *bf;
216 struct ath_frame_info *fi;
217
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
220 bf = fi->bf;
221
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224
225 if (bf)
226 continue;
227
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 if (!bf) {
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
233 continue;
234 }
235 }
236
237 }
238
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
240 {
241 struct ath_txq *txq = tid->ac->txq;
242 struct sk_buff *skb;
243 struct ath_buf *bf;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
248
249 INIT_LIST_HEAD(&bf_head);
250
251 memset(&ts, 0, sizeof(ts));
252
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
255 bf = fi->bf;
256 if (!bf) {
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
259 continue;
260 }
261
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
264 sendbar = true;
265 }
266
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
269 }
270
271 if (sendbar) {
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
275 }
276 }
277
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 int seqno)
280 {
281 int index, cindex;
282
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
285
286 __clear_bit(cindex, tid->tx_buf);
287
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
292 tid->bar_index--;
293 }
294 }
295
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
297 struct ath_buf *bf)
298 {
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
301 int index, cindex;
302
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
306 fi->baw_tracked = 1;
307
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
312 }
313 }
314
315 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
317
318 {
319 struct sk_buff *skb;
320 struct ath_buf *bf;
321 struct list_head bf_head;
322 struct ath_tx_status ts;
323 struct ath_frame_info *fi;
324
325 memset(&ts, 0, sizeof(ts));
326 INIT_LIST_HEAD(&bf_head);
327
328 while ((skb = ath_tid_dequeue(tid))) {
329 fi = get_frame_info(skb);
330 bf = fi->bf;
331
332 if (!bf) {
333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
334 continue;
335 }
336
337 list_add_tail(&bf->list, &bf_head);
338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
339 }
340 }
341
342 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
343 struct sk_buff *skb, int count)
344 {
345 struct ath_frame_info *fi = get_frame_info(skb);
346 struct ath_buf *bf = fi->bf;
347 struct ieee80211_hdr *hdr;
348 int prev = fi->retries;
349
350 TX_STAT_INC(txq->axq_qnum, a_retries);
351 fi->retries += count;
352
353 if (prev > 0)
354 return;
355
356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
360 }
361
362 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
363 {
364 struct ath_buf *bf = NULL;
365
366 spin_lock_bh(&sc->tx.txbuflock);
367
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
369 spin_unlock_bh(&sc->tx.txbuflock);
370 return NULL;
371 }
372
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 list_del(&bf->list);
375
376 spin_unlock_bh(&sc->tx.txbuflock);
377
378 return bf;
379 }
380
381 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382 {
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
386 }
387
388 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
389 {
390 struct ath_buf *tbf;
391
392 tbf = ath_tx_get_buffer(sc);
393 if (WARN_ON(!tbf))
394 return NULL;
395
396 ATH_TXBUF_RESET(tbf);
397
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
401 tbf->bf_state = bf->bf_state;
402 tbf->bf_state.stale = false;
403
404 return tbf;
405 }
406
407 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
408 struct ath_tx_status *ts, int txok,
409 int *nframes, int *nbad)
410 {
411 struct ath_frame_info *fi;
412 u16 seq_st = 0;
413 u32 ba[WME_BA_BMP_SIZE >> 5];
414 int ba_index;
415 int isaggr = 0;
416
417 *nbad = 0;
418 *nframes = 0;
419
420 isaggr = bf_isaggr(bf);
421 if (isaggr) {
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
424 }
425
426 while (bf) {
427 fi = get_frame_info(bf->bf_mpdu);
428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
429
430 (*nframes)++;
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
432 (*nbad)++;
433
434 bf = bf->bf_next;
435 }
436 }
437
438
439 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
441 struct ath_tx_status *ts, int txok)
442 {
443 struct ath_node *an = NULL;
444 struct sk_buff *skb;
445 struct ieee80211_sta *sta;
446 struct ieee80211_hw *hw = sc->hw;
447 struct ieee80211_hdr *hdr;
448 struct ieee80211_tx_info *tx_info;
449 struct ath_atx_tid *tid = NULL;
450 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
451 struct list_head bf_head;
452 struct sk_buff_head bf_pending;
453 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
454 u32 ba[WME_BA_BMP_SIZE >> 5];
455 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
456 bool rc_update = true, isba;
457 struct ieee80211_tx_rate rates[4];
458 struct ath_frame_info *fi;
459 int nframes;
460 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
461 int i, retries;
462 int bar_index = -1;
463
464 skb = bf->bf_mpdu;
465 hdr = (struct ieee80211_hdr *)skb->data;
466
467 tx_info = IEEE80211_SKB_CB(skb);
468
469 memcpy(rates, bf->rates, sizeof(rates));
470
471 retries = ts->ts_longretry + 1;
472 for (i = 0; i < ts->ts_rateindex; i++)
473 retries += rates[i].count;
474
475 rcu_read_lock();
476
477 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
478 if (!sta) {
479 rcu_read_unlock();
480
481 INIT_LIST_HEAD(&bf_head);
482 while (bf) {
483 bf_next = bf->bf_next;
484
485 if (!bf->bf_state.stale || bf_next != NULL)
486 list_move_tail(&bf->list, &bf_head);
487
488 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
489
490 bf = bf_next;
491 }
492 return;
493 }
494
495 an = (struct ath_node *)sta->drv_priv;
496 tid = ath_get_skb_tid(sc, an, skb);
497 seq_first = tid->seq_start;
498 isba = ts->ts_flags & ATH9K_TX_BA;
499
500 /*
501 * The hardware occasionally sends a tx status for the wrong TID.
502 * In this case, the BA status cannot be considered valid and all
503 * subframes need to be retransmitted
504 *
505 * Only BlockAcks have a TID and therefore normal Acks cannot be
506 * checked
507 */
508 if (isba && tid->tidno != ts->tid)
509 txok = false;
510
511 isaggr = bf_isaggr(bf);
512 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
513
514 if (isaggr && txok) {
515 if (ts->ts_flags & ATH9K_TX_BA) {
516 seq_st = ts->ts_seqnum;
517 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
518 } else {
519 /*
520 * AR5416 can become deaf/mute when BA
521 * issue happens. Chip needs to be reset.
522 * But AP code may have sychronization issues
523 * when perform internal reset in this routine.
524 * Only enable reset in STA mode for now.
525 */
526 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
527 needreset = 1;
528 }
529 }
530
531 __skb_queue_head_init(&bf_pending);
532
533 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
534 while (bf) {
535 u16 seqno = bf->bf_state.seqno;
536
537 txfail = txpending = sendbar = 0;
538 bf_next = bf->bf_next;
539
540 skb = bf->bf_mpdu;
541 tx_info = IEEE80211_SKB_CB(skb);
542 fi = get_frame_info(skb);
543
544 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
545 !tid->active) {
546 /*
547 * Outside of the current BlockAck window,
548 * maybe part of a previous session
549 */
550 txfail = 1;
551 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
552 /* transmit completion, subframe is
553 * acked by block ack */
554 acked_cnt++;
555 } else if (!isaggr && txok) {
556 /* transmit completion */
557 acked_cnt++;
558 } else if (flush) {
559 txpending = 1;
560 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
561 if (txok || !an->sleeping)
562 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
563 retries);
564
565 txpending = 1;
566 } else {
567 txfail = 1;
568 txfail_cnt++;
569 bar_index = max_t(int, bar_index,
570 ATH_BA_INDEX(seq_first, seqno));
571 }
572
573 /*
574 * Make sure the last desc is reclaimed if it
575 * not a holding desc.
576 */
577 INIT_LIST_HEAD(&bf_head);
578 if (bf_next != NULL || !bf_last->bf_state.stale)
579 list_move_tail(&bf->list, &bf_head);
580
581 if (!txpending) {
582 /*
583 * complete the acked-ones/xretried ones; update
584 * block-ack window
585 */
586 ath_tx_update_baw(sc, tid, seqno);
587
588 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
589 memcpy(tx_info->control.rates, rates, sizeof(rates));
590 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
591 rc_update = false;
592 }
593
594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
595 !txfail);
596 } else {
597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
600 }
601 /* retry the un-acked ones */
602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
603 struct ath_buf *tbf;
604
605 tbf = ath_clone_txbuf(sc, bf_last);
606 /*
607 * Update tx baw and complete the
608 * frame with failed status if we
609 * run out of tx buf.
610 */
611 if (!tbf) {
612 ath_tx_update_baw(sc, tid, seqno);
613
614 ath_tx_complete_buf(sc, bf, txq,
615 &bf_head, ts, 0);
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
618 break;
619 }
620
621 fi->bf = tbf;
622 }
623
624 /*
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
627 */
628 __skb_queue_tail(&bf_pending, skb);
629 }
630
631 bf = bf_next;
632 }
633
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
636 if (an->sleeping)
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
638
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
640 if (!an->sleeping) {
641 ath_tx_queue_tid(txq, tid);
642
643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
644 tid->ac->clear_ps_filter = true;
645 }
646 }
647
648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
650
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
653
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
657 }
658
659 rcu_read_unlock();
660
661 if (needreset)
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
663 }
664
665 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
666 {
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
669 }
670
671 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
674 {
675 struct ieee80211_tx_info *info;
676 bool txok, flush;
677
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
681
682 txq->axq_depth--;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
685
686 if (!bf_isampdu(bf)) {
687 if (!flush) {
688 info = IEEE80211_SKB_CB(bf->bf_mpdu);
689 memcpy(info->control.rates, bf->rates,
690 sizeof(info->control.rates));
691 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
692 }
693 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
694 } else
695 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
696
697 if (!flush)
698 ath_txq_schedule(sc, txq);
699 }
700
701 static bool ath_lookup_legacy(struct ath_buf *bf)
702 {
703 struct sk_buff *skb;
704 struct ieee80211_tx_info *tx_info;
705 struct ieee80211_tx_rate *rates;
706 int i;
707
708 skb = bf->bf_mpdu;
709 tx_info = IEEE80211_SKB_CB(skb);
710 rates = tx_info->control.rates;
711
712 for (i = 0; i < 4; i++) {
713 if (!rates[i].count || rates[i].idx < 0)
714 break;
715
716 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
717 return true;
718 }
719
720 return false;
721 }
722
723 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
724 struct ath_atx_tid *tid)
725 {
726 struct sk_buff *skb;
727 struct ieee80211_tx_info *tx_info;
728 struct ieee80211_tx_rate *rates;
729 u32 max_4ms_framelen, frmlen;
730 u16 aggr_limit, bt_aggr_limit, legacy = 0;
731 int q = tid->ac->txq->mac80211_qnum;
732 int i;
733
734 skb = bf->bf_mpdu;
735 tx_info = IEEE80211_SKB_CB(skb);
736 rates = bf->rates;
737
738 /*
739 * Find the lowest frame length among the rate series that will have a
740 * 4ms (or TXOP limited) transmit duration.
741 */
742 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
743
744 for (i = 0; i < 4; i++) {
745 int modeidx;
746
747 if (!rates[i].count)
748 continue;
749
750 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
751 legacy = 1;
752 break;
753 }
754
755 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
756 modeidx = MCS_HT40;
757 else
758 modeidx = MCS_HT20;
759
760 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
761 modeidx++;
762
763 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
764 max_4ms_framelen = min(max_4ms_framelen, frmlen);
765 }
766
767 /*
768 * limit aggregate size by the minimum rate if rate selected is
769 * not a probe rate, if rate selected is a probe rate then
770 * avoid aggregation of this packet.
771 */
772 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
773 return 0;
774
775 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
776
777 /*
778 * Override the default aggregation limit for BTCOEX.
779 */
780 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
781 if (bt_aggr_limit)
782 aggr_limit = bt_aggr_limit;
783
784 /*
785 * h/w can accept aggregates up to 16 bit lengths (65535).
786 * The IE, however can hold up to 65536, which shows up here
787 * as zero. Ignore 65536 since we are constrained by hw.
788 */
789 if (tid->an->maxampdu)
790 aggr_limit = min(aggr_limit, tid->an->maxampdu);
791
792 return aggr_limit;
793 }
794
795 /*
796 * Returns the number of delimiters to be added to
797 * meet the minimum required mpdudensity.
798 */
799 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
800 struct ath_buf *bf, u16 frmlen,
801 bool first_subfrm)
802 {
803 #define FIRST_DESC_NDELIMS 60
804 u32 nsymbits, nsymbols;
805 u16 minlen;
806 u8 flags, rix;
807 int width, streams, half_gi, ndelim, mindelim;
808 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
809
810 /* Select standard number of delimiters based on frame length alone */
811 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
812
813 /*
814 * If encryption enabled, hardware requires some more padding between
815 * subframes.
816 * TODO - this could be improved to be dependent on the rate.
817 * The hardware can keep up at lower rates, but not higher rates
818 */
819 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
820 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
821 ndelim += ATH_AGGR_ENCRYPTDELIM;
822
823 /*
824 * Add delimiter when using RTS/CTS with aggregation
825 * and non enterprise AR9003 card
826 */
827 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
828 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
829 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
830
831 /*
832 * Convert desired mpdu density from microeconds to bytes based
833 * on highest rate in rate series (i.e. first rate) to determine
834 * required minimum length for subframe. Take into account
835 * whether high rate is 20 or 40Mhz and half or full GI.
836 *
837 * If there is no mpdu density restriction, no further calculation
838 * is needed.
839 */
840
841 if (tid->an->mpdudensity == 0)
842 return ndelim;
843
844 rix = bf->rates[0].idx;
845 flags = bf->rates[0].flags;
846 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
847 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
848
849 if (half_gi)
850 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
851 else
852 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
853
854 if (nsymbols == 0)
855 nsymbols = 1;
856
857 streams = HT_RC_2_STREAMS(rix);
858 nsymbits = bits_per_symbol[rix % 8][width] * streams;
859 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
860
861 if (frmlen < minlen) {
862 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
863 ndelim = max(mindelim, ndelim);
864 }
865
866 return ndelim;
867 }
868
869 static struct ath_buf *
870 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
871 struct ath_atx_tid *tid, struct sk_buff_head **q)
872 {
873 struct ieee80211_tx_info *tx_info;
874 struct ath_frame_info *fi;
875 struct sk_buff *skb;
876 struct ath_buf *bf;
877 u16 seqno;
878
879 while (1) {
880 *q = &tid->retry_q;
881 if (skb_queue_empty(*q))
882 *q = &tid->buf_q;
883
884 skb = skb_peek(*q);
885 if (!skb)
886 break;
887
888 fi = get_frame_info(skb);
889 bf = fi->bf;
890 if (!fi->bf)
891 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
892 else
893 bf->bf_state.stale = false;
894
895 if (!bf) {
896 __skb_unlink(skb, *q);
897 ath_txq_skb_done(sc, txq, skb);
898 ieee80211_free_txskb(sc->hw, skb);
899 continue;
900 }
901
902 bf->bf_next = NULL;
903 bf->bf_lastbf = bf;
904
905 tx_info = IEEE80211_SKB_CB(skb);
906 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
907
908 /*
909 * No aggregation session is running, but there may be frames
910 * from a previous session or a failed attempt in the queue.
911 * Send them out as normal data frames
912 */
913 if (!tid->active)
914 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
915
916 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
917 bf->bf_state.bf_type = 0;
918 return bf;
919 }
920
921 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
922 seqno = bf->bf_state.seqno;
923
924 /* do not step over block-ack window */
925 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
926 break;
927
928 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
929 struct ath_tx_status ts = {};
930 struct list_head bf_head;
931
932 INIT_LIST_HEAD(&bf_head);
933 list_add(&bf->list, &bf_head);
934 __skb_unlink(skb, *q);
935 ath_tx_update_baw(sc, tid, seqno);
936 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
937 continue;
938 }
939
940 return bf;
941 }
942
943 return NULL;
944 }
945
946 static bool
947 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
948 struct ath_atx_tid *tid, struct list_head *bf_q,
949 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
950 int *aggr_len)
951 {
952 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
953 struct ath_buf *bf = bf_first, *bf_prev = NULL;
954 int nframes = 0, ndelim;
955 u16 aggr_limit = 0, al = 0, bpad = 0,
956 al_delta, h_baw = tid->baw_size / 2;
957 struct ieee80211_tx_info *tx_info;
958 struct ath_frame_info *fi;
959 struct sk_buff *skb;
960 bool closed = false;
961
962 bf = bf_first;
963 aggr_limit = ath_lookup_rate(sc, bf, tid);
964
965 do {
966 skb = bf->bf_mpdu;
967 fi = get_frame_info(skb);
968
969 /* do not exceed aggregation limit */
970 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
971 if (nframes) {
972 if (aggr_limit < al + bpad + al_delta ||
973 ath_lookup_legacy(bf) || nframes >= h_baw)
974 break;
975
976 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
977 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
978 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
979 break;
980 }
981
982 /* add padding for previous frame to aggregation length */
983 al += bpad + al_delta;
984
985 /*
986 * Get the delimiters needed to meet the MPDU
987 * density for this node.
988 */
989 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
990 !nframes);
991 bpad = PADBYTES(al_delta) + (ndelim << 2);
992
993 nframes++;
994 bf->bf_next = NULL;
995
996 /* link buffers of this frame to the aggregate */
997 if (!fi->baw_tracked)
998 ath_tx_addto_baw(sc, tid, bf);
999 bf->bf_state.ndelim = ndelim;
1000
1001 __skb_unlink(skb, tid_q);
1002 list_add_tail(&bf->list, bf_q);
1003 if (bf_prev)
1004 bf_prev->bf_next = bf;
1005
1006 bf_prev = bf;
1007
1008 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1009 if (!bf) {
1010 closed = true;
1011 break;
1012 }
1013 } while (ath_tid_has_buffered(tid));
1014
1015 bf = bf_first;
1016 bf->bf_lastbf = bf_prev;
1017
1018 if (bf == bf_prev) {
1019 al = get_frame_info(bf->bf_mpdu)->framelen;
1020 bf->bf_state.bf_type = BUF_AMPDU;
1021 } else {
1022 TX_STAT_INC(txq->axq_qnum, a_aggr);
1023 }
1024
1025 *aggr_len = al;
1026
1027 return closed;
1028 #undef PADBYTES
1029 }
1030
1031 /*
1032 * rix - rate index
1033 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1034 * width - 0 for 20 MHz, 1 for 40 MHz
1035 * half_gi - to use 4us v/s 3.6 us for symbol time
1036 */
1037 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1038 int width, int half_gi, bool shortPreamble)
1039 {
1040 u32 nbits, nsymbits, duration, nsymbols;
1041 int streams;
1042
1043 /* find number of symbols: PLCP + data */
1044 streams = HT_RC_2_STREAMS(rix);
1045 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1046 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1047 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1048
1049 if (!half_gi)
1050 duration = SYMBOL_TIME(nsymbols);
1051 else
1052 duration = SYMBOL_TIME_HALFGI(nsymbols);
1053
1054 /* addup duration for legacy/ht training and signal fields */
1055 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1056
1057 return duration;
1058 }
1059
1060 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1061 {
1062 int streams = HT_RC_2_STREAMS(mcs);
1063 int symbols, bits;
1064 int bytes = 0;
1065
1066 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1067 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1068 bits -= OFDM_PLCP_BITS;
1069 bytes = bits / 8;
1070 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1071 if (bytes > 65532)
1072 bytes = 65532;
1073
1074 return bytes;
1075 }
1076
1077 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1078 {
1079 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1080 int mcs;
1081
1082 /* 4ms is the default (and maximum) duration */
1083 if (!txop || txop > 4096)
1084 txop = 4096;
1085
1086 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1087 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1088 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1089 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1090 for (mcs = 0; mcs < 32; mcs++) {
1091 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1092 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1093 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1094 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1095 }
1096 }
1097
1098 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1099 struct ath_tx_info *info, int len, bool rts)
1100 {
1101 struct ath_hw *ah = sc->sc_ah;
1102 struct sk_buff *skb;
1103 struct ieee80211_tx_info *tx_info;
1104 struct ieee80211_tx_rate *rates;
1105 const struct ieee80211_rate *rate;
1106 struct ieee80211_hdr *hdr;
1107 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1108 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1109 int i;
1110 u8 rix = 0;
1111
1112 skb = bf->bf_mpdu;
1113 tx_info = IEEE80211_SKB_CB(skb);
1114 rates = bf->rates;
1115 hdr = (struct ieee80211_hdr *)skb->data;
1116
1117 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1118 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1119 info->rtscts_rate = fi->rtscts_rate;
1120
1121 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1122 bool is_40, is_sgi, is_sp;
1123 int phy;
1124
1125 if (!rates[i].count || (rates[i].idx < 0))
1126 continue;
1127
1128 rix = rates[i].idx;
1129 info->rates[i].Tries = rates[i].count;
1130
1131 /*
1132 * Handle RTS threshold for unaggregated HT frames.
1133 */
1134 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1135 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1136 unlikely(rts_thresh != (u32) -1)) {
1137 if (!rts_thresh || (len > rts_thresh))
1138 rts = true;
1139 }
1140
1141 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1143 info->flags |= ATH9K_TXDESC_RTSENA;
1144 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1145 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1146 info->flags |= ATH9K_TXDESC_CTSENA;
1147 }
1148
1149 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1150 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1151 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1152 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1153
1154 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1155 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1156 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1157
1158 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1159 /* MCS rates */
1160 info->rates[i].Rate = rix | 0x80;
1161 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1162 ah->txchainmask, info->rates[i].Rate);
1163 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1164 is_40, is_sgi, is_sp);
1165 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1166 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1167 continue;
1168 }
1169
1170 /* legacy rates */
1171 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1172 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1173 !(rate->flags & IEEE80211_RATE_ERP_G))
1174 phy = WLAN_RC_PHY_CCK;
1175 else
1176 phy = WLAN_RC_PHY_OFDM;
1177
1178 info->rates[i].Rate = rate->hw_value;
1179 if (rate->hw_value_short) {
1180 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1181 info->rates[i].Rate |= rate->hw_value_short;
1182 } else {
1183 is_sp = false;
1184 }
1185
1186 if (bf->bf_state.bfs_paprd)
1187 info->rates[i].ChSel = ah->txchainmask;
1188 else
1189 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1190 ah->txchainmask, info->rates[i].Rate);
1191
1192 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1193 phy, rate->bitrate * 100, len, rix, is_sp);
1194 }
1195
1196 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1197 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1198 info->flags &= ~ATH9K_TXDESC_RTSENA;
1199
1200 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1201 if (info->flags & ATH9K_TXDESC_RTSENA)
1202 info->flags &= ~ATH9K_TXDESC_CTSENA;
1203 }
1204
1205 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1206 {
1207 struct ieee80211_hdr *hdr;
1208 enum ath9k_pkt_type htype;
1209 __le16 fc;
1210
1211 hdr = (struct ieee80211_hdr *)skb->data;
1212 fc = hdr->frame_control;
1213
1214 if (ieee80211_is_beacon(fc))
1215 htype = ATH9K_PKT_TYPE_BEACON;
1216 else if (ieee80211_is_probe_resp(fc))
1217 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1218 else if (ieee80211_is_atim(fc))
1219 htype = ATH9K_PKT_TYPE_ATIM;
1220 else if (ieee80211_is_pspoll(fc))
1221 htype = ATH9K_PKT_TYPE_PSPOLL;
1222 else
1223 htype = ATH9K_PKT_TYPE_NORMAL;
1224
1225 return htype;
1226 }
1227
1228 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1229 struct ath_txq *txq, int len)
1230 {
1231 struct ath_hw *ah = sc->sc_ah;
1232 struct ath_buf *bf_first = NULL;
1233 struct ath_tx_info info;
1234 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1235 bool rts = false;
1236
1237 memset(&info, 0, sizeof(info));
1238 info.is_first = true;
1239 info.is_last = true;
1240 info.txpower = MAX_RATE_POWER;
1241 info.qcu = txq->axq_qnum;
1242
1243 while (bf) {
1244 struct sk_buff *skb = bf->bf_mpdu;
1245 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1246 struct ath_frame_info *fi = get_frame_info(skb);
1247 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1248
1249 info.type = get_hw_packet_type(skb);
1250 if (bf->bf_next)
1251 info.link = bf->bf_next->bf_daddr;
1252 else
1253 info.link = 0;
1254
1255 if (!bf_first) {
1256 bf_first = bf;
1257
1258 info.flags = ATH9K_TXDESC_INTREQ;
1259 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1260 txq == sc->tx.uapsdq)
1261 info.flags |= ATH9K_TXDESC_CLRDMASK;
1262
1263 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1264 info.flags |= ATH9K_TXDESC_NOACK;
1265 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1266 info.flags |= ATH9K_TXDESC_LDPC;
1267
1268 if (bf->bf_state.bfs_paprd)
1269 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1270 ATH9K_TXDESC_PAPRD_S;
1271
1272 /*
1273 * mac80211 doesn't handle RTS threshold for HT because
1274 * the decision has to be taken based on AMPDU length
1275 * and aggregation is done entirely inside ath9k.
1276 * Set the RTS/CTS flag for the first subframe based
1277 * on the threshold.
1278 */
1279 if (aggr && (bf == bf_first) &&
1280 unlikely(rts_thresh != (u32) -1)) {
1281 /*
1282 * "len" is the size of the entire AMPDU.
1283 */
1284 if (!rts_thresh || (len > rts_thresh))
1285 rts = true;
1286 }
1287
1288 if (!aggr)
1289 len = fi->framelen;
1290
1291 ath_buf_set_rate(sc, bf, &info, len, rts);
1292 }
1293
1294 info.buf_addr[0] = bf->bf_buf_addr;
1295 info.buf_len[0] = skb->len;
1296 info.pkt_len = fi->framelen;
1297 info.keyix = fi->keyix;
1298 info.keytype = fi->keytype;
1299
1300 if (aggr) {
1301 if (bf == bf_first)
1302 info.aggr = AGGR_BUF_FIRST;
1303 else if (bf == bf_first->bf_lastbf)
1304 info.aggr = AGGR_BUF_LAST;
1305 else
1306 info.aggr = AGGR_BUF_MIDDLE;
1307
1308 info.ndelim = bf->bf_state.ndelim;
1309 info.aggr_len = len;
1310 }
1311
1312 if (bf == bf_first->bf_lastbf)
1313 bf_first = NULL;
1314
1315 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1316 bf = bf->bf_next;
1317 }
1318 }
1319
1320 static void
1321 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1322 struct ath_atx_tid *tid, struct list_head *bf_q,
1323 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1324 {
1325 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1326 struct sk_buff *skb;
1327 int nframes = 0;
1328
1329 do {
1330 struct ieee80211_tx_info *tx_info;
1331 skb = bf->bf_mpdu;
1332
1333 nframes++;
1334 __skb_unlink(skb, tid_q);
1335 list_add_tail(&bf->list, bf_q);
1336 if (bf_prev)
1337 bf_prev->bf_next = bf;
1338 bf_prev = bf;
1339
1340 if (nframes >= 2)
1341 break;
1342
1343 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1344 if (!bf)
1345 break;
1346
1347 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1348 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1349 break;
1350
1351 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1352 } while (1);
1353 }
1354
1355 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1356 struct ath_atx_tid *tid, bool *stop)
1357 {
1358 struct ath_buf *bf;
1359 struct ieee80211_tx_info *tx_info;
1360 struct sk_buff_head *tid_q;
1361 struct list_head bf_q;
1362 int aggr_len = 0;
1363 bool aggr, last = true;
1364
1365 if (!ath_tid_has_buffered(tid))
1366 return false;
1367
1368 INIT_LIST_HEAD(&bf_q);
1369
1370 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1371 if (!bf)
1372 return false;
1373
1374 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1375 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1376 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1377 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1378 *stop = true;
1379 return false;
1380 }
1381
1382 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1383 if (aggr)
1384 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1385 tid_q, &aggr_len);
1386 else
1387 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1388
1389 if (list_empty(&bf_q))
1390 return false;
1391
1392 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1393 tid->ac->clear_ps_filter = false;
1394 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1395 }
1396
1397 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1398 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1399 return true;
1400 }
1401
1402 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1403 u16 tid, u16 *ssn)
1404 {
1405 struct ath_atx_tid *txtid;
1406 struct ath_txq *txq;
1407 struct ath_node *an;
1408 u8 density;
1409
1410 an = (struct ath_node *)sta->drv_priv;
1411 txtid = ATH_AN_2_TID(an, tid);
1412 txq = txtid->ac->txq;
1413
1414 ath_txq_lock(sc, txq);
1415
1416 /* update ampdu factor/density, they may have changed. This may happen
1417 * in HT IBSS when a beacon with HT-info is received after the station
1418 * has already been added.
1419 */
1420 if (sta->ht_cap.ht_supported) {
1421 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1422 sta->ht_cap.ampdu_factor);
1423 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1424 an->mpdudensity = density;
1425 }
1426
1427 /* force sequence number allocation for pending frames */
1428 ath_tx_tid_change_state(sc, txtid);
1429
1430 txtid->active = true;
1431 txtid->paused = true;
1432 *ssn = txtid->seq_start = txtid->seq_next;
1433 txtid->bar_index = -1;
1434
1435 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1436 txtid->baw_head = txtid->baw_tail = 0;
1437
1438 ath_txq_unlock_complete(sc, txq);
1439
1440 return 0;
1441 }
1442
1443 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1444 {
1445 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1446 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1447 struct ath_txq *txq = txtid->ac->txq;
1448
1449 ath_txq_lock(sc, txq);
1450 txtid->active = false;
1451 txtid->paused = false;
1452 ath_tx_flush_tid(sc, txtid);
1453 ath_tx_tid_change_state(sc, txtid);
1454 ath_txq_unlock_complete(sc, txq);
1455 }
1456
1457 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1458 struct ath_node *an)
1459 {
1460 struct ath_atx_tid *tid;
1461 struct ath_atx_ac *ac;
1462 struct ath_txq *txq;
1463 bool buffered;
1464 int tidno;
1465
1466 for (tidno = 0, tid = &an->tid[tidno];
1467 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1468
1469 ac = tid->ac;
1470 txq = ac->txq;
1471
1472 ath_txq_lock(sc, txq);
1473
1474 if (!tid->sched) {
1475 ath_txq_unlock(sc, txq);
1476 continue;
1477 }
1478
1479 buffered = ath_tid_has_buffered(tid);
1480
1481 tid->sched = false;
1482 list_del(&tid->list);
1483
1484 if (ac->sched) {
1485 ac->sched = false;
1486 list_del(&ac->list);
1487 }
1488
1489 ath_txq_unlock(sc, txq);
1490
1491 ieee80211_sta_set_buffered(sta, tidno, buffered);
1492 }
1493 }
1494
1495 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1496 {
1497 struct ath_atx_tid *tid;
1498 struct ath_atx_ac *ac;
1499 struct ath_txq *txq;
1500 int tidno;
1501
1502 for (tidno = 0, tid = &an->tid[tidno];
1503 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1504
1505 ac = tid->ac;
1506 txq = ac->txq;
1507
1508 ath_txq_lock(sc, txq);
1509 ac->clear_ps_filter = true;
1510
1511 if (!tid->paused && ath_tid_has_buffered(tid)) {
1512 ath_tx_queue_tid(txq, tid);
1513 ath_txq_schedule(sc, txq);
1514 }
1515
1516 ath_txq_unlock_complete(sc, txq);
1517 }
1518 }
1519
1520 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1521 u16 tidno)
1522 {
1523 struct ath_atx_tid *tid;
1524 struct ath_node *an;
1525 struct ath_txq *txq;
1526
1527 an = (struct ath_node *)sta->drv_priv;
1528 tid = ATH_AN_2_TID(an, tidno);
1529 txq = tid->ac->txq;
1530
1531 ath_txq_lock(sc, txq);
1532
1533 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1534 tid->paused = false;
1535
1536 if (ath_tid_has_buffered(tid)) {
1537 ath_tx_queue_tid(txq, tid);
1538 ath_txq_schedule(sc, txq);
1539 }
1540
1541 ath_txq_unlock_complete(sc, txq);
1542 }
1543
1544 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1545 struct ieee80211_sta *sta,
1546 u16 tids, int nframes,
1547 enum ieee80211_frame_release_type reason,
1548 bool more_data)
1549 {
1550 struct ath_softc *sc = hw->priv;
1551 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1552 struct ath_txq *txq = sc->tx.uapsdq;
1553 struct ieee80211_tx_info *info;
1554 struct list_head bf_q;
1555 struct ath_buf *bf_tail = NULL, *bf;
1556 struct sk_buff_head *tid_q;
1557 int sent = 0;
1558 int i;
1559
1560 INIT_LIST_HEAD(&bf_q);
1561 for (i = 0; tids && nframes; i++, tids >>= 1) {
1562 struct ath_atx_tid *tid;
1563
1564 if (!(tids & 1))
1565 continue;
1566
1567 tid = ATH_AN_2_TID(an, i);
1568 if (tid->paused)
1569 continue;
1570
1571 ath_txq_lock(sc, tid->ac->txq);
1572 while (nframes > 0) {
1573 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1574 if (!bf)
1575 break;
1576
1577 __skb_unlink(bf->bf_mpdu, tid_q);
1578 list_add_tail(&bf->list, &bf_q);
1579 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1580 if (bf_isampdu(bf)) {
1581 ath_tx_addto_baw(sc, tid, bf);
1582 bf->bf_state.bf_type &= ~BUF_AGGR;
1583 }
1584 if (bf_tail)
1585 bf_tail->bf_next = bf;
1586
1587 bf_tail = bf;
1588 nframes--;
1589 sent++;
1590 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1591
1592 if (an->sta && !ath_tid_has_buffered(tid))
1593 ieee80211_sta_set_buffered(an->sta, i, false);
1594 }
1595 ath_txq_unlock_complete(sc, tid->ac->txq);
1596 }
1597
1598 if (list_empty(&bf_q))
1599 return;
1600
1601 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1602 info->flags |= IEEE80211_TX_STATUS_EOSP;
1603
1604 bf = list_first_entry(&bf_q, struct ath_buf, list);
1605 ath_txq_lock(sc, txq);
1606 ath_tx_fill_desc(sc, bf, txq, 0);
1607 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1608 ath_txq_unlock(sc, txq);
1609 }
1610
1611 /********************/
1612 /* Queue Management */
1613 /********************/
1614
1615 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1616 {
1617 struct ath_hw *ah = sc->sc_ah;
1618 struct ath9k_tx_queue_info qi;
1619 static const int subtype_txq_to_hwq[] = {
1620 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1621 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1622 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1623 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1624 };
1625 int axq_qnum, i;
1626
1627 memset(&qi, 0, sizeof(qi));
1628 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1629 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1630 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1631 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1632 qi.tqi_physCompBuf = 0;
1633
1634 /*
1635 * Enable interrupts only for EOL and DESC conditions.
1636 * We mark tx descriptors to receive a DESC interrupt
1637 * when a tx queue gets deep; otherwise waiting for the
1638 * EOL to reap descriptors. Note that this is done to
1639 * reduce interrupt load and this only defers reaping
1640 * descriptors, never transmitting frames. Aside from
1641 * reducing interrupts this also permits more concurrency.
1642 * The only potential downside is if the tx queue backs
1643 * up in which case the top half of the kernel may backup
1644 * due to a lack of tx descriptors.
1645 *
1646 * The UAPSD queue is an exception, since we take a desc-
1647 * based intr on the EOSP frames.
1648 */
1649 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1650 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1651 } else {
1652 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1653 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1654 else
1655 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1656 TXQ_FLAG_TXDESCINT_ENABLE;
1657 }
1658 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1659 if (axq_qnum == -1) {
1660 /*
1661 * NB: don't print a message, this happens
1662 * normally on parts with too few tx queues
1663 */
1664 return NULL;
1665 }
1666 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1667 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1668
1669 txq->axq_qnum = axq_qnum;
1670 txq->mac80211_qnum = -1;
1671 txq->axq_link = NULL;
1672 __skb_queue_head_init(&txq->complete_q);
1673 INIT_LIST_HEAD(&txq->axq_q);
1674 INIT_LIST_HEAD(&txq->axq_acq);
1675 spin_lock_init(&txq->axq_lock);
1676 txq->axq_depth = 0;
1677 txq->axq_ampdu_depth = 0;
1678 txq->axq_tx_inprogress = false;
1679 sc->tx.txqsetup |= 1<<axq_qnum;
1680
1681 txq->txq_headidx = txq->txq_tailidx = 0;
1682 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1683 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1684 }
1685 return &sc->tx.txq[axq_qnum];
1686 }
1687
1688 int ath_txq_update(struct ath_softc *sc, int qnum,
1689 struct ath9k_tx_queue_info *qinfo)
1690 {
1691 struct ath_hw *ah = sc->sc_ah;
1692 int error = 0;
1693 struct ath9k_tx_queue_info qi;
1694
1695 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1696
1697 ath9k_hw_get_txq_props(ah, qnum, &qi);
1698 qi.tqi_aifs = qinfo->tqi_aifs;
1699 qi.tqi_cwmin = qinfo->tqi_cwmin;
1700 qi.tqi_cwmax = qinfo->tqi_cwmax;
1701 qi.tqi_burstTime = qinfo->tqi_burstTime;
1702 qi.tqi_readyTime = qinfo->tqi_readyTime;
1703
1704 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1705 ath_err(ath9k_hw_common(sc->sc_ah),
1706 "Unable to update hardware queue %u!\n", qnum);
1707 error = -EIO;
1708 } else {
1709 ath9k_hw_resettxqueue(ah, qnum);
1710 }
1711
1712 return error;
1713 }
1714
1715 int ath_cabq_update(struct ath_softc *sc)
1716 {
1717 struct ath9k_tx_queue_info qi;
1718 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1719 int qnum = sc->beacon.cabq->axq_qnum;
1720
1721 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1722 /*
1723 * Ensure the readytime % is within the bounds.
1724 */
1725 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1726 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1727 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1728 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1729
1730 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1731 sc->config.cabqReadytime) / 100;
1732 ath_txq_update(sc, qnum, &qi);
1733
1734 return 0;
1735 }
1736
1737 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1738 struct list_head *list)
1739 {
1740 struct ath_buf *bf, *lastbf;
1741 struct list_head bf_head;
1742 struct ath_tx_status ts;
1743
1744 memset(&ts, 0, sizeof(ts));
1745 ts.ts_status = ATH9K_TX_FLUSH;
1746 INIT_LIST_HEAD(&bf_head);
1747
1748 while (!list_empty(list)) {
1749 bf = list_first_entry(list, struct ath_buf, list);
1750
1751 if (bf->bf_state.stale) {
1752 list_del(&bf->list);
1753
1754 ath_tx_return_buffer(sc, bf);
1755 continue;
1756 }
1757
1758 lastbf = bf->bf_lastbf;
1759 list_cut_position(&bf_head, list, &lastbf->list);
1760 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1761 }
1762 }
1763
1764 /*
1765 * Drain a given TX queue (could be Beacon or Data)
1766 *
1767 * This assumes output has been stopped and
1768 * we do not need to block ath_tx_tasklet.
1769 */
1770 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1771 {
1772 ath_txq_lock(sc, txq);
1773
1774 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1775 int idx = txq->txq_tailidx;
1776
1777 while (!list_empty(&txq->txq_fifo[idx])) {
1778 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1779
1780 INCR(idx, ATH_TXFIFO_DEPTH);
1781 }
1782 txq->txq_tailidx = idx;
1783 }
1784
1785 txq->axq_link = NULL;
1786 txq->axq_tx_inprogress = false;
1787 ath_drain_txq_list(sc, txq, &txq->axq_q);
1788
1789 ath_txq_unlock_complete(sc, txq);
1790 }
1791
1792 bool ath_drain_all_txq(struct ath_softc *sc)
1793 {
1794 struct ath_hw *ah = sc->sc_ah;
1795 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1796 struct ath_txq *txq;
1797 int i;
1798 u32 npend = 0;
1799
1800 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1801 return true;
1802
1803 ath9k_hw_abort_tx_dma(ah);
1804
1805 /* Check if any queue remains active */
1806 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1807 if (!ATH_TXQ_SETUP(sc, i))
1808 continue;
1809
1810 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1811 npend |= BIT(i);
1812 }
1813
1814 if (npend)
1815 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1816
1817 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1818 if (!ATH_TXQ_SETUP(sc, i))
1819 continue;
1820
1821 /*
1822 * The caller will resume queues with ieee80211_wake_queues.
1823 * Mark the queue as not stopped to prevent ath_tx_complete
1824 * from waking the queue too early.
1825 */
1826 txq = &sc->tx.txq[i];
1827 txq->stopped = false;
1828 ath_draintxq(sc, txq);
1829 }
1830
1831 return !npend;
1832 }
1833
1834 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1835 {
1836 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1837 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1838 }
1839
1840 /* For each axq_acq entry, for each tid, try to schedule packets
1841 * for transmit until ampdu_depth has reached min Q depth.
1842 */
1843 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1844 {
1845 struct ath_atx_ac *ac, *last_ac;
1846 struct ath_atx_tid *tid, *last_tid;
1847 bool sent = false;
1848
1849 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1850 list_empty(&txq->axq_acq))
1851 return;
1852
1853 rcu_read_lock();
1854
1855 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1856 while (!list_empty(&txq->axq_acq)) {
1857 bool stop = false;
1858
1859 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1860 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1861 list_del(&ac->list);
1862 ac->sched = false;
1863
1864 while (!list_empty(&ac->tid_q)) {
1865
1866 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1867 list);
1868 list_del(&tid->list);
1869 tid->sched = false;
1870
1871 if (tid->paused)
1872 continue;
1873
1874 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1875 sent = true;
1876
1877 /*
1878 * add tid to round-robin queue if more frames
1879 * are pending for the tid
1880 */
1881 if (ath_tid_has_buffered(tid))
1882 ath_tx_queue_tid(txq, tid);
1883
1884 if (stop || tid == last_tid)
1885 break;
1886 }
1887
1888 if (!list_empty(&ac->tid_q) && !ac->sched) {
1889 ac->sched = true;
1890 list_add_tail(&ac->list, &txq->axq_acq);
1891 }
1892
1893 if (stop)
1894 break;
1895
1896 if (ac == last_ac) {
1897 if (!sent)
1898 break;
1899
1900 sent = false;
1901 last_ac = list_entry(txq->axq_acq.prev,
1902 struct ath_atx_ac, list);
1903 }
1904 }
1905
1906 rcu_read_unlock();
1907 }
1908
1909 /***********/
1910 /* TX, DMA */
1911 /***********/
1912
1913 /*
1914 * Insert a chain of ath_buf (descriptors) on a txq and
1915 * assume the descriptors are already chained together by caller.
1916 */
1917 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1918 struct list_head *head, bool internal)
1919 {
1920 struct ath_hw *ah = sc->sc_ah;
1921 struct ath_common *common = ath9k_hw_common(ah);
1922 struct ath_buf *bf, *bf_last;
1923 bool puttxbuf = false;
1924 bool edma;
1925
1926 /*
1927 * Insert the frame on the outbound list and
1928 * pass it on to the hardware.
1929 */
1930
1931 if (list_empty(head))
1932 return;
1933
1934 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1935 bf = list_first_entry(head, struct ath_buf, list);
1936 bf_last = list_entry(head->prev, struct ath_buf, list);
1937
1938 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1939 txq->axq_qnum, txq->axq_depth);
1940
1941 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1942 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1943 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1944 puttxbuf = true;
1945 } else {
1946 list_splice_tail_init(head, &txq->axq_q);
1947
1948 if (txq->axq_link) {
1949 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1950 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1951 txq->axq_qnum, txq->axq_link,
1952 ito64(bf->bf_daddr), bf->bf_desc);
1953 } else if (!edma)
1954 puttxbuf = true;
1955
1956 txq->axq_link = bf_last->bf_desc;
1957 }
1958
1959 if (puttxbuf) {
1960 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1961 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1962 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1963 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1964 }
1965
1966 if (!edma) {
1967 TX_STAT_INC(txq->axq_qnum, txstart);
1968 ath9k_hw_txstart(ah, txq->axq_qnum);
1969 }
1970
1971 if (!internal) {
1972 while (bf) {
1973 txq->axq_depth++;
1974 if (bf_is_ampdu_not_probing(bf))
1975 txq->axq_ampdu_depth++;
1976
1977 bf_last = bf->bf_lastbf;
1978 bf = bf_last->bf_next;
1979 bf_last->bf_next = NULL;
1980 }
1981 }
1982 }
1983
1984 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1985 struct ath_atx_tid *tid, struct sk_buff *skb)
1986 {
1987 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1988 struct ath_frame_info *fi = get_frame_info(skb);
1989 struct list_head bf_head;
1990 struct ath_buf *bf = fi->bf;
1991
1992 INIT_LIST_HEAD(&bf_head);
1993 list_add_tail(&bf->list, &bf_head);
1994 bf->bf_state.bf_type = 0;
1995 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1996 bf->bf_state.bf_type = BUF_AMPDU;
1997 ath_tx_addto_baw(sc, tid, bf);
1998 }
1999
2000 bf->bf_next = NULL;
2001 bf->bf_lastbf = bf;
2002 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2003 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2004 TX_STAT_INC(txq->axq_qnum, queued);
2005 }
2006
2007 static void setup_frame_info(struct ieee80211_hw *hw,
2008 struct ieee80211_sta *sta,
2009 struct sk_buff *skb,
2010 int framelen)
2011 {
2012 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2013 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2014 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2015 const struct ieee80211_rate *rate;
2016 struct ath_frame_info *fi = get_frame_info(skb);
2017 struct ath_node *an = NULL;
2018 enum ath9k_key_type keytype;
2019 bool short_preamble = false;
2020
2021 /*
2022 * We check if Short Preamble is needed for the CTS rate by
2023 * checking the BSS's global flag.
2024 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2025 */
2026 if (tx_info->control.vif &&
2027 tx_info->control.vif->bss_conf.use_short_preamble)
2028 short_preamble = true;
2029
2030 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2031 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2032
2033 if (sta)
2034 an = (struct ath_node *) sta->drv_priv;
2035
2036 memset(fi, 0, sizeof(*fi));
2037 if (hw_key)
2038 fi->keyix = hw_key->hw_key_idx;
2039 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2040 fi->keyix = an->ps_key;
2041 else
2042 fi->keyix = ATH9K_TXKEYIX_INVALID;
2043 fi->keytype = keytype;
2044 fi->framelen = framelen;
2045 fi->rtscts_rate = rate->hw_value;
2046 if (short_preamble)
2047 fi->rtscts_rate |= rate->hw_value_short;
2048 }
2049
2050 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2051 {
2052 struct ath_hw *ah = sc->sc_ah;
2053 struct ath9k_channel *curchan = ah->curchan;
2054
2055 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2056 (curchan->channelFlags & CHANNEL_5GHZ) &&
2057 (chainmask == 0x7) && (rate < 0x90))
2058 return 0x3;
2059 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2060 IS_CCK_RATE(rate))
2061 return 0x2;
2062 else
2063 return chainmask;
2064 }
2065
2066 /*
2067 * Assign a descriptor (and sequence number if necessary,
2068 * and map buffer for DMA. Frees skb on error
2069 */
2070 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2071 struct ath_txq *txq,
2072 struct ath_atx_tid *tid,
2073 struct sk_buff *skb)
2074 {
2075 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2076 struct ath_frame_info *fi = get_frame_info(skb);
2077 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2078 struct ath_buf *bf;
2079 int fragno;
2080 u16 seqno;
2081
2082 bf = ath_tx_get_buffer(sc);
2083 if (!bf) {
2084 ath_dbg(common, XMIT, "TX buffers are full\n");
2085 return NULL;
2086 }
2087
2088 ATH_TXBUF_RESET(bf);
2089
2090 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2091 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2092 seqno = tid->seq_next;
2093 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2094
2095 if (fragno)
2096 hdr->seq_ctrl |= cpu_to_le16(fragno);
2097
2098 if (!ieee80211_has_morefrags(hdr->frame_control))
2099 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2100
2101 bf->bf_state.seqno = seqno;
2102 }
2103
2104 bf->bf_mpdu = skb;
2105
2106 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2107 skb->len, DMA_TO_DEVICE);
2108 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2109 bf->bf_mpdu = NULL;
2110 bf->bf_buf_addr = 0;
2111 ath_err(ath9k_hw_common(sc->sc_ah),
2112 "dma_mapping_error() on TX\n");
2113 ath_tx_return_buffer(sc, bf);
2114 return NULL;
2115 }
2116
2117 fi->bf = bf;
2118
2119 return bf;
2120 }
2121
2122 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2123 struct ath_tx_control *txctl)
2124 {
2125 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2126 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2127 struct ieee80211_sta *sta = txctl->sta;
2128 struct ieee80211_vif *vif = info->control.vif;
2129 struct ath_vif *avp;
2130 struct ath_softc *sc = hw->priv;
2131 int frmlen = skb->len + FCS_LEN;
2132 int padpos, padsize;
2133
2134 /* NOTE: sta can be NULL according to net/mac80211.h */
2135 if (sta)
2136 txctl->an = (struct ath_node *)sta->drv_priv;
2137 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2138 avp = (void *)vif->drv_priv;
2139 txctl->an = &avp->mcast_node;
2140 }
2141
2142 if (info->control.hw_key)
2143 frmlen += info->control.hw_key->icv_len;
2144
2145 /*
2146 * As a temporary workaround, assign seq# here; this will likely need
2147 * to be cleaned up to work better with Beacon transmission and virtual
2148 * BSSes.
2149 */
2150 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2151 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2152 sc->tx.seq_no += 0x10;
2153 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2154 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2155 }
2156
2157 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2158 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2159 !ieee80211_is_data(hdr->frame_control))
2160 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2161
2162 /* Add the padding after the header if this is not already done */
2163 padpos = ieee80211_hdrlen(hdr->frame_control);
2164 padsize = padpos & 3;
2165 if (padsize && skb->len > padpos) {
2166 if (skb_headroom(skb) < padsize)
2167 return -ENOMEM;
2168
2169 skb_push(skb, padsize);
2170 memmove(skb->data, skb->data + padsize, padpos);
2171 }
2172
2173 setup_frame_info(hw, sta, skb, frmlen);
2174 return 0;
2175 }
2176
2177
2178 /* Upon failure caller should free skb */
2179 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2180 struct ath_tx_control *txctl)
2181 {
2182 struct ieee80211_hdr *hdr;
2183 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2184 struct ieee80211_sta *sta = txctl->sta;
2185 struct ieee80211_vif *vif = info->control.vif;
2186 struct ath_softc *sc = hw->priv;
2187 struct ath_txq *txq = txctl->txq;
2188 struct ath_atx_tid *tid = NULL;
2189 struct ath_buf *bf;
2190 int q;
2191 int ret;
2192
2193 ret = ath_tx_prepare(hw, skb, txctl);
2194 if (ret)
2195 return ret;
2196
2197 hdr = (struct ieee80211_hdr *) skb->data;
2198 /*
2199 * At this point, the vif, hw_key and sta pointers in the tx control
2200 * info are no longer valid (overwritten by the ath_frame_info data.
2201 */
2202
2203 q = skb_get_queue_mapping(skb);
2204
2205 ath_txq_lock(sc, txq);
2206 if (txq == sc->tx.txq_map[q] &&
2207 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2208 !txq->stopped) {
2209 ieee80211_stop_queue(sc->hw, q);
2210 txq->stopped = true;
2211 }
2212
2213 if (txctl->an && ieee80211_is_data_present(hdr->frame_control))
2214 tid = ath_get_skb_tid(sc, txctl->an, skb);
2215
2216 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2217 ath_txq_unlock(sc, txq);
2218 txq = sc->tx.uapsdq;
2219 ath_txq_lock(sc, txq);
2220 } else if (txctl->an &&
2221 ieee80211_is_data_present(hdr->frame_control)) {
2222 WARN_ON(tid->ac->txq != txctl->txq);
2223
2224 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2225 tid->ac->clear_ps_filter = true;
2226
2227 /*
2228 * Add this frame to software queue for scheduling later
2229 * for aggregation.
2230 */
2231 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2232 __skb_queue_tail(&tid->buf_q, skb);
2233 if (!txctl->an->sleeping)
2234 ath_tx_queue_tid(txq, tid);
2235
2236 ath_txq_schedule(sc, txq);
2237 goto out;
2238 }
2239
2240 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2241 if (!bf) {
2242 ath_txq_skb_done(sc, txq, skb);
2243 if (txctl->paprd)
2244 dev_kfree_skb_any(skb);
2245 else
2246 ieee80211_free_txskb(sc->hw, skb);
2247 goto out;
2248 }
2249
2250 bf->bf_state.bfs_paprd = txctl->paprd;
2251
2252 if (txctl->paprd)
2253 bf->bf_state.bfs_paprd_timestamp = jiffies;
2254
2255 ath_set_rates(vif, sta, bf);
2256 ath_tx_send_normal(sc, txq, tid, skb);
2257
2258 out:
2259 ath_txq_unlock(sc, txq);
2260
2261 return 0;
2262 }
2263
2264 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2265 struct sk_buff *skb)
2266 {
2267 struct ath_softc *sc = hw->priv;
2268 struct ath_tx_control txctl = {
2269 .txq = sc->beacon.cabq
2270 };
2271 struct ath_tx_info info = {};
2272 struct ieee80211_hdr *hdr;
2273 struct ath_buf *bf_tail = NULL;
2274 struct ath_buf *bf;
2275 LIST_HEAD(bf_q);
2276 int duration = 0;
2277 int max_duration;
2278
2279 max_duration =
2280 sc->cur_beacon_conf.beacon_interval * 1000 *
2281 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2282
2283 do {
2284 struct ath_frame_info *fi = get_frame_info(skb);
2285
2286 if (ath_tx_prepare(hw, skb, &txctl))
2287 break;
2288
2289 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2290 if (!bf)
2291 break;
2292
2293 bf->bf_lastbf = bf;
2294 ath_set_rates(vif, NULL, bf);
2295 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2296 duration += info.rates[0].PktDuration;
2297 if (bf_tail)
2298 bf_tail->bf_next = bf;
2299
2300 list_add_tail(&bf->list, &bf_q);
2301 bf_tail = bf;
2302 skb = NULL;
2303
2304 if (duration > max_duration)
2305 break;
2306
2307 skb = ieee80211_get_buffered_bc(hw, vif);
2308 } while(skb);
2309
2310 if (skb)
2311 ieee80211_free_txskb(hw, skb);
2312
2313 if (list_empty(&bf_q))
2314 return;
2315
2316 bf = list_first_entry(&bf_q, struct ath_buf, list);
2317 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2318
2319 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2320 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2321 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2322 sizeof(*hdr), DMA_TO_DEVICE);
2323 }
2324
2325 ath_txq_lock(sc, txctl.txq);
2326 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2327 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2328 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2329 ath_txq_unlock(sc, txctl.txq);
2330 }
2331
2332 /*****************/
2333 /* TX Completion */
2334 /*****************/
2335
2336 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2337 int tx_flags, struct ath_txq *txq)
2338 {
2339 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2341 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2342 int padpos, padsize;
2343 unsigned long flags;
2344
2345 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2346
2347 if (sc->sc_ah->caldata)
2348 sc->sc_ah->caldata->paprd_packet_sent = true;
2349
2350 if (!(tx_flags & ATH_TX_ERROR))
2351 /* Frame was ACKed */
2352 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2353
2354 padpos = ieee80211_hdrlen(hdr->frame_control);
2355 padsize = padpos & 3;
2356 if (padsize && skb->len>padpos+padsize) {
2357 /*
2358 * Remove MAC header padding before giving the frame back to
2359 * mac80211.
2360 */
2361 memmove(skb->data + padsize, skb->data, padpos);
2362 skb_pull(skb, padsize);
2363 }
2364
2365 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2366 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2367 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2368 ath_dbg(common, PS,
2369 "Going back to sleep after having received TX status (0x%lx)\n",
2370 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2371 PS_WAIT_FOR_CAB |
2372 PS_WAIT_FOR_PSPOLL_DATA |
2373 PS_WAIT_FOR_TX_ACK));
2374 }
2375 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2376
2377 __skb_queue_tail(&txq->complete_q, skb);
2378 ath_txq_skb_done(sc, txq, skb);
2379 }
2380
2381 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2382 struct ath_txq *txq, struct list_head *bf_q,
2383 struct ath_tx_status *ts, int txok)
2384 {
2385 struct sk_buff *skb = bf->bf_mpdu;
2386 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2387 unsigned long flags;
2388 int tx_flags = 0;
2389
2390 if (!txok)
2391 tx_flags |= ATH_TX_ERROR;
2392
2393 if (ts->ts_status & ATH9K_TXERR_FILT)
2394 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2395
2396 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2397 bf->bf_buf_addr = 0;
2398
2399 if (bf->bf_state.bfs_paprd) {
2400 if (time_after(jiffies,
2401 bf->bf_state.bfs_paprd_timestamp +
2402 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2403 dev_kfree_skb_any(skb);
2404 else
2405 complete(&sc->paprd_complete);
2406 } else {
2407 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2408 ath_tx_complete(sc, skb, tx_flags, txq);
2409 }
2410 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2411 * accidentally reference it later.
2412 */
2413 bf->bf_mpdu = NULL;
2414
2415 /*
2416 * Return the list of ath_buf of this mpdu to free queue
2417 */
2418 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2419 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2420 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2421 }
2422
2423 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2424 struct ath_tx_status *ts, int nframes, int nbad,
2425 int txok)
2426 {
2427 struct sk_buff *skb = bf->bf_mpdu;
2428 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2429 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2430 struct ieee80211_hw *hw = sc->hw;
2431 struct ath_hw *ah = sc->sc_ah;
2432 u8 i, tx_rateindex;
2433
2434 if (txok)
2435 tx_info->status.ack_signal = ts->ts_rssi;
2436
2437 tx_rateindex = ts->ts_rateindex;
2438 WARN_ON(tx_rateindex >= hw->max_rates);
2439
2440 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2441 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2442
2443 BUG_ON(nbad > nframes);
2444 }
2445 tx_info->status.ampdu_len = nframes;
2446 tx_info->status.ampdu_ack_len = nframes - nbad;
2447
2448 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2449 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2450 /*
2451 * If an underrun error is seen assume it as an excessive
2452 * retry only if max frame trigger level has been reached
2453 * (2 KB for single stream, and 4 KB for dual stream).
2454 * Adjust the long retry as if the frame was tried
2455 * hw->max_rate_tries times to affect how rate control updates
2456 * PER for the failed rate.
2457 * In case of congestion on the bus penalizing this type of
2458 * underruns should help hardware actually transmit new frames
2459 * successfully by eventually preferring slower rates.
2460 * This itself should also alleviate congestion on the bus.
2461 */
2462 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2463 ATH9K_TX_DELIM_UNDERRUN)) &&
2464 ieee80211_is_data(hdr->frame_control) &&
2465 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2466 tx_info->status.rates[tx_rateindex].count =
2467 hw->max_rate_tries;
2468 }
2469
2470 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2471 tx_info->status.rates[i].count = 0;
2472 tx_info->status.rates[i].idx = -1;
2473 }
2474
2475 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2476 }
2477
2478 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2479 {
2480 struct ath_hw *ah = sc->sc_ah;
2481 struct ath_common *common = ath9k_hw_common(ah);
2482 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2483 struct list_head bf_head;
2484 struct ath_desc *ds;
2485 struct ath_tx_status ts;
2486 int status;
2487
2488 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2489 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2490 txq->axq_link);
2491
2492 ath_txq_lock(sc, txq);
2493 for (;;) {
2494 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2495 break;
2496
2497 if (list_empty(&txq->axq_q)) {
2498 txq->axq_link = NULL;
2499 ath_txq_schedule(sc, txq);
2500 break;
2501 }
2502 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2503
2504 /*
2505 * There is a race condition that a BH gets scheduled
2506 * after sw writes TxE and before hw re-load the last
2507 * descriptor to get the newly chained one.
2508 * Software must keep the last DONE descriptor as a
2509 * holding descriptor - software does so by marking
2510 * it with the STALE flag.
2511 */
2512 bf_held = NULL;
2513 if (bf->bf_state.stale) {
2514 bf_held = bf;
2515 if (list_is_last(&bf_held->list, &txq->axq_q))
2516 break;
2517
2518 bf = list_entry(bf_held->list.next, struct ath_buf,
2519 list);
2520 }
2521
2522 lastbf = bf->bf_lastbf;
2523 ds = lastbf->bf_desc;
2524
2525 memset(&ts, 0, sizeof(ts));
2526 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2527 if (status == -EINPROGRESS)
2528 break;
2529
2530 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2531
2532 /*
2533 * Remove ath_buf's of the same transmit unit from txq,
2534 * however leave the last descriptor back as the holding
2535 * descriptor for hw.
2536 */
2537 lastbf->bf_state.stale = true;
2538 INIT_LIST_HEAD(&bf_head);
2539 if (!list_is_singular(&lastbf->list))
2540 list_cut_position(&bf_head,
2541 &txq->axq_q, lastbf->list.prev);
2542
2543 if (bf_held) {
2544 list_del(&bf_held->list);
2545 ath_tx_return_buffer(sc, bf_held);
2546 }
2547
2548 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2549 }
2550 ath_txq_unlock_complete(sc, txq);
2551 }
2552
2553 void ath_tx_tasklet(struct ath_softc *sc)
2554 {
2555 struct ath_hw *ah = sc->sc_ah;
2556 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2557 int i;
2558
2559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2560 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2561 ath_tx_processq(sc, &sc->tx.txq[i]);
2562 }
2563 }
2564
2565 void ath_tx_edma_tasklet(struct ath_softc *sc)
2566 {
2567 struct ath_tx_status ts;
2568 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2569 struct ath_hw *ah = sc->sc_ah;
2570 struct ath_txq *txq;
2571 struct ath_buf *bf, *lastbf;
2572 struct list_head bf_head;
2573 struct list_head *fifo_list;
2574 int status;
2575
2576 for (;;) {
2577 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2578 break;
2579
2580 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2581 if (status == -EINPROGRESS)
2582 break;
2583 if (status == -EIO) {
2584 ath_dbg(common, XMIT, "Error processing tx status\n");
2585 break;
2586 }
2587
2588 /* Process beacon completions separately */
2589 if (ts.qid == sc->beacon.beaconq) {
2590 sc->beacon.tx_processed = true;
2591 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2592
2593 ath9k_csa_is_finished(sc);
2594 continue;
2595 }
2596
2597 txq = &sc->tx.txq[ts.qid];
2598
2599 ath_txq_lock(sc, txq);
2600
2601 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2602
2603 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2604 if (list_empty(fifo_list)) {
2605 ath_txq_unlock(sc, txq);
2606 return;
2607 }
2608
2609 bf = list_first_entry(fifo_list, struct ath_buf, list);
2610 if (bf->bf_state.stale) {
2611 list_del(&bf->list);
2612 ath_tx_return_buffer(sc, bf);
2613 bf = list_first_entry(fifo_list, struct ath_buf, list);
2614 }
2615
2616 lastbf = bf->bf_lastbf;
2617
2618 INIT_LIST_HEAD(&bf_head);
2619 if (list_is_last(&lastbf->list, fifo_list)) {
2620 list_splice_tail_init(fifo_list, &bf_head);
2621 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2622
2623 if (!list_empty(&txq->axq_q)) {
2624 struct list_head bf_q;
2625
2626 INIT_LIST_HEAD(&bf_q);
2627 txq->axq_link = NULL;
2628 list_splice_tail_init(&txq->axq_q, &bf_q);
2629 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2630 }
2631 } else {
2632 lastbf->bf_state.stale = true;
2633 if (bf != lastbf)
2634 list_cut_position(&bf_head, fifo_list,
2635 lastbf->list.prev);
2636 }
2637
2638 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2639 ath_txq_unlock_complete(sc, txq);
2640 }
2641 }
2642
2643 /*****************/
2644 /* Init, Cleanup */
2645 /*****************/
2646
2647 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2648 {
2649 struct ath_descdma *dd = &sc->txsdma;
2650 u8 txs_len = sc->sc_ah->caps.txs_len;
2651
2652 dd->dd_desc_len = size * txs_len;
2653 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2654 &dd->dd_desc_paddr, GFP_KERNEL);
2655 if (!dd->dd_desc)
2656 return -ENOMEM;
2657
2658 return 0;
2659 }
2660
2661 static int ath_tx_edma_init(struct ath_softc *sc)
2662 {
2663 int err;
2664
2665 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2666 if (!err)
2667 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2668 sc->txsdma.dd_desc_paddr,
2669 ATH_TXSTATUS_RING_SIZE);
2670
2671 return err;
2672 }
2673
2674 int ath_tx_init(struct ath_softc *sc, int nbufs)
2675 {
2676 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2677 int error = 0;
2678
2679 spin_lock_init(&sc->tx.txbuflock);
2680
2681 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2682 "tx", nbufs, 1, 1);
2683 if (error != 0) {
2684 ath_err(common,
2685 "Failed to allocate tx descriptors: %d\n", error);
2686 return error;
2687 }
2688
2689 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2690 "beacon", ATH_BCBUF, 1, 1);
2691 if (error != 0) {
2692 ath_err(common,
2693 "Failed to allocate beacon descriptors: %d\n", error);
2694 return error;
2695 }
2696
2697 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2698
2699 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2700 error = ath_tx_edma_init(sc);
2701
2702 return error;
2703 }
2704
2705 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2706 {
2707 struct ath_atx_tid *tid;
2708 struct ath_atx_ac *ac;
2709 int tidno, acno;
2710
2711 for (tidno = 0, tid = &an->tid[tidno];
2712 tidno < IEEE80211_NUM_TIDS;
2713 tidno++, tid++) {
2714 tid->an = an;
2715 tid->tidno = tidno;
2716 tid->seq_start = tid->seq_next = 0;
2717 tid->baw_size = WME_MAX_BA;
2718 tid->baw_head = tid->baw_tail = 0;
2719 tid->sched = false;
2720 tid->paused = false;
2721 tid->active = false;
2722 __skb_queue_head_init(&tid->buf_q);
2723 __skb_queue_head_init(&tid->retry_q);
2724 acno = TID_TO_WME_AC(tidno);
2725 tid->ac = &an->ac[acno];
2726 }
2727
2728 for (acno = 0, ac = &an->ac[acno];
2729 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2730 ac->sched = false;
2731 ac->clear_ps_filter = true;
2732 ac->txq = sc->tx.txq_map[acno];
2733 INIT_LIST_HEAD(&ac->tid_q);
2734 }
2735 }
2736
2737 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2738 {
2739 struct ath_atx_ac *ac;
2740 struct ath_atx_tid *tid;
2741 struct ath_txq *txq;
2742 int tidno;
2743
2744 for (tidno = 0, tid = &an->tid[tidno];
2745 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2746
2747 ac = tid->ac;
2748 txq = ac->txq;
2749
2750 ath_txq_lock(sc, txq);
2751
2752 if (tid->sched) {
2753 list_del(&tid->list);
2754 tid->sched = false;
2755 }
2756
2757 if (ac->sched) {
2758 list_del(&ac->list);
2759 tid->ac->sched = false;
2760 }
2761
2762 ath_tid_drain(sc, txq, tid);
2763 tid->active = false;
2764
2765 ath_txq_unlock(sc, txq);
2766 }
2767 }
Linux with added FPC-III support