drivers/net/wireless/mwifiex/sdio.h

   1 /*
   2  * Marvell Wireless LAN device driver: SDIO specific definitions
   3  *
   4  * Copyright (C) 2011, Marvell International Ltd.
   5  *
   6  * This software file (the "File") is distributed by Marvell International
   7  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
   8  * (the "License").  You may use, redistribute and/or modify this File in
   9  * accordance with the terms and conditions of the License, a copy of which
  10  * is available by writing to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13  *
  14  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  17  * this warranty disclaimer.
  18  */
  19
  20 #ifndef _MWIFIEX_SDIO_H
  21 #define _MWIFIEX_SDIO_H
  22
  23
  24 #include <linux/mmc/sdio.h>
  25 #include <linux/mmc/sdio_ids.h>
  26 #include <linux/mmc/sdio_func.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/mmc/host.h>
  29
  30 #include "main.h"
  31
  32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
  33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
  34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
  35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
  36
  37 #define BLOCK_MODE      1
  38 #define BYTE_MODE       0
  39
  40 #define REG_PORT                        0
  41
  42 #define MWIFIEX_SDIO_IO_PORT_MASK               0xfffff
  43
  44 #define MWIFIEX_SDIO_BYTE_MODE_MASK     0x80000000
  45
  46 #define SDIO_MPA_ADDR_BASE              0x1000
  47 #define CTRL_PORT                       0
  48 #define CTRL_PORT_MASK                  0x0001
  49
  50 #define CMD_PORT_UPLD_INT_MASK          (0x1U<<6)
  51 #define CMD_PORT_DNLD_INT_MASK          (0x1U<<7)
  52 #define HOST_TERM_CMD53                 (0x1U << 2)
  53 #define REG_PORT                        0
  54 #define MEM_PORT                        0x10000
  55 #define CMD_RD_LEN_0                    0xB4
  56 #define CMD_RD_LEN_1                    0xB5
  57 #define CARD_CONFIG_2_1_REG             0xCD
  58 #define CMD53_NEW_MODE                  (0x1U << 0)
  59 #define CMD_CONFIG_0                    0xB8
  60 #define CMD_PORT_RD_LEN_EN              (0x1U << 2)
  61 #define CMD_CONFIG_1                    0xB9
  62 #define CMD_PORT_AUTO_EN                (0x1U << 0)
  63 #define CMD_PORT_SLCT                   0x8000
  64 #define UP_LD_CMD_PORT_HOST_INT_STATUS  (0x40U)
  65 #define DN_LD_CMD_PORT_HOST_INT_STATUS  (0x80U)
  66
  67 #define SDIO_MP_TX_AGGR_DEF_BUF_SIZE        (8192)      /* 8K */
  68
  69 /* Multi port RX aggregation buffer size */
  70 #define SDIO_MP_RX_AGGR_DEF_BUF_SIZE        (16384)     /* 16K */
  71
  72 /* Misc. Config Register : Auto Re-enable interrupts */
  73 #define AUTO_RE_ENABLE_INT              BIT(4)
  74
  75 /* Host Control Registers */
  76 /* Host Control Registers : I/O port 0 */
  77 #define IO_PORT_0_REG                   0x78
  78 /* Host Control Registers : I/O port 1 */
  79 #define IO_PORT_1_REG                   0x79
  80 /* Host Control Registers : I/O port 2 */
  81 #define IO_PORT_2_REG                   0x7A
  82
  83 /* Host Control Registers : Configuration */
  84 #define CONFIGURATION_REG               0x00
  85 /* Host Control Registers : Host power up */
  86 #define HOST_POWER_UP                   (0x1U << 1)
  87
  88 /* Host Control Registers : Host interrupt mask */
  89 #define HOST_INT_MASK_REG               0x02
  90 /* Host Control Registers : Upload host interrupt mask */
  91 #define UP_LD_HOST_INT_MASK             (0x1U)
  92 /* Host Control Registers : Download host interrupt mask */
  93 #define DN_LD_HOST_INT_MASK             (0x2U)
  94
  95 /* Host Control Registers : Host interrupt status */
  96 #define HOST_INTSTATUS_REG              0x03
  97 /* Host Control Registers : Upload host interrupt status */
  98 #define UP_LD_HOST_INT_STATUS           (0x1U)
  99 /* Host Control Registers : Download host interrupt status */
 100 #define DN_LD_HOST_INT_STATUS           (0x2U)
 101
 102 /* Host Control Registers : Host interrupt RSR */
 103 #define HOST_INT_RSR_REG                0x01
 104
 105 /* Host Control Registers : Host interrupt status */
 106 #define HOST_INT_STATUS_REG             0x28
 107
 108 /* Card Control Registers : Card I/O ready */
 109 #define CARD_IO_READY                   (0x1U << 3)
 110 /* Card Control Registers : Download card ready */
 111 #define DN_LD_CARD_RDY                  (0x1U << 0)
 112
 113 /* Max retry number of CMD53 write */
 114 #define MAX_WRITE_IOMEM_RETRY           2
 115
 116 /* SDIO Tx aggregation in progress ? */
 117 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
 118
 119 /* SDIO Tx aggregation buffer room for next packet ? */
 120 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)        \
 121                                                 <= a->mpa_tx.buf_size)
 122
 123 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
 124 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {              \
 125         memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],                      \
 126                         payload, pkt_len);                              \
 127         a->mpa_tx.buf_len += pkt_len;                                   \
 128         if (!a->mpa_tx.pkt_cnt)                                         \
 129                 a->mpa_tx.start_port = port;                            \
 130         if (a->mpa_tx.start_port <= port)                               \
 131                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));            \
 132         else                                                            \
 133                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+            \
 134                                                 (a->max_ports - \
 135                                                 a->mp_end_port)));      \
 136         a->mpa_tx.pkt_cnt++;                                            \
 137 } while (0)
 138
 139 /* SDIO Tx aggregation limit ? */
 140 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 141                         (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
 142
 143 /* Reset SDIO Tx aggregation buffer parameters */
 144 #define MP_TX_AGGR_BUF_RESET(a) do {                                    \
 145         a->mpa_tx.pkt_cnt = 0;                                          \
 146         a->mpa_tx.buf_len = 0;                                          \
 147         a->mpa_tx.ports = 0;                                            \
 148         a->mpa_tx.start_port = 0;                                       \
 149 } while (0)
 150
 151 /* SDIO Rx aggregation limit ? */
 152 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 153                         (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
 154
 155 /* SDIO Rx aggregation in progress ? */
 156 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
 157
 158 /* SDIO Rx aggregation buffer room for next packet ? */
 159 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)                              \
 160                         ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
 161
 162 /* Reset SDIO Rx aggregation buffer parameters */
 163 #define MP_RX_AGGR_BUF_RESET(a) do {                                    \
 164         a->mpa_rx.pkt_cnt = 0;                                          \
 165         a->mpa_rx.buf_len = 0;                                          \
 166         a->mpa_rx.ports = 0;                                            \
 167         a->mpa_rx.start_port = 0;                                       \
 168 } while (0)
 169
 170 /* data structure for SDIO MPA TX */
 171 struct mwifiex_sdio_mpa_tx {
 172         /* multiport tx aggregation buffer pointer */
 173         u8 *buf;
 174         u32 buf_len;
 175         u32 pkt_cnt;
 176         u32 ports;
 177         u16 start_port;
 178         u8 enabled;
 179         u32 buf_size;
 180         u32 pkt_aggr_limit;
 181 };
 182
 183 struct mwifiex_sdio_mpa_rx {
 184         u8 *buf;
 185         u32 buf_len;
 186         u32 pkt_cnt;
 187         u32 ports;
 188         u16 start_port;
 189
 190         struct sk_buff **skb_arr;
 191         u32 *len_arr;
 192
 193         u8 enabled;
 194         u32 buf_size;
 195         u32 pkt_aggr_limit;
 196 };
 197
 198 int mwifiex_bus_register(void);
 199 void mwifiex_bus_unregister(void);
 200
 201 struct mwifiex_sdio_card_reg {
 202         u8 start_rd_port;
 203         u8 start_wr_port;
 204         u8 base_0_reg;
 205         u8 base_1_reg;
 206         u8 poll_reg;
 207         u8 host_int_enable;
 208         u8 status_reg_0;
 209         u8 status_reg_1;
 210         u8 sdio_int_mask;
 211         u32 data_port_mask;
 212         u8 max_mp_regs;
 213         u8 rd_bitmap_l;
 214         u8 rd_bitmap_u;
 215         u8 rd_bitmap_1l;
 216         u8 rd_bitmap_1u;
 217         u8 wr_bitmap_l;
 218         u8 wr_bitmap_u;
 219         u8 wr_bitmap_1l;
 220         u8 wr_bitmap_1u;
 221         u8 rd_len_p0_l;
 222         u8 rd_len_p0_u;
 223         u8 card_misc_cfg_reg;
 224 };
 225
 226 struct sdio_mmc_card {
 227         struct sdio_func *func;
 228         struct mwifiex_adapter *adapter;
 229
 230         const char *firmware;
 231         const struct mwifiex_sdio_card_reg *reg;
 232         u8 max_ports;
 233         u8 mp_agg_pkt_limit;
 234         bool supports_sdio_new_mode;
 235         bool has_control_mask;
 236
 237         u32 mp_rd_bitmap;
 238         u32 mp_wr_bitmap;
 239
 240         u16 mp_end_port;
 241         u32 mp_data_port_mask;
 242
 243         u8 curr_rd_port;
 244         u8 curr_wr_port;
 245
 246         u8 *mp_regs;
 247
 248         struct mwifiex_sdio_mpa_tx mpa_tx;
 249         struct mwifiex_sdio_mpa_rx mpa_rx;
 250 };
 251
 252 struct mwifiex_sdio_device {
 253         const char *firmware;
 254         const struct mwifiex_sdio_card_reg *reg;
 255         u8 max_ports;
 256         u8 mp_agg_pkt_limit;
 257         bool supports_sdio_new_mode;
 258         bool has_control_mask;
 259 };
 260
 261 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
 262         .start_rd_port = 1,
 263         .start_wr_port = 1,
 264         .base_0_reg = 0x0040,
 265         .base_1_reg = 0x0041,
 266         .poll_reg = 0x30,
 267         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
 268         .status_reg_0 = 0x60,
 269         .status_reg_1 = 0x61,
 270         .sdio_int_mask = 0x3f,
 271         .data_port_mask = 0x0000fffe,
 272         .max_mp_regs = 64,
 273         .rd_bitmap_l = 0x04,
 274         .rd_bitmap_u = 0x05,
 275         .wr_bitmap_l = 0x06,
 276         .wr_bitmap_u = 0x07,
 277         .rd_len_p0_l = 0x08,
 278         .rd_len_p0_u = 0x09,
 279         .card_misc_cfg_reg = 0x6c,
 280 };
 281
 282 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
 283         .start_rd_port = 0,
 284         .start_wr_port = 0,
 285         .base_0_reg = 0x60,
 286         .base_1_reg = 0x61,
 287         .poll_reg = 0x50,
 288         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
 289                         CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
 290         .status_reg_0 = 0xc0,
 291         .status_reg_1 = 0xc1,
 292         .sdio_int_mask = 0xff,
 293         .data_port_mask = 0xffffffff,
 294         .max_mp_regs = 184,
 295         .rd_bitmap_l = 0x04,
 296         .rd_bitmap_u = 0x05,
 297         .rd_bitmap_1l = 0x06,
 298         .rd_bitmap_1u = 0x07,
 299         .wr_bitmap_l = 0x08,
 300         .wr_bitmap_u = 0x09,
 301         .wr_bitmap_1l = 0x0a,
 302         .wr_bitmap_1u = 0x0b,
 303         .rd_len_p0_l = 0x0c,
 304         .rd_len_p0_u = 0x0d,
 305         .card_misc_cfg_reg = 0xcc,
 306 };
 307
 308 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
 309         .firmware = SD8786_DEFAULT_FW_NAME,
 310         .reg = &mwifiex_reg_sd87xx,
 311         .max_ports = 16,
 312         .mp_agg_pkt_limit = 8,
 313         .supports_sdio_new_mode = false,
 314         .has_control_mask = true,
 315 };
 316
 317 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
 318         .firmware = SD8787_DEFAULT_FW_NAME,
 319         .reg = &mwifiex_reg_sd87xx,
 320         .max_ports = 16,
 321         .mp_agg_pkt_limit = 8,
 322         .supports_sdio_new_mode = false,
 323         .has_control_mask = true,
 324 };
 325
 326 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
 327         .firmware = SD8797_DEFAULT_FW_NAME,
 328         .reg = &mwifiex_reg_sd87xx,
 329         .max_ports = 16,
 330         .mp_agg_pkt_limit = 8,
 331         .supports_sdio_new_mode = false,
 332         .has_control_mask = true,
 333 };
 334
 335 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
 336         .firmware = SD8897_DEFAULT_FW_NAME,
 337         .reg = &mwifiex_reg_sd8897,
 338         .max_ports = 32,
 339         .mp_agg_pkt_limit = 16,
 340         .supports_sdio_new_mode = true,
 341         .has_control_mask = false,
 342 };
 343
 344 /*
 345  * .cmdrsp_complete handler
 346  */
 347 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
 348                                                struct sk_buff *skb)
 349 {
 350         dev_kfree_skb_any(skb);
 351         return 0;
 352 }
 353
 354 /*
 355  * .event_complete handler
 356  */
 357 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
 358                                               struct sk_buff *skb)
 359 {
 360         dev_kfree_skb_any(skb);
 361         return 0;
 362 }
 363
 364 static inline bool
 365 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 366 {
 367         u8 tmp;
 368
 369         if (card->curr_rd_port < card->mpa_rx.start_port) {
 370                 if (card->supports_sdio_new_mode)
 371                         tmp = card->mp_end_port >> 1;
 372                 else
 373                         tmp = card->mp_agg_pkt_limit;
 374
 375                 if (((card->max_ports - card->mpa_rx.start_port) +
 376                     card->curr_rd_port) >= tmp)
 377                         return true;
 378         }
 379
 380         if (!card->supports_sdio_new_mode)
 381                 return false;
 382
 383         if ((card->curr_rd_port - card->mpa_rx.start_port) >=
 384             (card->mp_end_port >> 1))
 385                 return true;
 386
 387         return false;
 388 }
 389
 390 static inline bool
 391 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 392 {
 393         u16 tmp;
 394
 395         if (card->curr_wr_port < card->mpa_tx.start_port) {
 396                 if (card->supports_sdio_new_mode)
 397                         tmp = card->mp_end_port >> 1;
 398                 else
 399                         tmp = card->mp_agg_pkt_limit;
 400
 401                 if (((card->max_ports - card->mpa_tx.start_port) +
 402                     card->curr_wr_port) >= tmp)
 403                         return true;
 404         }
 405
 406         if (!card->supports_sdio_new_mode)
 407                 return false;
 408
 409         if ((card->curr_wr_port - card->mpa_tx.start_port) >=
 410             (card->mp_end_port >> 1))
 411                 return true;
 412
 413         return false;
 414 }
 415
 416 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
 417 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
 418                                     struct sk_buff *skb, u8 port)
 419 {
 420         card->mpa_rx.buf_len += skb->len;
 421
 422         if (!card->mpa_rx.pkt_cnt)
 423                 card->mpa_rx.start_port = port;
 424
 425         if (card->supports_sdio_new_mode) {
 426                 card->mpa_rx.ports |= (1 << port);
 427         } else {
 428                 if (card->mpa_rx.start_port <= port)
 429                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
 430                 else
 431                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
 432         }
 433         card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
 434         card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
 435         card->mpa_rx.pkt_cnt++;
 436 }
 437 #endif /* _MWIFIEX_SDIO_H */