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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
blob446eadeaaef675bd11bd2e795aada23db6241dc3
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
225 [EEPROM_CHIP_ID] = 0x0000,
226 [EEPROM_VERSION] = 0x0001,
227 [EEPROM_MAC_ADDR_0] = 0x0002,
228 [EEPROM_MAC_ADDR_1] = 0x0003,
229 [EEPROM_MAC_ADDR_2] = 0x0004,
230 [EEPROM_NIC_CONF0] = 0x001a,
231 [EEPROM_NIC_CONF1] = 0x001b,
232 [EEPROM_FREQ] = 0x001d,
233 [EEPROM_LED_AG_CONF] = 0x001e,
234 [EEPROM_LED_ACT_CONF] = 0x001f,
235 [EEPROM_LED_POLARITY] = 0x0020,
236 [EEPROM_NIC_CONF2] = 0x0021,
237 [EEPROM_LNA] = 0x0022,
238 [EEPROM_RSSI_BG] = 0x0023,
239 [EEPROM_RSSI_BG2] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A] = 0x0025,
242 [EEPROM_RSSI_A2] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
245 [EEPROM_TXPOWER_DELTA] = 0x0028,
246 [EEPROM_TXPOWER_BG1] = 0x0029,
247 [EEPROM_TXPOWER_BG2] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
253 [EEPROM_TXPOWER_A1] = 0x003c,
254 [EEPROM_TXPOWER_A2] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE] = 0x006f,
261 [EEPROM_BBP_START] = 0x0078,
262 };
263
264 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
265 [EEPROM_CHIP_ID] = 0x0000,
266 [EEPROM_VERSION] = 0x0001,
267 [EEPROM_MAC_ADDR_0] = 0x0002,
268 [EEPROM_MAC_ADDR_1] = 0x0003,
269 [EEPROM_MAC_ADDR_2] = 0x0004,
270 [EEPROM_NIC_CONF0] = 0x001a,
271 [EEPROM_NIC_CONF1] = 0x001b,
272 [EEPROM_NIC_CONF2] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
274 [EEPROM_FREQ] = 0x0022,
275 [EEPROM_LED_AG_CONF] = 0x0023,
276 [EEPROM_LED_ACT_CONF] = 0x0024,
277 [EEPROM_LED_POLARITY] = 0x0025,
278 [EEPROM_LNA] = 0x0026,
279 [EEPROM_EXT_LNA2] = 0x0027,
280 [EEPROM_RSSI_BG] = 0x0028,
281 [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A] = 0x002a,
285 [EEPROM_RSSI_A2] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1] = 0x0030,
288 [EEPROM_TXPOWER_BG2] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
295 [EEPROM_TXPOWER_A1] = 0x004b,
296 [EEPROM_TXPOWER_A2] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
304 };
305
306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
307 const enum rt2800_eeprom_word word)
308 {
309 const unsigned int *map;
310 unsigned int index;
311
312 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev->hw->wiphy), word))
315 return 0;
316
317 if (rt2x00_rt(rt2x00dev, RT3593))
318 map = rt2800_eeprom_map_ext;
319 else
320 map = rt2800_eeprom_map;
321
322 index = map[word];
323
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
328 * actual chipset.
329 */
330 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev->hw->wiphy), word);
333
334 return index;
335 }
336
337 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
338 const enum rt2800_eeprom_word word)
339 {
340 unsigned int index;
341
342 index = rt2800_eeprom_word_index(rt2x00dev, word);
343 return rt2x00_eeprom_addr(rt2x00dev, index);
344 }
345
346 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
347 const enum rt2800_eeprom_word word, u16 *data)
348 {
349 unsigned int index;
350
351 index = rt2800_eeprom_word_index(rt2x00dev, word);
352 rt2x00_eeprom_read(rt2x00dev, index, data);
353 }
354
355 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
356 const enum rt2800_eeprom_word word, u16 data)
357 {
358 unsigned int index;
359
360 index = rt2800_eeprom_word_index(rt2x00dev, word);
361 rt2x00_eeprom_write(rt2x00dev, index, data);
362 }
363
364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
365 const enum rt2800_eeprom_word array,
366 unsigned int offset,
367 u16 *data)
368 {
369 unsigned int index;
370
371 index = rt2800_eeprom_word_index(rt2x00dev, array);
372 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
373 }
374
375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
376 {
377 u32 reg;
378 int i, count;
379
380 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
381 if (rt2x00_get_field32(reg, WLAN_EN))
382 return 0;
383
384 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
385 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
386 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
387 rt2x00_set_field32(&reg, WLAN_EN, 1);
388 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
389
390 udelay(REGISTER_BUSY_DELAY);
391
392 count = 0;
393 do {
394 /*
395 * Check PLL_LD & XTAL_RDY.
396 */
397 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
398 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
399 if (rt2x00_get_field32(reg, PLL_LD) &&
400 rt2x00_get_field32(reg, XTAL_RDY))
401 break;
402 udelay(REGISTER_BUSY_DELAY);
403 }
404
405 if (i >= REGISTER_BUSY_COUNT) {
406
407 if (count >= 10)
408 return -EIO;
409
410 rt2800_register_write(rt2x00dev, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY);
412 rt2800_register_write(rt2x00dev, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY);
414 rt2800_register_write(rt2x00dev, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY);
416 count++;
417 } else {
418 count = 0;
419 }
420
421 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
422 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
423 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
424 rt2x00_set_field32(&reg, WLAN_RESET, 1);
425 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
426 udelay(10);
427 rt2x00_set_field32(&reg, WLAN_RESET, 0);
428 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
429 udelay(10);
430 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
431 } while (count != 0);
432
433 return 0;
434 }
435
436 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
437 const u8 command, const u8 token,
438 const u8 arg0, const u8 arg1)
439 {
440 u32 reg;
441
442 /*
443 * SOC devices don't support MCU requests.
444 */
445 if (rt2x00_is_soc(rt2x00dev))
446 return;
447
448 mutex_lock(&rt2x00dev->csr_mutex);
449
450 /*
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
453 */
454 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
455 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
456 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
457 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
458 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
459 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
460
461 reg = 0;
462 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
463 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
464 }
465
466 mutex_unlock(&rt2x00dev->csr_mutex);
467 }
468 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
469
470 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
471 {
472 unsigned int i = 0;
473 u32 reg;
474
475 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
477 if (reg && reg != ~0)
478 return 0;
479 msleep(1);
480 }
481
482 rt2x00_err(rt2x00dev, "Unstable hardware\n");
483 return -EBUSY;
484 }
485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
486
487 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
488 {
489 unsigned int i;
490 u32 reg;
491
492 /*
493 * Some devices are really slow to respond here. Wait a whole second
494 * before timing out.
495 */
496 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
497 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
498 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
499 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
500 return 0;
501
502 msleep(10);
503 }
504
505 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
506 return -EACCES;
507 }
508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
509
510 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
511 {
512 u32 reg;
513
514 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
515 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
516 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
517 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
518 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
519 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
520 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
521 }
522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
523
524 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
525 unsigned short *txwi_size,
526 unsigned short *rxwi_size)
527 {
528 switch (rt2x00dev->chip.rt) {
529 case RT3593:
530 *txwi_size = TXWI_DESC_SIZE_4WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
532 break;
533
534 case RT5592:
535 *txwi_size = TXWI_DESC_SIZE_5WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
537 break;
538
539 default:
540 *txwi_size = TXWI_DESC_SIZE_4WORDS;
541 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
542 break;
543 }
544 }
545 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
546
547 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
548 {
549 u16 fw_crc;
550 u16 crc;
551
552 /*
553 * The last 2 bytes in the firmware array are the crc checksum itself,
554 * this means that we should never pass those 2 bytes to the crc
555 * algorithm.
556 */
557 fw_crc = (data[len - 2] << 8 | data[len - 1]);
558
559 /*
560 * Use the crc ccitt algorithm.
561 * This will return the same value as the legacy driver which
562 * used bit ordering reversion on the both the firmware bytes
563 * before input input as well as on the final output.
564 * Obviously using crc ccitt directly is much more efficient.
565 */
566 crc = crc_ccitt(~0, data, len - 2);
567
568 /*
569 * There is a small difference between the crc-itu-t + bitrev and
570 * the crc-ccitt crc calculation. In the latter method the 2 bytes
571 * will be swapped, use swab16 to convert the crc to the correct
572 * value.
573 */
574 crc = swab16(crc);
575
576 return fw_crc == crc;
577 }
578
579 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
580 const u8 *data, const size_t len)
581 {
582 size_t offset = 0;
583 size_t fw_len;
584 bool multiple;
585
586 /*
587 * PCI(e) & SOC devices require firmware with a length
588 * of 8kb. USB devices require firmware files with a length
589 * of 4kb. Certain USB chipsets however require different firmware,
590 * which Ralink only provides attached to the original firmware
591 * file. Thus for USB devices, firmware files have a length
592 * which is a multiple of 4kb. The firmware for rt3290 chip also
593 * have a length which is a multiple of 4kb.
594 */
595 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
596 fw_len = 4096;
597 else
598 fw_len = 8192;
599
600 multiple = true;
601 /*
602 * Validate the firmware length
603 */
604 if (len != fw_len && (!multiple || (len % fw_len) != 0))
605 return FW_BAD_LENGTH;
606
607 /*
608 * Check if the chipset requires one of the upper parts
609 * of the firmware.
610 */
611 if (rt2x00_is_usb(rt2x00dev) &&
612 !rt2x00_rt(rt2x00dev, RT2860) &&
613 !rt2x00_rt(rt2x00dev, RT2872) &&
614 !rt2x00_rt(rt2x00dev, RT3070) &&
615 ((len / fw_len) == 1))
616 return FW_BAD_VERSION;
617
618 /*
619 * 8kb firmware files must be checked as if it were
620 * 2 separate firmware files.
621 */
622 while (offset < len) {
623 if (!rt2800_check_firmware_crc(data + offset, fw_len))
624 return FW_BAD_CRC;
625
626 offset += fw_len;
627 }
628
629 return FW_OK;
630 }
631 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
632
633 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
634 const u8 *data, const size_t len)
635 {
636 unsigned int i;
637 u32 reg;
638 int retval;
639
640 if (rt2x00_rt(rt2x00dev, RT3290)) {
641 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
642 if (retval)
643 return -EBUSY;
644 }
645
646 /*
647 * If driver doesn't wake up firmware here,
648 * rt2800_load_firmware will hang forever when interface is up again.
649 */
650 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
651
652 /*
653 * Wait for stable hardware.
654 */
655 if (rt2800_wait_csr_ready(rt2x00dev))
656 return -EBUSY;
657
658 if (rt2x00_is_pci(rt2x00dev)) {
659 if (rt2x00_rt(rt2x00dev, RT3290) ||
660 rt2x00_rt(rt2x00dev, RT3572) ||
661 rt2x00_rt(rt2x00dev, RT5390) ||
662 rt2x00_rt(rt2x00dev, RT5392)) {
663 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
664 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
665 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
666 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
667 }
668 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
669 }
670
671 rt2800_disable_wpdma(rt2x00dev);
672
673 /*
674 * Write firmware to the device.
675 */
676 rt2800_drv_write_firmware(rt2x00dev, data, len);
677
678 /*
679 * Wait for device to stabilize.
680 */
681 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
682 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
683 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
684 break;
685 msleep(1);
686 }
687
688 if (i == REGISTER_BUSY_COUNT) {
689 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
690 return -EBUSY;
691 }
692
693 /*
694 * Disable DMA, will be reenabled later when enabling
695 * the radio.
696 */
697 rt2800_disable_wpdma(rt2x00dev);
698
699 /*
700 * Initialize firmware.
701 */
702 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
703 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
704 if (rt2x00_is_usb(rt2x00dev)) {
705 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
706 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
707 }
708 msleep(1);
709
710 return 0;
711 }
712 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
713
714 void rt2800_write_tx_data(struct queue_entry *entry,
715 struct txentry_desc *txdesc)
716 {
717 __le32 *txwi = rt2800_drv_get_txwi(entry);
718 u32 word;
719 int i;
720
721 /*
722 * Initialize TX Info descriptor
723 */
724 rt2x00_desc_read(txwi, 0, &word);
725 rt2x00_set_field32(&word, TXWI_W0_FRAG,
726 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
728 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
729 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
730 rt2x00_set_field32(&word, TXWI_W0_TS,
731 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
732 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
733 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
734 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
735 txdesc->u.ht.mpdu_density);
736 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
737 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
738 rt2x00_set_field32(&word, TXWI_W0_BW,
739 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
740 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
741 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
742 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
743 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
744 rt2x00_desc_write(txwi, 0, word);
745
746 rt2x00_desc_read(txwi, 1, &word);
747 rt2x00_set_field32(&word, TXWI_W1_ACK,
748 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
749 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
750 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
751 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
752 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
753 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
754 txdesc->key_idx : txdesc->u.ht.wcid);
755 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
756 txdesc->length);
757 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
758 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
759 rt2x00_desc_write(txwi, 1, word);
760
761 /*
762 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
763 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
764 * When TXD_W3_WIV is set to 1 it will use the IV data
765 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
766 * crypto entry in the registers should be used to encrypt the frame.
767 *
768 * Nulify all remaining words as well, we don't know how to program them.
769 */
770 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
771 _rt2x00_desc_write(txwi, i, 0);
772 }
773 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
774
775 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
776 {
777 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
778 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
779 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
780 u16 eeprom;
781 u8 offset0;
782 u8 offset1;
783 u8 offset2;
784
785 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
786 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
787 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
788 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
789 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
790 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
791 } else {
792 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
793 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
794 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
795 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
796 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
797 }
798
799 /*
800 * Convert the value from the descriptor into the RSSI value
801 * If the value in the descriptor is 0, it is considered invalid
802 * and the default (extremely low) rssi value is assumed
803 */
804 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
805 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
806 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
807
808 /*
809 * mac80211 only accepts a single RSSI value. Calculating the
810 * average doesn't deliver a fair answer either since -60:-60 would
811 * be considered equally good as -50:-70 while the second is the one
812 * which gives less energy...
813 */
814 rssi0 = max(rssi0, rssi1);
815 return (int)max(rssi0, rssi2);
816 }
817
818 void rt2800_process_rxwi(struct queue_entry *entry,
819 struct rxdone_entry_desc *rxdesc)
820 {
821 __le32 *rxwi = (__le32 *) entry->skb->data;
822 u32 word;
823
824 rt2x00_desc_read(rxwi, 0, &word);
825
826 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
827 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
828
829 rt2x00_desc_read(rxwi, 1, &word);
830
831 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
832 rxdesc->flags |= RX_FLAG_SHORT_GI;
833
834 if (rt2x00_get_field32(word, RXWI_W1_BW))
835 rxdesc->flags |= RX_FLAG_40MHZ;
836
837 /*
838 * Detect RX rate, always use MCS as signal type.
839 */
840 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
841 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
842 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
843
844 /*
845 * Mask of 0x8 bit to remove the short preamble flag.
846 */
847 if (rxdesc->rate_mode == RATE_MODE_CCK)
848 rxdesc->signal &= ~0x8;
849
850 rt2x00_desc_read(rxwi, 2, &word);
851
852 /*
853 * Convert descriptor AGC value to RSSI value.
854 */
855 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
856 /*
857 * Remove RXWI descriptor from start of the buffer.
858 */
859 skb_pull(entry->skb, entry->queue->winfo_size);
860 }
861 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
862
863 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
864 {
865 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
866 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
867 struct txdone_entry_desc txdesc;
868 u32 word;
869 u16 mcs, real_mcs;
870 int aggr, ampdu;
871
872 /*
873 * Obtain the status about this packet.
874 */
875 txdesc.flags = 0;
876 rt2x00_desc_read(txwi, 0, &word);
877
878 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
879 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
880
881 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
882 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
883
884 /*
885 * If a frame was meant to be sent as a single non-aggregated MPDU
886 * but ended up in an aggregate the used tx rate doesn't correlate
887 * with the one specified in the TXWI as the whole aggregate is sent
888 * with the same rate.
889 *
890 * For example: two frames are sent to rt2x00, the first one sets
891 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
892 * and requests MCS15. If the hw aggregates both frames into one
893 * AMDPU the tx status for both frames will contain MCS7 although
894 * the frame was sent successfully.
895 *
896 * Hence, replace the requested rate with the real tx rate to not
897 * confuse the rate control algortihm by providing clearly wrong
898 * data.
899 */
900 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
901 skbdesc->tx_rate_idx = real_mcs;
902 mcs = real_mcs;
903 }
904
905 if (aggr == 1 || ampdu == 1)
906 __set_bit(TXDONE_AMPDU, &txdesc.flags);
907
908 /*
909 * Ralink has a retry mechanism using a global fallback
910 * table. We setup this fallback table to try the immediate
911 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
912 * always contains the MCS used for the last transmission, be
913 * it successful or not.
914 */
915 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
916 /*
917 * Transmission succeeded. The number of retries is
918 * mcs - real_mcs
919 */
920 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
921 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
922 } else {
923 /*
924 * Transmission failed. The number of retries is
925 * always 7 in this case (for a total number of 8
926 * frames sent).
927 */
928 __set_bit(TXDONE_FAILURE, &txdesc.flags);
929 txdesc.retry = rt2x00dev->long_retry;
930 }
931
932 /*
933 * the frame was retried at least once
934 * -> hw used fallback rates
935 */
936 if (txdesc.retry)
937 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
938
939 rt2x00lib_txdone(entry, &txdesc);
940 }
941 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
942
943 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
944 unsigned int index)
945 {
946 return HW_BEACON_BASE(index);
947 }
948
949 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
950 unsigned int index)
951 {
952 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
953 }
954
955 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
956 {
957 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
958 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
959 unsigned int beacon_base;
960 unsigned int padding_len;
961 u32 orig_reg, reg;
962 const int txwi_desc_size = entry->queue->winfo_size;
963
964 /*
965 * Disable beaconing while we are reloading the beacon data,
966 * otherwise we might be sending out invalid data.
967 */
968 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
969 orig_reg = reg;
970 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
971 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
972
973 /*
974 * Add space for the TXWI in front of the skb.
975 */
976 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
977
978 /*
979 * Register descriptor details in skb frame descriptor.
980 */
981 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
982 skbdesc->desc = entry->skb->data;
983 skbdesc->desc_len = txwi_desc_size;
984
985 /*
986 * Add the TXWI for the beacon to the skb.
987 */
988 rt2800_write_tx_data(entry, txdesc);
989
990 /*
991 * Dump beacon to userspace through debugfs.
992 */
993 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
994
995 /*
996 * Write entire beacon with TXWI and padding to register.
997 */
998 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
999 if (padding_len && skb_pad(entry->skb, padding_len)) {
1000 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1001 /* skb freed by skb_pad() on failure */
1002 entry->skb = NULL;
1003 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1004 return;
1005 }
1006
1007 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1008
1009 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1010 entry->skb->len + padding_len);
1011
1012 /*
1013 * Enable beaconing again.
1014 */
1015 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1016 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1017
1018 /*
1019 * Clean up beacon skb.
1020 */
1021 dev_kfree_skb_any(entry->skb);
1022 entry->skb = NULL;
1023 }
1024 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1025
1026 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1027 unsigned int index)
1028 {
1029 int i;
1030 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1031 unsigned int beacon_base;
1032
1033 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1034
1035 /*
1036 * For the Beacon base registers we only need to clear
1037 * the whole TXWI which (when set to 0) will invalidate
1038 * the entire beacon.
1039 */
1040 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1041 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1042 }
1043
1044 void rt2800_clear_beacon(struct queue_entry *entry)
1045 {
1046 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1047 u32 reg;
1048
1049 /*
1050 * Disable beaconing while we are reloading the beacon data,
1051 * otherwise we might be sending out invalid data.
1052 */
1053 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1054 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1055 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1056
1057 /*
1058 * Clear beacon.
1059 */
1060 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1061
1062 /*
1063 * Enabled beaconing again.
1064 */
1065 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1066 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1067 }
1068 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1069
1070 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1071 const struct rt2x00debug rt2800_rt2x00debug = {
1072 .owner = THIS_MODULE,
1073 .csr = {
1074 .read = rt2800_register_read,
1075 .write = rt2800_register_write,
1076 .flags = RT2X00DEBUGFS_OFFSET,
1077 .word_base = CSR_REG_BASE,
1078 .word_size = sizeof(u32),
1079 .word_count = CSR_REG_SIZE / sizeof(u32),
1080 },
1081 .eeprom = {
1082 /* NOTE: The local EEPROM access functions can't
1083 * be used here, use the generic versions instead.
1084 */
1085 .read = rt2x00_eeprom_read,
1086 .write = rt2x00_eeprom_write,
1087 .word_base = EEPROM_BASE,
1088 .word_size = sizeof(u16),
1089 .word_count = EEPROM_SIZE / sizeof(u16),
1090 },
1091 .bbp = {
1092 .read = rt2800_bbp_read,
1093 .write = rt2800_bbp_write,
1094 .word_base = BBP_BASE,
1095 .word_size = sizeof(u8),
1096 .word_count = BBP_SIZE / sizeof(u8),
1097 },
1098 .rf = {
1099 .read = rt2x00_rf_read,
1100 .write = rt2800_rf_write,
1101 .word_base = RF_BASE,
1102 .word_size = sizeof(u32),
1103 .word_count = RF_SIZE / sizeof(u32),
1104 },
1105 .rfcsr = {
1106 .read = rt2800_rfcsr_read,
1107 .write = rt2800_rfcsr_write,
1108 .word_base = RFCSR_BASE,
1109 .word_size = sizeof(u8),
1110 .word_count = RFCSR_SIZE / sizeof(u8),
1111 },
1112 };
1113 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1114 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1115
1116 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1117 {
1118 u32 reg;
1119
1120 if (rt2x00_rt(rt2x00dev, RT3290)) {
1121 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1122 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1123 } else {
1124 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1125 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1126 }
1127 }
1128 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1129
1130 #ifdef CONFIG_RT2X00_LIB_LEDS
1131 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1132 enum led_brightness brightness)
1133 {
1134 struct rt2x00_led *led =
1135 container_of(led_cdev, struct rt2x00_led, led_dev);
1136 unsigned int enabled = brightness != LED_OFF;
1137 unsigned int bg_mode =
1138 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1139 unsigned int polarity =
1140 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1141 EEPROM_FREQ_LED_POLARITY);
1142 unsigned int ledmode =
1143 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1144 EEPROM_FREQ_LED_MODE);
1145 u32 reg;
1146
1147 /* Check for SoC (SOC devices don't support MCU requests) */
1148 if (rt2x00_is_soc(led->rt2x00dev)) {
1149 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1150
1151 /* Set LED Polarity */
1152 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1153
1154 /* Set LED Mode */
1155 if (led->type == LED_TYPE_RADIO) {
1156 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1157 enabled ? 3 : 0);
1158 } else if (led->type == LED_TYPE_ASSOC) {
1159 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1160 enabled ? 3 : 0);
1161 } else if (led->type == LED_TYPE_QUALITY) {
1162 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1163 enabled ? 3 : 0);
1164 }
1165
1166 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1167
1168 } else {
1169 if (led->type == LED_TYPE_RADIO) {
1170 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1171 enabled ? 0x20 : 0);
1172 } else if (led->type == LED_TYPE_ASSOC) {
1173 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1174 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1175 } else if (led->type == LED_TYPE_QUALITY) {
1176 /*
1177 * The brightness is divided into 6 levels (0 - 5),
1178 * The specs tell us the following levels:
1179 * 0, 1 ,3, 7, 15, 31
1180 * to determine the level in a simple way we can simply
1181 * work with bitshifting:
1182 * (1 << level) - 1
1183 */
1184 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1185 (1 << brightness / (LED_FULL / 6)) - 1,
1186 polarity);
1187 }
1188 }
1189 }
1190
1191 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1192 struct rt2x00_led *led, enum led_type type)
1193 {
1194 led->rt2x00dev = rt2x00dev;
1195 led->type = type;
1196 led->led_dev.brightness_set = rt2800_brightness_set;
1197 led->flags = LED_INITIALIZED;
1198 }
1199 #endif /* CONFIG_RT2X00_LIB_LEDS */
1200
1201 /*
1202 * Configuration handlers.
1203 */
1204 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1205 const u8 *address,
1206 int wcid)
1207 {
1208 struct mac_wcid_entry wcid_entry;
1209 u32 offset;
1210
1211 offset = MAC_WCID_ENTRY(wcid);
1212
1213 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1214 if (address)
1215 memcpy(wcid_entry.mac, address, ETH_ALEN);
1216
1217 rt2800_register_multiwrite(rt2x00dev, offset,
1218 &wcid_entry, sizeof(wcid_entry));
1219 }
1220
1221 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1222 {
1223 u32 offset;
1224 offset = MAC_WCID_ATTR_ENTRY(wcid);
1225 rt2800_register_write(rt2x00dev, offset, 0);
1226 }
1227
1228 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1229 int wcid, u32 bssidx)
1230 {
1231 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1232 u32 reg;
1233
1234 /*
1235 * The BSS Idx numbers is split in a main value of 3 bits,
1236 * and a extended field for adding one additional bit to the value.
1237 */
1238 rt2800_register_read(rt2x00dev, offset, &reg);
1239 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1240 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1241 (bssidx & 0x8) >> 3);
1242 rt2800_register_write(rt2x00dev, offset, reg);
1243 }
1244
1245 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1246 struct rt2x00lib_crypto *crypto,
1247 struct ieee80211_key_conf *key)
1248 {
1249 struct mac_iveiv_entry iveiv_entry;
1250 u32 offset;
1251 u32 reg;
1252
1253 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1254
1255 if (crypto->cmd == SET_KEY) {
1256 rt2800_register_read(rt2x00dev, offset, &reg);
1257 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1258 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1259 /*
1260 * Both the cipher as the BSS Idx numbers are split in a main
1261 * value of 3 bits, and a extended field for adding one additional
1262 * bit to the value.
1263 */
1264 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1265 (crypto->cipher & 0x7));
1266 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1267 (crypto->cipher & 0x8) >> 3);
1268 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1269 rt2800_register_write(rt2x00dev, offset, reg);
1270 } else {
1271 /* Delete the cipher without touching the bssidx */
1272 rt2800_register_read(rt2x00dev, offset, &reg);
1273 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1274 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1275 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1276 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1277 rt2800_register_write(rt2x00dev, offset, reg);
1278 }
1279
1280 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1281
1282 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1283 if ((crypto->cipher == CIPHER_TKIP) ||
1284 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1285 (crypto->cipher == CIPHER_AES))
1286 iveiv_entry.iv[3] |= 0x20;
1287 iveiv_entry.iv[3] |= key->keyidx << 6;
1288 rt2800_register_multiwrite(rt2x00dev, offset,
1289 &iveiv_entry, sizeof(iveiv_entry));
1290 }
1291
1292 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1293 struct rt2x00lib_crypto *crypto,
1294 struct ieee80211_key_conf *key)
1295 {
1296 struct hw_key_entry key_entry;
1297 struct rt2x00_field32 field;
1298 u32 offset;
1299 u32 reg;
1300
1301 if (crypto->cmd == SET_KEY) {
1302 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1303
1304 memcpy(key_entry.key, crypto->key,
1305 sizeof(key_entry.key));
1306 memcpy(key_entry.tx_mic, crypto->tx_mic,
1307 sizeof(key_entry.tx_mic));
1308 memcpy(key_entry.rx_mic, crypto->rx_mic,
1309 sizeof(key_entry.rx_mic));
1310
1311 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1312 rt2800_register_multiwrite(rt2x00dev, offset,
1313 &key_entry, sizeof(key_entry));
1314 }
1315
1316 /*
1317 * The cipher types are stored over multiple registers
1318 * starting with SHARED_KEY_MODE_BASE each word will have
1319 * 32 bits and contains the cipher types for 2 bssidx each.
1320 * Using the correct defines correctly will cause overhead,
1321 * so just calculate the correct offset.
1322 */
1323 field.bit_offset = 4 * (key->hw_key_idx % 8);
1324 field.bit_mask = 0x7 << field.bit_offset;
1325
1326 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1327
1328 rt2800_register_read(rt2x00dev, offset, &reg);
1329 rt2x00_set_field32(&reg, field,
1330 (crypto->cmd == SET_KEY) * crypto->cipher);
1331 rt2800_register_write(rt2x00dev, offset, reg);
1332
1333 /*
1334 * Update WCID information
1335 */
1336 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1337 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1338 crypto->bssidx);
1339 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1340
1341 return 0;
1342 }
1343 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1344
1345 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1346 {
1347 struct mac_wcid_entry wcid_entry;
1348 int idx;
1349 u32 offset;
1350
1351 /*
1352 * Search for the first free WCID entry and return the corresponding
1353 * index.
1354 *
1355 * Make sure the WCID starts _after_ the last possible shared key
1356 * entry (>32).
1357 *
1358 * Since parts of the pairwise key table might be shared with
1359 * the beacon frame buffers 6 & 7 we should only write into the
1360 * first 222 entries.
1361 */
1362 for (idx = 33; idx <= 222; idx++) {
1363 offset = MAC_WCID_ENTRY(idx);
1364 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1365 sizeof(wcid_entry));
1366 if (is_broadcast_ether_addr(wcid_entry.mac))
1367 return idx;
1368 }
1369
1370 /*
1371 * Use -1 to indicate that we don't have any more space in the WCID
1372 * table.
1373 */
1374 return -1;
1375 }
1376
1377 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1378 struct rt2x00lib_crypto *crypto,
1379 struct ieee80211_key_conf *key)
1380 {
1381 struct hw_key_entry key_entry;
1382 u32 offset;
1383
1384 if (crypto->cmd == SET_KEY) {
1385 /*
1386 * Allow key configuration only for STAs that are
1387 * known by the hw.
1388 */
1389 if (crypto->wcid < 0)
1390 return -ENOSPC;
1391 key->hw_key_idx = crypto->wcid;
1392
1393 memcpy(key_entry.key, crypto->key,
1394 sizeof(key_entry.key));
1395 memcpy(key_entry.tx_mic, crypto->tx_mic,
1396 sizeof(key_entry.tx_mic));
1397 memcpy(key_entry.rx_mic, crypto->rx_mic,
1398 sizeof(key_entry.rx_mic));
1399
1400 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1401 rt2800_register_multiwrite(rt2x00dev, offset,
1402 &key_entry, sizeof(key_entry));
1403 }
1404
1405 /*
1406 * Update WCID information
1407 */
1408 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1409
1410 return 0;
1411 }
1412 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1413
1414 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1415 struct ieee80211_sta *sta)
1416 {
1417 int wcid;
1418 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1419
1420 /*
1421 * Find next free WCID.
1422 */
1423 wcid = rt2800_find_wcid(rt2x00dev);
1424
1425 /*
1426 * Store selected wcid even if it is invalid so that we can
1427 * later decide if the STA is uploaded into the hw.
1428 */
1429 sta_priv->wcid = wcid;
1430
1431 /*
1432 * No space left in the device, however, we can still communicate
1433 * with the STA -> No error.
1434 */
1435 if (wcid < 0)
1436 return 0;
1437
1438 /*
1439 * Clean up WCID attributes and write STA address to the device.
1440 */
1441 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1442 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1443 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1444 rt2x00lib_get_bssidx(rt2x00dev, vif));
1445 return 0;
1446 }
1447 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1448
1449 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1450 {
1451 /*
1452 * Remove WCID entry, no need to clean the attributes as they will
1453 * get renewed when the WCID is reused.
1454 */
1455 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1456
1457 return 0;
1458 }
1459 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1460
1461 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1462 const unsigned int filter_flags)
1463 {
1464 u32 reg;
1465
1466 /*
1467 * Start configuration steps.
1468 * Note that the version error will always be dropped
1469 * and broadcast frames will always be accepted since
1470 * there is no filter for it at this time.
1471 */
1472 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1473 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1474 !(filter_flags & FIF_FCSFAIL));
1475 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1476 !(filter_flags & FIF_PLCPFAIL));
1477 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1478 !(filter_flags & FIF_PROMISC_IN_BSS));
1479 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1480 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1481 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1482 !(filter_flags & FIF_ALLMULTI));
1483 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1484 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1485 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1486 !(filter_flags & FIF_CONTROL));
1487 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1488 !(filter_flags & FIF_CONTROL));
1489 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1490 !(filter_flags & FIF_CONTROL));
1491 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1492 !(filter_flags & FIF_CONTROL));
1493 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1494 !(filter_flags & FIF_CONTROL));
1495 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1496 !(filter_flags & FIF_PSPOLL));
1497 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1498 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1499 !(filter_flags & FIF_CONTROL));
1500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1501 !(filter_flags & FIF_CONTROL));
1502 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1505
1506 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1507 struct rt2x00intf_conf *conf, const unsigned int flags)
1508 {
1509 u32 reg;
1510 bool update_bssid = false;
1511
1512 if (flags & CONFIG_UPDATE_TYPE) {
1513 /*
1514 * Enable synchronisation.
1515 */
1516 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1517 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1518 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1519
1520 if (conf->sync == TSF_SYNC_AP_NONE) {
1521 /*
1522 * Tune beacon queue transmit parameters for AP mode
1523 */
1524 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1525 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1526 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1527 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1528 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1529 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1530 } else {
1531 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1532 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1533 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1534 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1535 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1536 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1537 }
1538 }
1539
1540 if (flags & CONFIG_UPDATE_MAC) {
1541 if (flags & CONFIG_UPDATE_TYPE &&
1542 conf->sync == TSF_SYNC_AP_NONE) {
1543 /*
1544 * The BSSID register has to be set to our own mac
1545 * address in AP mode.
1546 */
1547 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1548 update_bssid = true;
1549 }
1550
1551 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1552 reg = le32_to_cpu(conf->mac[1]);
1553 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1554 conf->mac[1] = cpu_to_le32(reg);
1555 }
1556
1557 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1558 conf->mac, sizeof(conf->mac));
1559 }
1560
1561 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1562 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1563 reg = le32_to_cpu(conf->bssid[1]);
1564 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1565 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1566 conf->bssid[1] = cpu_to_le32(reg);
1567 }
1568
1569 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1570 conf->bssid, sizeof(conf->bssid));
1571 }
1572 }
1573 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1574
1575 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1576 struct rt2x00lib_erp *erp)
1577 {
1578 bool any_sta_nongf = !!(erp->ht_opmode &
1579 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1580 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1581 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1582 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1583 u32 reg;
1584
1585 /* default protection rate for HT20: OFDM 24M */
1586 mm20_rate = gf20_rate = 0x4004;
1587
1588 /* default protection rate for HT40: duplicate OFDM 24M */
1589 mm40_rate = gf40_rate = 0x4084;
1590
1591 switch (protection) {
1592 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1593 /*
1594 * All STAs in this BSS are HT20/40 but there might be
1595 * STAs not supporting greenfield mode.
1596 * => Disable protection for HT transmissions.
1597 */
1598 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1599
1600 break;
1601 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1602 /*
1603 * All STAs in this BSS are HT20 or HT20/40 but there
1604 * might be STAs not supporting greenfield mode.
1605 * => Protect all HT40 transmissions.
1606 */
1607 mm20_mode = gf20_mode = 0;
1608 mm40_mode = gf40_mode = 2;
1609
1610 break;
1611 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1612 /*
1613 * Nonmember protection:
1614 * According to 802.11n we _should_ protect all
1615 * HT transmissions (but we don't have to).
1616 *
1617 * But if cts_protection is enabled we _shall_ protect
1618 * all HT transmissions using a CCK rate.
1619 *
1620 * And if any station is non GF we _shall_ protect
1621 * GF transmissions.
1622 *
1623 * We decide to protect everything
1624 * -> fall through to mixed mode.
1625 */
1626 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1627 /*
1628 * Legacy STAs are present
1629 * => Protect all HT transmissions.
1630 */
1631 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1632
1633 /*
1634 * If erp protection is needed we have to protect HT
1635 * transmissions with CCK 11M long preamble.
1636 */
1637 if (erp->cts_protection) {
1638 /* don't duplicate RTS/CTS in CCK mode */
1639 mm20_rate = mm40_rate = 0x0003;
1640 gf20_rate = gf40_rate = 0x0003;
1641 }
1642 break;
1643 }
1644
1645 /* check for STAs not supporting greenfield mode */
1646 if (any_sta_nongf)
1647 gf20_mode = gf40_mode = 2;
1648
1649 /* Update HT protection config */
1650 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1651 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1652 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1653 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1654
1655 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1656 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1657 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1658 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1659
1660 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1661 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1662 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1663 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1664
1665 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1666 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1667 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1668 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1669 }
1670
1671 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1672 u32 changed)
1673 {
1674 u32 reg;
1675
1676 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1677 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1678 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1679 !!erp->short_preamble);
1680 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1681 !!erp->short_preamble);
1682 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1683 }
1684
1685 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1686 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1687 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1688 erp->cts_protection ? 2 : 0);
1689 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1690 }
1691
1692 if (changed & BSS_CHANGED_BASIC_RATES) {
1693 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1694 erp->basic_rates);
1695 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1696 }
1697
1698 if (changed & BSS_CHANGED_ERP_SLOT) {
1699 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1700 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1701 erp->slot_time);
1702 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1703
1704 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1705 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1706 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1707 }
1708
1709 if (changed & BSS_CHANGED_BEACON_INT) {
1710 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1711 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1712 erp->beacon_int * 16);
1713 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1714 }
1715
1716 if (changed & BSS_CHANGED_HT)
1717 rt2800_config_ht_opmode(rt2x00dev, erp);
1718 }
1719 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1720
1721 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1722 {
1723 u32 reg;
1724 u16 eeprom;
1725 u8 led_ctrl, led_g_mode, led_r_mode;
1726
1727 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1728 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1729 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1730 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1731 } else {
1732 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1733 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1734 }
1735 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1736
1737 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1738 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1739 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1740 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1741 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1742 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1743 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1744 if (led_ctrl == 0 || led_ctrl > 0x40) {
1745 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1746 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1747 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1748 } else {
1749 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1750 (led_g_mode << 2) | led_r_mode, 1);
1751 }
1752 }
1753 }
1754
1755 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1756 enum antenna ant)
1757 {
1758 u32 reg;
1759 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1760 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1761
1762 if (rt2x00_is_pci(rt2x00dev)) {
1763 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1764 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1765 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1766 } else if (rt2x00_is_usb(rt2x00dev))
1767 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1768 eesk_pin, 0);
1769
1770 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1771 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1772 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1773 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1774 }
1775
1776 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1777 {
1778 u8 r1;
1779 u8 r3;
1780 u16 eeprom;
1781
1782 rt2800_bbp_read(rt2x00dev, 1, &r1);
1783 rt2800_bbp_read(rt2x00dev, 3, &r3);
1784
1785 if (rt2x00_rt(rt2x00dev, RT3572) &&
1786 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1787 rt2800_config_3572bt_ant(rt2x00dev);
1788
1789 /*
1790 * Configure the TX antenna.
1791 */
1792 switch (ant->tx_chain_num) {
1793 case 1:
1794 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1795 break;
1796 case 2:
1797 if (rt2x00_rt(rt2x00dev, RT3572) &&
1798 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1799 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1800 else
1801 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1802 break;
1803 case 3:
1804 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1805 break;
1806 }
1807
1808 /*
1809 * Configure the RX antenna.
1810 */
1811 switch (ant->rx_chain_num) {
1812 case 1:
1813 if (rt2x00_rt(rt2x00dev, RT3070) ||
1814 rt2x00_rt(rt2x00dev, RT3090) ||
1815 rt2x00_rt(rt2x00dev, RT3352) ||
1816 rt2x00_rt(rt2x00dev, RT3390)) {
1817 rt2800_eeprom_read(rt2x00dev,
1818 EEPROM_NIC_CONF1, &eeprom);
1819 if (rt2x00_get_field16(eeprom,
1820 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1821 rt2800_set_ant_diversity(rt2x00dev,
1822 rt2x00dev->default_ant.rx);
1823 }
1824 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1825 break;
1826 case 2:
1827 if (rt2x00_rt(rt2x00dev, RT3572) &&
1828 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1829 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1830 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1831 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1832 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1833 } else {
1834 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1835 }
1836 break;
1837 case 3:
1838 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1839 break;
1840 }
1841
1842 rt2800_bbp_write(rt2x00dev, 3, r3);
1843 rt2800_bbp_write(rt2x00dev, 1, r1);
1844
1845 if (rt2x00_rt(rt2x00dev, RT3593)) {
1846 if (ant->rx_chain_num == 1)
1847 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1848 else
1849 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1850 }
1851 }
1852 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1853
1854 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1855 struct rt2x00lib_conf *libconf)
1856 {
1857 u16 eeprom;
1858 short lna_gain;
1859
1860 if (libconf->rf.channel <= 14) {
1861 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1862 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1863 } else if (libconf->rf.channel <= 64) {
1864 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1865 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1866 } else if (libconf->rf.channel <= 128) {
1867 if (rt2x00_rt(rt2x00dev, RT3593)) {
1868 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1869 lna_gain = rt2x00_get_field16(eeprom,
1870 EEPROM_EXT_LNA2_A1);
1871 } else {
1872 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1873 lna_gain = rt2x00_get_field16(eeprom,
1874 EEPROM_RSSI_BG2_LNA_A1);
1875 }
1876 } else {
1877 if (rt2x00_rt(rt2x00dev, RT3593)) {
1878 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1879 lna_gain = rt2x00_get_field16(eeprom,
1880 EEPROM_EXT_LNA2_A2);
1881 } else {
1882 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1883 lna_gain = rt2x00_get_field16(eeprom,
1884 EEPROM_RSSI_A2_LNA_A2);
1885 }
1886 }
1887
1888 rt2x00dev->lna_gain = lna_gain;
1889 }
1890
1891 #define FREQ_OFFSET_BOUND 0x5f
1892
1893 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1894 {
1895 u8 freq_offset, prev_freq_offset;
1896 u8 rfcsr, prev_rfcsr;
1897
1898 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1899 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1900
1901 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1902 prev_rfcsr = rfcsr;
1903
1904 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1905 if (rfcsr == prev_rfcsr)
1906 return;
1907
1908 if (rt2x00_is_usb(rt2x00dev)) {
1909 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1910 freq_offset, prev_rfcsr);
1911 return;
1912 }
1913
1914 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1915 while (prev_freq_offset != freq_offset) {
1916 if (prev_freq_offset < freq_offset)
1917 prev_freq_offset++;
1918 else
1919 prev_freq_offset--;
1920
1921 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1922 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1923
1924 usleep_range(1000, 1500);
1925 }
1926 }
1927
1928 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1929 struct ieee80211_conf *conf,
1930 struct rf_channel *rf,
1931 struct channel_info *info)
1932 {
1933 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1934
1935 if (rt2x00dev->default_ant.tx_chain_num == 1)
1936 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1937
1938 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1939 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1940 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1941 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1942 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1943
1944 if (rf->channel > 14) {
1945 /*
1946 * When TX power is below 0, we should increase it by 7 to
1947 * make it a positive value (Minimum value is -7).
1948 * However this means that values between 0 and 7 have
1949 * double meaning, and we should set a 7DBm boost flag.
1950 */
1951 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1952 (info->default_power1 >= 0));
1953
1954 if (info->default_power1 < 0)
1955 info->default_power1 += 7;
1956
1957 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1958
1959 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1960 (info->default_power2 >= 0));
1961
1962 if (info->default_power2 < 0)
1963 info->default_power2 += 7;
1964
1965 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1966 } else {
1967 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1968 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1969 }
1970
1971 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1972
1973 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1974 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1975 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1976 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1977
1978 udelay(200);
1979
1980 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1981 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1982 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1983 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1984
1985 udelay(200);
1986
1987 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1988 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1989 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1990 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1991 }
1992
1993 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1994 struct ieee80211_conf *conf,
1995 struct rf_channel *rf,
1996 struct channel_info *info)
1997 {
1998 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1999 u8 rfcsr, calib_tx, calib_rx;
2000
2001 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2002
2003 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2004 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2005 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2006
2007 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2008 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2009 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2010
2011 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2012 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2013 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2014
2015 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2016 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2017 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2018
2019 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2020 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2021 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2022 rt2x00dev->default_ant.rx_chain_num <= 1);
2023 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2024 rt2x00dev->default_ant.rx_chain_num <= 2);
2025 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2026 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2027 rt2x00dev->default_ant.tx_chain_num <= 1);
2028 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2029 rt2x00dev->default_ant.tx_chain_num <= 2);
2030 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2031
2032 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2033 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2034 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2035 msleep(1);
2036 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2037 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2038
2039 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2040 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2041 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2042
2043 if (rt2x00_rt(rt2x00dev, RT3390)) {
2044 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2045 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2046 } else {
2047 if (conf_is_ht40(conf)) {
2048 calib_tx = drv_data->calibration_bw40;
2049 calib_rx = drv_data->calibration_bw40;
2050 } else {
2051 calib_tx = drv_data->calibration_bw20;
2052 calib_rx = drv_data->calibration_bw20;
2053 }
2054 }
2055
2056 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2057 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2058 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2059
2060 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2061 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2062 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2063
2064 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2065 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2066 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2067
2068 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2069 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2070 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2071 msleep(1);
2072 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2073 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2074 }
2075
2076 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2077 struct ieee80211_conf *conf,
2078 struct rf_channel *rf,
2079 struct channel_info *info)
2080 {
2081 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2082 u8 rfcsr;
2083 u32 reg;
2084
2085 if (rf->channel <= 14) {
2086 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2087 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2088 } else {
2089 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2090 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2091 }
2092
2093 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2094 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2095
2096 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2097 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2098 if (rf->channel <= 14)
2099 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2100 else
2101 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2102 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2103
2104 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2105 if (rf->channel <= 14)
2106 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2107 else
2108 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2109 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2110
2111 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2112 if (rf->channel <= 14) {
2113 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2114 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2115 info->default_power1);
2116 } else {
2117 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2118 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2119 (info->default_power1 & 0x3) |
2120 ((info->default_power1 & 0xC) << 1));
2121 }
2122 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2123
2124 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2125 if (rf->channel <= 14) {
2126 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2127 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2128 info->default_power2);
2129 } else {
2130 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2131 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2132 (info->default_power2 & 0x3) |
2133 ((info->default_power2 & 0xC) << 1));
2134 }
2135 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2136
2137 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2138 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2139 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2140 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2141 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2142 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2143 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2144 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2145 if (rf->channel <= 14) {
2146 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2147 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2148 }
2149 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2150 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2151 } else {
2152 switch (rt2x00dev->default_ant.tx_chain_num) {
2153 case 1:
2154 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2155 case 2:
2156 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2157 break;
2158 }
2159
2160 switch (rt2x00dev->default_ant.rx_chain_num) {
2161 case 1:
2162 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2163 case 2:
2164 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2165 break;
2166 }
2167 }
2168 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2169
2170 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2171 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2172 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2173
2174 if (conf_is_ht40(conf)) {
2175 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2176 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2177 } else {
2178 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2179 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2180 }
2181
2182 if (rf->channel <= 14) {
2183 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2184 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2185 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2186 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2187 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2188 rfcsr = 0x4c;
2189 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2190 drv_data->txmixer_gain_24g);
2191 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2192 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2193 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2194 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2195 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2196 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2197 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2198 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2199 } else {
2200 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2201 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2202 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2203 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2204 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2205 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2206 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2207 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2208 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2209 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2210 rfcsr = 0x7a;
2211 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2212 drv_data->txmixer_gain_5g);
2213 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2214 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2215 if (rf->channel <= 64) {
2216 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2217 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2218 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2219 } else if (rf->channel <= 128) {
2220 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2221 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2222 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2223 } else {
2224 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2225 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2226 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2227 }
2228 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2229 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2230 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2231 }
2232
2233 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2234 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2235 if (rf->channel <= 14)
2236 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2237 else
2238 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2239 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2240
2241 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2242 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2243 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2244 }
2245
2246 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2247 struct ieee80211_conf *conf,
2248 struct rf_channel *rf,
2249 struct channel_info *info)
2250 {
2251 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2252 u8 txrx_agc_fc;
2253 u8 txrx_h20m;
2254 u8 rfcsr;
2255 u8 bbp;
2256 const bool txbf_enabled = false; /* TODO */
2257
2258 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2259 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2260 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2261 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2262 rt2800_bbp_write(rt2x00dev, 109, bbp);
2263
2264 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2265 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2266 rt2800_bbp_write(rt2x00dev, 110, bbp);
2267
2268 if (rf->channel <= 14) {
2269 /* Restore BBP 25 & 26 for 2.4 GHz */
2270 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2271 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2272 } else {
2273 /* Hard code BBP 25 & 26 for 5GHz */
2274
2275 /* Enable IQ Phase correction */
2276 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2277 /* Setup IQ Phase correction value */
2278 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2279 }
2280
2281 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2282 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2283
2284 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2285 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2286 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2287
2288 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2289 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2290 if (rf->channel <= 14)
2291 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2292 else
2293 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2294 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2295
2296 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2297 if (rf->channel <= 14) {
2298 rfcsr = 0;
2299 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2300 info->default_power1 & 0x1f);
2301 } else {
2302 if (rt2x00_is_usb(rt2x00dev))
2303 rfcsr = 0x40;
2304
2305 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2306 ((info->default_power1 & 0x18) << 1) |
2307 (info->default_power1 & 7));
2308 }
2309 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2310
2311 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2312 if (rf->channel <= 14) {
2313 rfcsr = 0;
2314 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2315 info->default_power2 & 0x1f);
2316 } else {
2317 if (rt2x00_is_usb(rt2x00dev))
2318 rfcsr = 0x40;
2319
2320 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2321 ((info->default_power2 & 0x18) << 1) |
2322 (info->default_power2 & 7));
2323 }
2324 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2325
2326 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2327 if (rf->channel <= 14) {
2328 rfcsr = 0;
2329 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2330 info->default_power3 & 0x1f);
2331 } else {
2332 if (rt2x00_is_usb(rt2x00dev))
2333 rfcsr = 0x40;
2334
2335 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2336 ((info->default_power3 & 0x18) << 1) |
2337 (info->default_power3 & 7));
2338 }
2339 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2340
2341 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2342 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2343 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2344 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2345 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2346 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2347 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2348 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2349 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2350
2351 switch (rt2x00dev->default_ant.tx_chain_num) {
2352 case 3:
2353 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2354 /* fallthrough */
2355 case 2:
2356 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2357 /* fallthrough */
2358 case 1:
2359 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2360 break;
2361 }
2362
2363 switch (rt2x00dev->default_ant.rx_chain_num) {
2364 case 3:
2365 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2366 /* fallthrough */
2367 case 2:
2368 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2369 /* fallthrough */
2370 case 1:
2371 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2372 break;
2373 }
2374 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2375
2376 rt2800_adjust_freq_offset(rt2x00dev);
2377
2378 if (conf_is_ht40(conf)) {
2379 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2380 RFCSR24_TX_AGC_FC);
2381 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2382 RFCSR24_TX_H20M);
2383 } else {
2384 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2385 RFCSR24_TX_AGC_FC);
2386 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2387 RFCSR24_TX_H20M);
2388 }
2389
2390 /* NOTE: the reference driver does not writes the new value
2391 * back to RFCSR 32
2392 */
2393 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2394 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2395
2396 if (rf->channel <= 14)
2397 rfcsr = 0xa0;
2398 else
2399 rfcsr = 0x80;
2400 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2401
2402 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2403 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2404 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2405 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2406
2407 /* Band selection */
2408 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2409 if (rf->channel <= 14)
2410 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2411 else
2412 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2413 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2414
2415 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2416 if (rf->channel <= 14)
2417 rfcsr = 0x3c;
2418 else
2419 rfcsr = 0x20;
2420 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2421
2422 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2423 if (rf->channel <= 14)
2424 rfcsr = 0x1a;
2425 else
2426 rfcsr = 0x12;
2427 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2428
2429 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2430 if (rf->channel >= 1 && rf->channel <= 14)
2431 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2432 else if (rf->channel >= 36 && rf->channel <= 64)
2433 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2434 else if (rf->channel >= 100 && rf->channel <= 128)
2435 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2436 else
2437 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2438 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2439
2440 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2441 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2442 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2443
2444 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2445
2446 if (rf->channel <= 14) {
2447 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2448 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2449 } else {
2450 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2451 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2452 }
2453
2454 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2455 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2456 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2457
2458 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2459 if (rf->channel <= 14) {
2460 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2461 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2462 } else {
2463 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2464 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2465 }
2466 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2467
2468 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2469 if (rf->channel <= 14)
2470 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2471 else
2472 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2473
2474 if (txbf_enabled)
2475 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2476
2477 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2478
2479 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2480 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2481 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2482
2483 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2484 if (rf->channel <= 14)
2485 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2486 else
2487 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2488 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2489
2490 if (rf->channel <= 14) {
2491 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2492 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2493 } else {
2494 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2495 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2496 }
2497
2498 /* Initiate VCO calibration */
2499 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2500 if (rf->channel <= 14) {
2501 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2502 } else {
2503 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2504 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2505 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2506 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2507 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2508 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2509 }
2510 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2511
2512 if (rf->channel >= 1 && rf->channel <= 14) {
2513 rfcsr = 0x23;
2514 if (txbf_enabled)
2515 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2516 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2517
2518 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2519 } else if (rf->channel >= 36 && rf->channel <= 64) {
2520 rfcsr = 0x36;
2521 if (txbf_enabled)
2522 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2523 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2524
2525 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2526 } else if (rf->channel >= 100 && rf->channel <= 128) {
2527 rfcsr = 0x32;
2528 if (txbf_enabled)
2529 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2530 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2531
2532 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2533 } else {
2534 rfcsr = 0x30;
2535 if (txbf_enabled)
2536 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2537 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2538
2539 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2540 }
2541 }
2542
2543 #define POWER_BOUND 0x27
2544 #define POWER_BOUND_5G 0x2b
2545
2546 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2547 struct ieee80211_conf *conf,
2548 struct rf_channel *rf,
2549 struct channel_info *info)
2550 {
2551 u8 rfcsr;
2552
2553 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2554 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2555 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2556 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2557 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2558
2559 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2560 if (info->default_power1 > POWER_BOUND)
2561 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2562 else
2563 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2564 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2565
2566 rt2800_adjust_freq_offset(rt2x00dev);
2567
2568 if (rf->channel <= 14) {
2569 if (rf->channel == 6)
2570 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2571 else
2572 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2573
2574 if (rf->channel >= 1 && rf->channel <= 6)
2575 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2576 else if (rf->channel >= 7 && rf->channel <= 11)
2577 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2578 else if (rf->channel >= 12 && rf->channel <= 14)
2579 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2580 }
2581 }
2582
2583 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2584 struct ieee80211_conf *conf,
2585 struct rf_channel *rf,
2586 struct channel_info *info)
2587 {
2588 u8 rfcsr;
2589
2590 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2591 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2592
2593 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2594 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2595 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2596
2597 if (info->default_power1 > POWER_BOUND)
2598 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2599 else
2600 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2601
2602 if (info->default_power2 > POWER_BOUND)
2603 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2604 else
2605 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2606
2607 rt2800_adjust_freq_offset(rt2x00dev);
2608
2609 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2610 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2611 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2612
2613 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2614 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2615 else
2616 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2617
2618 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2619 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2620 else
2621 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2622
2623 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2624 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2625
2626 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2627
2628 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2629 }
2630
2631 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2632 struct ieee80211_conf *conf,
2633 struct rf_channel *rf,
2634 struct channel_info *info)
2635 {
2636 u8 rfcsr;
2637
2638 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2639 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2640 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2641 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2642 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2643
2644 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2645 if (info->default_power1 > POWER_BOUND)
2646 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2647 else
2648 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2649 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2650
2651 if (rt2x00_rt(rt2x00dev, RT5392)) {
2652 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2653 if (info->default_power1 > POWER_BOUND)
2654 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2655 else
2656 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2657 info->default_power2);
2658 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2659 }
2660
2661 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2662 if (rt2x00_rt(rt2x00dev, RT5392)) {
2663 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2664 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2665 }
2666 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2667 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2668 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2669 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2670 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2671
2672 rt2800_adjust_freq_offset(rt2x00dev);
2673
2674 if (rf->channel <= 14) {
2675 int idx = rf->channel-1;
2676
2677 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2678 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2679 /* r55/r59 value array of channel 1~14 */
2680 static const char r55_bt_rev[] = {0x83, 0x83,
2681 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2682 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2683 static const char r59_bt_rev[] = {0x0e, 0x0e,
2684 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2685 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2686
2687 rt2800_rfcsr_write(rt2x00dev, 55,
2688 r55_bt_rev[idx]);
2689 rt2800_rfcsr_write(rt2x00dev, 59,
2690 r59_bt_rev[idx]);
2691 } else {
2692 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2693 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2694 0x88, 0x88, 0x86, 0x85, 0x84};
2695
2696 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2697 }
2698 } else {
2699 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2700 static const char r55_nonbt_rev[] = {0x23, 0x23,
2701 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2702 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2703 static const char r59_nonbt_rev[] = {0x07, 0x07,
2704 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2705 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2706
2707 rt2800_rfcsr_write(rt2x00dev, 55,
2708 r55_nonbt_rev[idx]);
2709 rt2800_rfcsr_write(rt2x00dev, 59,
2710 r59_nonbt_rev[idx]);
2711 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2712 rt2x00_rt(rt2x00dev, RT5392)) {
2713 static const char r59_non_bt[] = {0x8f, 0x8f,
2714 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2715 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2716
2717 rt2800_rfcsr_write(rt2x00dev, 59,
2718 r59_non_bt[idx]);
2719 }
2720 }
2721 }
2722 }
2723
2724 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2725 struct ieee80211_conf *conf,
2726 struct rf_channel *rf,
2727 struct channel_info *info)
2728 {
2729 u8 rfcsr, ep_reg;
2730 u32 reg;
2731 int power_bound;
2732
2733 /* TODO */
2734 const bool is_11b = false;
2735 const bool is_type_ep = false;
2736
2737 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2738 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2739 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2740 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2741
2742 /* Order of values on rf_channel entry: N, K, mod, R */
2743 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2744
2745 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2746 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2747 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2748 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2749 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2750
2751 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2752 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2753 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2754 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2755
2756 if (rf->channel <= 14) {
2757 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2758 /* FIXME: RF11 owerwrite ? */
2759 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2760 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2761 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2762 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2763 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2764 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2765 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2766 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2767 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2768 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2769 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2770 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2771 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2772 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2773 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2774 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2775 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2776 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2777 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2778 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2779 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2780 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2781 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2782 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2783 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2784 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2785 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2786 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2787
2788 /* TODO RF27 <- tssi */
2789
2790 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2791 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2792 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2793
2794 if (is_11b) {
2795 /* CCK */
2796 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2797 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2798 if (is_type_ep)
2799 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2800 else
2801 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2802 } else {
2803 /* OFDM */
2804 if (is_type_ep)
2805 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2806 else
2807 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2808 }
2809
2810 power_bound = POWER_BOUND;
2811 ep_reg = 0x2;
2812 } else {
2813 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2814 /* FIMXE: RF11 overwrite */
2815 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2816 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2817 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2818 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2819 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2820 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2821 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2822 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2823 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2824 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2825 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2826 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2827 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2828 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2829
2830 /* TODO RF27 <- tssi */
2831
2832 if (rf->channel >= 36 && rf->channel <= 64) {
2833
2834 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2835 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2836 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2837 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2838 if (rf->channel <= 50)
2839 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2840 else if (rf->channel >= 52)
2841 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2842 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2843 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2844 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2845 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2846 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2847 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2848 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2849 if (rf->channel <= 50) {
2850 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2851 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2852 } else if (rf->channel >= 52) {
2853 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2854 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2855 }
2856
2857 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2858 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2859 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2860
2861 } else if (rf->channel >= 100 && rf->channel <= 165) {
2862
2863 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2864 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2865 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2866 if (rf->channel <= 153) {
2867 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2868 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2869 } else if (rf->channel >= 155) {
2870 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2871 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2872 }
2873 if (rf->channel <= 138) {
2874 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2875 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2876 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2877 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2878 } else if (rf->channel >= 140) {
2879 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2880 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2881 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2882 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2883 }
2884 if (rf->channel <= 124)
2885 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2886 else if (rf->channel >= 126)
2887 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2888 if (rf->channel <= 138)
2889 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2890 else if (rf->channel >= 140)
2891 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2892 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2893 if (rf->channel <= 138)
2894 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2895 else if (rf->channel >= 140)
2896 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2897 if (rf->channel <= 128)
2898 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2899 else if (rf->channel >= 130)
2900 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2901 if (rf->channel <= 116)
2902 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2903 else if (rf->channel >= 118)
2904 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2905 if (rf->channel <= 138)
2906 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2907 else if (rf->channel >= 140)
2908 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2909 if (rf->channel <= 116)
2910 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2911 else if (rf->channel >= 118)
2912 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2913 }
2914
2915 power_bound = POWER_BOUND_5G;
2916 ep_reg = 0x3;
2917 }
2918
2919 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2920 if (info->default_power1 > power_bound)
2921 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2922 else
2923 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2924 if (is_type_ep)
2925 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2926 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2927
2928 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2929 if (info->default_power2 > power_bound)
2930 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2931 else
2932 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2933 if (is_type_ep)
2934 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2935 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2936
2937 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2938 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2939 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2940
2941 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2942 rt2x00dev->default_ant.tx_chain_num >= 1);
2943 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2944 rt2x00dev->default_ant.tx_chain_num == 2);
2945 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2946
2947 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2948 rt2x00dev->default_ant.rx_chain_num >= 1);
2949 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2950 rt2x00dev->default_ant.rx_chain_num == 2);
2951 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2952
2953 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2954 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2955
2956 if (conf_is_ht40(conf))
2957 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2958 else
2959 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2960
2961 if (!is_11b) {
2962 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2963 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2964 }
2965
2966 /* TODO proper frequency adjustment */
2967 rt2800_adjust_freq_offset(rt2x00dev);
2968
2969 /* TODO merge with others */
2970 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2971 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2972 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2973
2974 /* BBP settings */
2975 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2976 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2977 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2978
2979 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2980 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2981 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2982 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2983
2984 /* GLRT band configuration */
2985 rt2800_bbp_write(rt2x00dev, 195, 128);
2986 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2987 rt2800_bbp_write(rt2x00dev, 195, 129);
2988 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2989 rt2800_bbp_write(rt2x00dev, 195, 130);
2990 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2991 rt2800_bbp_write(rt2x00dev, 195, 131);
2992 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2993 rt2800_bbp_write(rt2x00dev, 195, 133);
2994 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2995 rt2800_bbp_write(rt2x00dev, 195, 124);
2996 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2997 }
2998
2999 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3000 const unsigned int word,
3001 const u8 value)
3002 {
3003 u8 chain, reg;
3004
3005 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3006 rt2800_bbp_read(rt2x00dev, 27, &reg);
3007 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3008 rt2800_bbp_write(rt2x00dev, 27, reg);
3009
3010 rt2800_bbp_write(rt2x00dev, word, value);
3011 }
3012 }
3013
3014 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3015 {
3016 u8 cal;
3017
3018 /* TX0 IQ Gain */
3019 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3020 if (channel <= 14)
3021 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3022 else if (channel >= 36 && channel <= 64)
3023 cal = rt2x00_eeprom_byte(rt2x00dev,
3024 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3025 else if (channel >= 100 && channel <= 138)
3026 cal = rt2x00_eeprom_byte(rt2x00dev,
3027 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3028 else if (channel >= 140 && channel <= 165)
3029 cal = rt2x00_eeprom_byte(rt2x00dev,
3030 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3031 else
3032 cal = 0;
3033 rt2800_bbp_write(rt2x00dev, 159, cal);
3034
3035 /* TX0 IQ Phase */
3036 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3037 if (channel <= 14)
3038 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3039 else if (channel >= 36 && channel <= 64)
3040 cal = rt2x00_eeprom_byte(rt2x00dev,
3041 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3042 else if (channel >= 100 && channel <= 138)
3043 cal = rt2x00_eeprom_byte(rt2x00dev,
3044 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3045 else if (channel >= 140 && channel <= 165)
3046 cal = rt2x00_eeprom_byte(rt2x00dev,
3047 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3048 else
3049 cal = 0;
3050 rt2800_bbp_write(rt2x00dev, 159, cal);
3051
3052 /* TX1 IQ Gain */
3053 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3054 if (channel <= 14)
3055 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3056 else if (channel >= 36 && channel <= 64)
3057 cal = rt2x00_eeprom_byte(rt2x00dev,
3058 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3059 else if (channel >= 100 && channel <= 138)
3060 cal = rt2x00_eeprom_byte(rt2x00dev,
3061 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3062 else if (channel >= 140 && channel <= 165)
3063 cal = rt2x00_eeprom_byte(rt2x00dev,
3064 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3065 else
3066 cal = 0;
3067 rt2800_bbp_write(rt2x00dev, 159, cal);
3068
3069 /* TX1 IQ Phase */
3070 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3071 if (channel <= 14)
3072 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3073 else if (channel >= 36 && channel <= 64)
3074 cal = rt2x00_eeprom_byte(rt2x00dev,
3075 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3076 else if (channel >= 100 && channel <= 138)
3077 cal = rt2x00_eeprom_byte(rt2x00dev,
3078 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3079 else if (channel >= 140 && channel <= 165)
3080 cal = rt2x00_eeprom_byte(rt2x00dev,
3081 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3082 else
3083 cal = 0;
3084 rt2800_bbp_write(rt2x00dev, 159, cal);
3085
3086 /* FIXME: possible RX0, RX1 callibration ? */
3087
3088 /* RF IQ compensation control */
3089 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3090 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3091 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3092
3093 /* RF IQ imbalance compensation control */
3094 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3095 cal = rt2x00_eeprom_byte(rt2x00dev,
3096 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3097 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3098 }
3099
3100 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3101 unsigned int channel,
3102 char txpower)
3103 {
3104 if (rt2x00_rt(rt2x00dev, RT3593))
3105 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3106
3107 if (channel <= 14)
3108 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3109
3110 if (rt2x00_rt(rt2x00dev, RT3593))
3111 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3112 MAX_A_TXPOWER_3593);
3113 else
3114 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3115 }
3116
3117 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3118 struct ieee80211_conf *conf,
3119 struct rf_channel *rf,
3120 struct channel_info *info)
3121 {
3122 u32 reg;
3123 unsigned int tx_pin;
3124 u8 bbp, rfcsr;
3125
3126 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3127 info->default_power1);
3128 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3129 info->default_power2);
3130 if (rt2x00dev->default_ant.tx_chain_num > 2)
3131 info->default_power3 =
3132 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3133 info->default_power3);
3134
3135 switch (rt2x00dev->chip.rf) {
3136 case RF2020:
3137 case RF3020:
3138 case RF3021:
3139 case RF3022:
3140 case RF3320:
3141 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3142 break;
3143 case RF3052:
3144 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3145 break;
3146 case RF3053:
3147 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3148 break;
3149 case RF3290:
3150 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3151 break;
3152 case RF3322:
3153 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3154 break;
3155 case RF3070:
3156 case RF5360:
3157 case RF5370:
3158 case RF5372:
3159 case RF5390:
3160 case RF5392:
3161 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3162 break;
3163 case RF5592:
3164 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3165 break;
3166 default:
3167 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3168 }
3169
3170 if (rt2x00_rf(rt2x00dev, RF3070) ||
3171 rt2x00_rf(rt2x00dev, RF3290) ||
3172 rt2x00_rf(rt2x00dev, RF3322) ||
3173 rt2x00_rf(rt2x00dev, RF5360) ||
3174 rt2x00_rf(rt2x00dev, RF5370) ||
3175 rt2x00_rf(rt2x00dev, RF5372) ||
3176 rt2x00_rf(rt2x00dev, RF5390) ||
3177 rt2x00_rf(rt2x00dev, RF5392)) {
3178 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3179 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3180 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3181 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3182
3183 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3184 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3185 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3186 }
3187
3188 /*
3189 * Change BBP settings
3190 */
3191 if (rt2x00_rt(rt2x00dev, RT3352)) {
3192 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3193 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3194 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3195 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3196 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3197 if (rf->channel > 14) {
3198 /* Disable CCK Packet detection on 5GHz */
3199 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3200 } else {
3201 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3202 }
3203
3204 if (conf_is_ht40(conf))
3205 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3206 else
3207 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3208
3209 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3210 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3211 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3212 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3213 } else {
3214 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3215 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3216 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3217 rt2800_bbp_write(rt2x00dev, 86, 0);
3218 }
3219
3220 if (rf->channel <= 14) {
3221 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3222 !rt2x00_rt(rt2x00dev, RT5392)) {
3223 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3224 &rt2x00dev->cap_flags)) {
3225 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3226 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3227 } else {
3228 if (rt2x00_rt(rt2x00dev, RT3593))
3229 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3230 else
3231 rt2800_bbp_write(rt2x00dev, 82, 0x84);
3232 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3233 }
3234 if (rt2x00_rt(rt2x00dev, RT3593))
3235 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3236 }
3237
3238 } else {
3239 if (rt2x00_rt(rt2x00dev, RT3572))
3240 rt2800_bbp_write(rt2x00dev, 82, 0x94);
3241 else if (rt2x00_rt(rt2x00dev, RT3593))
3242 rt2800_bbp_write(rt2x00dev, 82, 0x82);
3243 else
3244 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3245
3246 if (rt2x00_rt(rt2x00dev, RT3593))
3247 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3248
3249 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
3250 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3251 else
3252 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3253 }
3254
3255 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3256 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3257 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3258 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3259 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3260
3261 if (rt2x00_rt(rt2x00dev, RT3572))
3262 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3263
3264 tx_pin = 0;
3265
3266 switch (rt2x00dev->default_ant.tx_chain_num) {
3267 case 3:
3268 /* Turn on tertiary PAs */
3269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3270 rf->channel > 14);
3271 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3272 rf->channel <= 14);
3273 /* fall-through */
3274 case 2:
3275 /* Turn on secondary PAs */
3276 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3277 rf->channel > 14);
3278 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3279 rf->channel <= 14);
3280 /* fall-through */
3281 case 1:
3282 /* Turn on primary PAs */
3283 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3284 rf->channel > 14);
3285 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
3286 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3287 else
3288 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3289 rf->channel <= 14);
3290 break;
3291 }
3292
3293 switch (rt2x00dev->default_ant.rx_chain_num) {
3294 case 3:
3295 /* Turn on tertiary LNAs */
3296 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3297 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3298 /* fall-through */
3299 case 2:
3300 /* Turn on secondary LNAs */
3301 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3302 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3303 /* fall-through */
3304 case 1:
3305 /* Turn on primary LNAs */
3306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3307 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3308 break;
3309 }
3310
3311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3312 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3313
3314 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3315
3316 if (rt2x00_rt(rt2x00dev, RT3572))
3317 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3318
3319 if (rt2x00_rt(rt2x00dev, RT3593)) {
3320 if (rt2x00_is_usb(rt2x00dev)) {
3321 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3322
3323 /* Band selection. GPIO #8 controls all paths */
3324 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3325 if (rf->channel <= 14)
3326 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3327 else
3328 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3329
3330 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3331 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3332
3333 /* LNA PE control.
3334 * GPIO #4 controls PE0 and PE1,
3335 * GPIO #7 controls PE2
3336 */
3337 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3338 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3339
3340 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3341 }
3342
3343 /* AGC init */
3344 if (rf->channel <= 14)
3345 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3346 else
3347 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3348
3349 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3350
3351 usleep_range(1000, 1500);
3352 }
3353
3354 if (rt2x00_rt(rt2x00dev, RT5592)) {
3355 rt2800_bbp_write(rt2x00dev, 195, 141);
3356 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3357
3358 /* AGC init */
3359 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3360 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3361
3362 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3363 }
3364
3365 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3366 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3367 rt2800_bbp_write(rt2x00dev, 4, bbp);
3368
3369 rt2800_bbp_read(rt2x00dev, 3, &bbp);
3370 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3371 rt2800_bbp_write(rt2x00dev, 3, bbp);
3372
3373 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3374 if (conf_is_ht40(conf)) {
3375 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3376 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3377 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3378 } else {
3379 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3380 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3381 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3382 }
3383 }
3384
3385 msleep(1);
3386
3387 /*
3388 * Clear channel statistic counters
3389 */
3390 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3391 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3392 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3393
3394 /*
3395 * Clear update flag
3396 */
3397 if (rt2x00_rt(rt2x00dev, RT3352)) {
3398 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3399 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3400 rt2800_bbp_write(rt2x00dev, 49, bbp);
3401 }
3402 }
3403
3404 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3405 {
3406 u8 tssi_bounds[9];
3407 u8 current_tssi;
3408 u16 eeprom;
3409 u8 step;
3410 int i;
3411
3412 /*
3413 * First check if temperature compensation is supported.
3414 */
3415 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3416 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3417 return 0;
3418
3419 /*
3420 * Read TSSI boundaries for temperature compensation from
3421 * the EEPROM.
3422 *
3423 * Array idx 0 1 2 3 4 5 6 7 8
3424 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3425 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3426 */
3427 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3428 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3429 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3430 EEPROM_TSSI_BOUND_BG1_MINUS4);
3431 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3432 EEPROM_TSSI_BOUND_BG1_MINUS3);
3433
3434 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3435 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3436 EEPROM_TSSI_BOUND_BG2_MINUS2);
3437 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3438 EEPROM_TSSI_BOUND_BG2_MINUS1);
3439
3440 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3441 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3442 EEPROM_TSSI_BOUND_BG3_REF);
3443 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3444 EEPROM_TSSI_BOUND_BG3_PLUS1);
3445
3446 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3447 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3448 EEPROM_TSSI_BOUND_BG4_PLUS2);
3449 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3450 EEPROM_TSSI_BOUND_BG4_PLUS3);
3451
3452 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3453 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3454 EEPROM_TSSI_BOUND_BG5_PLUS4);
3455
3456 step = rt2x00_get_field16(eeprom,
3457 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3458 } else {
3459 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3460 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3461 EEPROM_TSSI_BOUND_A1_MINUS4);
3462 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3463 EEPROM_TSSI_BOUND_A1_MINUS3);
3464
3465 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3466 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3467 EEPROM_TSSI_BOUND_A2_MINUS2);
3468 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3469 EEPROM_TSSI_BOUND_A2_MINUS1);
3470
3471 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3472 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3473 EEPROM_TSSI_BOUND_A3_REF);
3474 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3475 EEPROM_TSSI_BOUND_A3_PLUS1);
3476
3477 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3478 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3479 EEPROM_TSSI_BOUND_A4_PLUS2);
3480 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3481 EEPROM_TSSI_BOUND_A4_PLUS3);
3482
3483 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3484 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3485 EEPROM_TSSI_BOUND_A5_PLUS4);
3486
3487 step = rt2x00_get_field16(eeprom,
3488 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3489 }
3490
3491 /*
3492 * Check if temperature compensation is supported.
3493 */
3494 if (tssi_bounds[4] == 0xff || step == 0xff)
3495 return 0;
3496
3497 /*
3498 * Read current TSSI (BBP 49).
3499 */
3500 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3501
3502 /*
3503 * Compare TSSI value (BBP49) with the compensation boundaries
3504 * from the EEPROM and increase or decrease tx power.
3505 */
3506 for (i = 0; i <= 3; i++) {
3507 if (current_tssi > tssi_bounds[i])
3508 break;
3509 }
3510
3511 if (i == 4) {
3512 for (i = 8; i >= 5; i--) {
3513 if (current_tssi < tssi_bounds[i])
3514 break;
3515 }
3516 }
3517
3518 return (i - 4) * step;
3519 }
3520
3521 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3522 enum ieee80211_band band)
3523 {
3524 u16 eeprom;
3525 u8 comp_en;
3526 u8 comp_type;
3527 int comp_value = 0;
3528
3529 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3530
3531 /*
3532 * HT40 compensation not required.
3533 */
3534 if (eeprom == 0xffff ||
3535 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3536 return 0;
3537
3538 if (band == IEEE80211_BAND_2GHZ) {
3539 comp_en = rt2x00_get_field16(eeprom,
3540 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3541 if (comp_en) {
3542 comp_type = rt2x00_get_field16(eeprom,
3543 EEPROM_TXPOWER_DELTA_TYPE_2G);
3544 comp_value = rt2x00_get_field16(eeprom,
3545 EEPROM_TXPOWER_DELTA_VALUE_2G);
3546 if (!comp_type)
3547 comp_value = -comp_value;
3548 }
3549 } else {
3550 comp_en = rt2x00_get_field16(eeprom,
3551 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3552 if (comp_en) {
3553 comp_type = rt2x00_get_field16(eeprom,
3554 EEPROM_TXPOWER_DELTA_TYPE_5G);
3555 comp_value = rt2x00_get_field16(eeprom,
3556 EEPROM_TXPOWER_DELTA_VALUE_5G);
3557 if (!comp_type)
3558 comp_value = -comp_value;
3559 }
3560 }
3561
3562 return comp_value;
3563 }
3564
3565 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3566 int power_level, int max_power)
3567 {
3568 int delta;
3569
3570 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
3571 return 0;
3572
3573 /*
3574 * XXX: We don't know the maximum transmit power of our hardware since
3575 * the EEPROM doesn't expose it. We only know that we are calibrated
3576 * to 100% tx power.
3577 *
3578 * Hence, we assume the regulatory limit that cfg80211 calulated for
3579 * the current channel is our maximum and if we are requested to lower
3580 * the value we just reduce our tx power accordingly.
3581 */
3582 delta = power_level - max_power;
3583 return min(delta, 0);
3584 }
3585
3586 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3587 enum ieee80211_band band, int power_level,
3588 u8 txpower, int delta)
3589 {
3590 u16 eeprom;
3591 u8 criterion;
3592 u8 eirp_txpower;
3593 u8 eirp_txpower_criterion;
3594 u8 reg_limit;
3595
3596 if (rt2x00_rt(rt2x00dev, RT3593))
3597 return min_t(u8, txpower, 0xc);
3598
3599 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
3600 /*
3601 * Check if eirp txpower exceed txpower_limit.
3602 * We use OFDM 6M as criterion and its eirp txpower
3603 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3604 * .11b data rate need add additional 4dbm
3605 * when calculating eirp txpower.
3606 */
3607 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3608 1, &eeprom);
3609 criterion = rt2x00_get_field16(eeprom,
3610 EEPROM_TXPOWER_BYRATE_RATE0);
3611
3612 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3613 &eeprom);
3614
3615 if (band == IEEE80211_BAND_2GHZ)
3616 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3617 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3618 else
3619 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3620 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3621
3622 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3623 (is_rate_b ? 4 : 0) + delta;
3624
3625 reg_limit = (eirp_txpower > power_level) ?
3626 (eirp_txpower - power_level) : 0;
3627 } else
3628 reg_limit = 0;
3629
3630 txpower = max(0, txpower + delta - reg_limit);
3631 return min_t(u8, txpower, 0xc);
3632 }
3633
3634
3635 enum {
3636 TX_PWR_CFG_0_IDX,
3637 TX_PWR_CFG_1_IDX,
3638 TX_PWR_CFG_2_IDX,
3639 TX_PWR_CFG_3_IDX,
3640 TX_PWR_CFG_4_IDX,
3641 TX_PWR_CFG_5_IDX,
3642 TX_PWR_CFG_6_IDX,
3643 TX_PWR_CFG_7_IDX,
3644 TX_PWR_CFG_8_IDX,
3645 TX_PWR_CFG_9_IDX,
3646 TX_PWR_CFG_0_EXT_IDX,
3647 TX_PWR_CFG_1_EXT_IDX,
3648 TX_PWR_CFG_2_EXT_IDX,
3649 TX_PWR_CFG_3_EXT_IDX,
3650 TX_PWR_CFG_4_EXT_IDX,
3651 TX_PWR_CFG_IDX_COUNT,
3652 };
3653
3654 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3655 struct ieee80211_channel *chan,
3656 int power_level)
3657 {
3658 u8 txpower;
3659 u16 eeprom;
3660 u32 regs[TX_PWR_CFG_IDX_COUNT];
3661 unsigned int offset;
3662 enum ieee80211_band band = chan->band;
3663 int delta;
3664 int i;
3665
3666 memset(regs, '\0', sizeof(regs));
3667
3668 /* TODO: adapt TX power reduction from the rt28xx code */
3669
3670 /* calculate temperature compensation delta */
3671 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3672
3673 if (band == IEEE80211_BAND_5GHZ)
3674 offset = 16;
3675 else
3676 offset = 0;
3677
3678 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3679 offset += 8;
3680
3681 /* read the next four txpower values */
3682 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3683 offset, &eeprom);
3684
3685 /* CCK 1MBS,2MBS */
3686 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3687 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3688 txpower, delta);
3689 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3690 TX_PWR_CFG_0_CCK1_CH0, txpower);
3691 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3692 TX_PWR_CFG_0_CCK1_CH1, txpower);
3693 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3694 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3695
3696 /* CCK 5.5MBS,11MBS */
3697 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3698 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3699 txpower, delta);
3700 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3701 TX_PWR_CFG_0_CCK5_CH0, txpower);
3702 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3703 TX_PWR_CFG_0_CCK5_CH1, txpower);
3704 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3705 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3706
3707 /* OFDM 6MBS,9MBS */
3708 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3709 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3710 txpower, delta);
3711 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3712 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3713 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3714 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3715 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3716 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3717
3718 /* OFDM 12MBS,18MBS */
3719 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3720 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3721 txpower, delta);
3722 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3723 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3724 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3725 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3726 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3727 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3728
3729 /* read the next four txpower values */
3730 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3731 offset + 1, &eeprom);
3732
3733 /* OFDM 24MBS,36MBS */
3734 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3735 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3736 txpower, delta);
3737 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3738 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3739 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3740 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3741 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3742 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3743
3744 /* OFDM 48MBS */
3745 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3746 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3747 txpower, delta);
3748 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3749 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3750 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3751 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3752 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3753 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3754
3755 /* OFDM 54MBS */
3756 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3757 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3758 txpower, delta);
3759 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3760 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3761 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3762 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3763 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3764 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3765
3766 /* read the next four txpower values */
3767 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3768 offset + 2, &eeprom);
3769
3770 /* MCS 0,1 */
3771 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3772 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3773 txpower, delta);
3774 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3775 TX_PWR_CFG_1_MCS0_CH0, txpower);
3776 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3777 TX_PWR_CFG_1_MCS0_CH1, txpower);
3778 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3779 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3780
3781 /* MCS 2,3 */
3782 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3783 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3784 txpower, delta);
3785 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3786 TX_PWR_CFG_1_MCS2_CH0, txpower);
3787 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3788 TX_PWR_CFG_1_MCS2_CH1, txpower);
3789 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3790 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3791
3792 /* MCS 4,5 */
3793 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3794 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3795 txpower, delta);
3796 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3797 TX_PWR_CFG_2_MCS4_CH0, txpower);
3798 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3799 TX_PWR_CFG_2_MCS4_CH1, txpower);
3800 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3801 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3802
3803 /* MCS 6 */
3804 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3805 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3806 txpower, delta);
3807 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3808 TX_PWR_CFG_2_MCS6_CH0, txpower);
3809 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3810 TX_PWR_CFG_2_MCS6_CH1, txpower);
3811 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3812 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3813
3814 /* read the next four txpower values */
3815 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3816 offset + 3, &eeprom);
3817
3818 /* MCS 7 */
3819 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3820 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3821 txpower, delta);
3822 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3823 TX_PWR_CFG_7_MCS7_CH0, txpower);
3824 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3825 TX_PWR_CFG_7_MCS7_CH1, txpower);
3826 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3827 TX_PWR_CFG_7_MCS7_CH2, txpower);
3828
3829 /* MCS 8,9 */
3830 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3831 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3832 txpower, delta);
3833 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3834 TX_PWR_CFG_2_MCS8_CH0, txpower);
3835 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3836 TX_PWR_CFG_2_MCS8_CH1, txpower);
3837 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3838 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3839
3840 /* MCS 10,11 */
3841 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3842 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3843 txpower, delta);
3844 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3845 TX_PWR_CFG_2_MCS10_CH0, txpower);
3846 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3847 TX_PWR_CFG_2_MCS10_CH1, txpower);
3848 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3849 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3850
3851 /* MCS 12,13 */
3852 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3853 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3854 txpower, delta);
3855 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3856 TX_PWR_CFG_3_MCS12_CH0, txpower);
3857 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3858 TX_PWR_CFG_3_MCS12_CH1, txpower);
3859 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3860 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3861
3862 /* read the next four txpower values */
3863 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3864 offset + 4, &eeprom);
3865
3866 /* MCS 14 */
3867 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3868 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3869 txpower, delta);
3870 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3871 TX_PWR_CFG_3_MCS14_CH0, txpower);
3872 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3873 TX_PWR_CFG_3_MCS14_CH1, txpower);
3874 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3875 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3876
3877 /* MCS 15 */
3878 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3879 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3880 txpower, delta);
3881 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3882 TX_PWR_CFG_8_MCS15_CH0, txpower);
3883 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3884 TX_PWR_CFG_8_MCS15_CH1, txpower);
3885 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3886 TX_PWR_CFG_8_MCS15_CH2, txpower);
3887
3888 /* MCS 16,17 */
3889 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3890 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3891 txpower, delta);
3892 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3893 TX_PWR_CFG_5_MCS16_CH0, txpower);
3894 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3895 TX_PWR_CFG_5_MCS16_CH1, txpower);
3896 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3897 TX_PWR_CFG_5_MCS16_CH2, txpower);
3898
3899 /* MCS 18,19 */
3900 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3901 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3902 txpower, delta);
3903 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3904 TX_PWR_CFG_5_MCS18_CH0, txpower);
3905 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3906 TX_PWR_CFG_5_MCS18_CH1, txpower);
3907 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3908 TX_PWR_CFG_5_MCS18_CH2, txpower);
3909
3910 /* read the next four txpower values */
3911 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3912 offset + 5, &eeprom);
3913
3914 /* MCS 20,21 */
3915 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3916 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3917 txpower, delta);
3918 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3919 TX_PWR_CFG_6_MCS20_CH0, txpower);
3920 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3921 TX_PWR_CFG_6_MCS20_CH1, txpower);
3922 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3923 TX_PWR_CFG_6_MCS20_CH2, txpower);
3924
3925 /* MCS 22 */
3926 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3927 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3928 txpower, delta);
3929 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3930 TX_PWR_CFG_6_MCS22_CH0, txpower);
3931 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3932 TX_PWR_CFG_6_MCS22_CH1, txpower);
3933 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3934 TX_PWR_CFG_6_MCS22_CH2, txpower);
3935
3936 /* MCS 23 */
3937 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3938 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3939 txpower, delta);
3940 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3941 TX_PWR_CFG_8_MCS23_CH0, txpower);
3942 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3943 TX_PWR_CFG_8_MCS23_CH1, txpower);
3944 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3945 TX_PWR_CFG_8_MCS23_CH2, txpower);
3946
3947 /* read the next four txpower values */
3948 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3949 offset + 6, &eeprom);
3950
3951 /* STBC, MCS 0,1 */
3952 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3953 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3954 txpower, delta);
3955 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3956 TX_PWR_CFG_3_STBC0_CH0, txpower);
3957 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3958 TX_PWR_CFG_3_STBC0_CH1, txpower);
3959 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3960 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3961
3962 /* STBC, MCS 2,3 */
3963 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3964 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3965 txpower, delta);
3966 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3967 TX_PWR_CFG_3_STBC2_CH0, txpower);
3968 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3969 TX_PWR_CFG_3_STBC2_CH1, txpower);
3970 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3971 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3972
3973 /* STBC, MCS 4,5 */
3974 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3975 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3976 txpower, delta);
3977 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3978 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3979 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3980 txpower);
3981
3982 /* STBC, MCS 6 */
3983 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3984 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3985 txpower, delta);
3986 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3987 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3988 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3989 txpower);
3990
3991 /* read the next four txpower values */
3992 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3993 offset + 7, &eeprom);
3994
3995 /* STBC, MCS 7 */
3996 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3997 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3998 txpower, delta);
3999 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4000 TX_PWR_CFG_9_STBC7_CH0, txpower);
4001 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4002 TX_PWR_CFG_9_STBC7_CH1, txpower);
4003 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4004 TX_PWR_CFG_9_STBC7_CH2, txpower);
4005
4006 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4007 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4016
4017 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4018 regs[TX_PWR_CFG_0_EXT_IDX]);
4019 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4020 regs[TX_PWR_CFG_1_EXT_IDX]);
4021 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4022 regs[TX_PWR_CFG_2_EXT_IDX]);
4023 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4024 regs[TX_PWR_CFG_3_EXT_IDX]);
4025 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4026 regs[TX_PWR_CFG_4_EXT_IDX]);
4027
4028 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4029 rt2x00_dbg(rt2x00dev,
4030 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4031 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4032 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4033 '4' : '2',
4034 (i > TX_PWR_CFG_9_IDX) ?
4035 (i - TX_PWR_CFG_9_IDX - 1) : i,
4036 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4037 (unsigned long) regs[i]);
4038 }
4039
4040 /*
4041 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4042 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4043 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4044 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4045 * Reference per rate transmit power values are located in the EEPROM at
4046 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4047 * current conditions (i.e. band, bandwidth, temperature, user settings).
4048 */
4049 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4050 struct ieee80211_channel *chan,
4051 int power_level)
4052 {
4053 u8 txpower, r1;
4054 u16 eeprom;
4055 u32 reg, offset;
4056 int i, is_rate_b, delta, power_ctrl;
4057 enum ieee80211_band band = chan->band;
4058
4059 /*
4060 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4061 * value read from EEPROM (different for 2GHz and for 5GHz).
4062 */
4063 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4064
4065 /*
4066 * Calculate temperature compensation. Depends on measurement of current
4067 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4068 * to temperature or maybe other factors) is smaller or bigger than
4069 * expected. We adjust it, based on TSSI reference and boundaries values
4070 * provided in EEPROM.
4071 */
4072 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4073
4074 /*
4075 * Decrease power according to user settings, on devices with unknown
4076 * maximum tx power. For other devices we take user power_level into
4077 * consideration on rt2800_compensate_txpower().
4078 */
4079 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4080 chan->max_power);
4081
4082 /*
4083 * BBP_R1 controls TX power for all rates, it allow to set the following
4084 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4085 *
4086 * TODO: we do not use +6 dBm option to do not increase power beyond
4087 * regulatory limit, however this could be utilized for devices with
4088 * CAPABILITY_POWER_LIMIT.
4089 *
4090 * TODO: add different temperature compensation code for RT3290 & RT5390
4091 * to allow to use BBP_R1 for those chips.
4092 */
4093 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4094 !rt2x00_rt(rt2x00dev, RT5390)) {
4095 rt2800_bbp_read(rt2x00dev, 1, &r1);
4096 if (delta <= -12) {
4097 power_ctrl = 2;
4098 delta += 12;
4099 } else if (delta <= -6) {
4100 power_ctrl = 1;
4101 delta += 6;
4102 } else {
4103 power_ctrl = 0;
4104 }
4105 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4106 rt2800_bbp_write(rt2x00dev, 1, r1);
4107 }
4108
4109 offset = TX_PWR_CFG_0;
4110
4111 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4112 /* just to be safe */
4113 if (offset > TX_PWR_CFG_4)
4114 break;
4115
4116 rt2800_register_read(rt2x00dev, offset, &reg);
4117
4118 /* read the next four txpower values */
4119 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4120 i, &eeprom);
4121
4122 is_rate_b = i ? 0 : 1;
4123 /*
4124 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4125 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4126 * TX_PWR_CFG_4: unknown
4127 */
4128 txpower = rt2x00_get_field16(eeprom,
4129 EEPROM_TXPOWER_BYRATE_RATE0);
4130 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4131 power_level, txpower, delta);
4132 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4133
4134 /*
4135 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4136 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4137 * TX_PWR_CFG_4: unknown
4138 */
4139 txpower = rt2x00_get_field16(eeprom,
4140 EEPROM_TXPOWER_BYRATE_RATE1);
4141 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4142 power_level, txpower, delta);
4143 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4144
4145 /*
4146 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4147 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4148 * TX_PWR_CFG_4: unknown
4149 */
4150 txpower = rt2x00_get_field16(eeprom,
4151 EEPROM_TXPOWER_BYRATE_RATE2);
4152 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4153 power_level, txpower, delta);
4154 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4155
4156 /*
4157 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4158 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4159 * TX_PWR_CFG_4: unknown
4160 */
4161 txpower = rt2x00_get_field16(eeprom,
4162 EEPROM_TXPOWER_BYRATE_RATE3);
4163 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4164 power_level, txpower, delta);
4165 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4166
4167 /* read the next four txpower values */
4168 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4169 i + 1, &eeprom);
4170
4171 is_rate_b = 0;
4172 /*
4173 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4174 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4175 * TX_PWR_CFG_4: unknown
4176 */
4177 txpower = rt2x00_get_field16(eeprom,
4178 EEPROM_TXPOWER_BYRATE_RATE0);
4179 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4180 power_level, txpower, delta);
4181 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4182
4183 /*
4184 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4185 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4186 * TX_PWR_CFG_4: unknown
4187 */
4188 txpower = rt2x00_get_field16(eeprom,
4189 EEPROM_TXPOWER_BYRATE_RATE1);
4190 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4191 power_level, txpower, delta);
4192 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4193
4194 /*
4195 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4196 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4197 * TX_PWR_CFG_4: unknown
4198 */
4199 txpower = rt2x00_get_field16(eeprom,
4200 EEPROM_TXPOWER_BYRATE_RATE2);
4201 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4202 power_level, txpower, delta);
4203 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4204
4205 /*
4206 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4207 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4208 * TX_PWR_CFG_4: unknown
4209 */
4210 txpower = rt2x00_get_field16(eeprom,
4211 EEPROM_TXPOWER_BYRATE_RATE3);
4212 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4213 power_level, txpower, delta);
4214 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4215
4216 rt2800_register_write(rt2x00dev, offset, reg);
4217
4218 /* next TX_PWR_CFG register */
4219 offset += 4;
4220 }
4221 }
4222
4223 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4224 struct ieee80211_channel *chan,
4225 int power_level)
4226 {
4227 if (rt2x00_rt(rt2x00dev, RT3593))
4228 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4229 else
4230 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4231 }
4232
4233 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4234 {
4235 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4236 rt2x00dev->tx_power);
4237 }
4238 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4239
4240 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4241 {
4242 u32 tx_pin;
4243 u8 rfcsr;
4244
4245 /*
4246 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4247 * designed to be controlled in oscillation frequency by a voltage
4248 * input. Maybe the temperature will affect the frequency of
4249 * oscillation to be shifted. The VCO calibration will be called
4250 * periodically to adjust the frequency to be precision.
4251 */
4252
4253 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4254 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4255 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4256
4257 switch (rt2x00dev->chip.rf) {
4258 case RF2020:
4259 case RF3020:
4260 case RF3021:
4261 case RF3022:
4262 case RF3320:
4263 case RF3052:
4264 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4265 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4266 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4267 break;
4268 case RF3053:
4269 case RF3070:
4270 case RF3290:
4271 case RF5360:
4272 case RF5370:
4273 case RF5372:
4274 case RF5390:
4275 case RF5392:
4276 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4277 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4278 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4279 break;
4280 default:
4281 return;
4282 }
4283
4284 mdelay(1);
4285
4286 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4287 if (rt2x00dev->rf_channel <= 14) {
4288 switch (rt2x00dev->default_ant.tx_chain_num) {
4289 case 3:
4290 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4291 /* fall through */
4292 case 2:
4293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4294 /* fall through */
4295 case 1:
4296 default:
4297 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4298 break;
4299 }
4300 } else {
4301 switch (rt2x00dev->default_ant.tx_chain_num) {
4302 case 3:
4303 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4304 /* fall through */
4305 case 2:
4306 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4307 /* fall through */
4308 case 1:
4309 default:
4310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4311 break;
4312 }
4313 }
4314 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4315
4316 }
4317 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4318
4319 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4320 struct rt2x00lib_conf *libconf)
4321 {
4322 u32 reg;
4323
4324 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4325 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4326 libconf->conf->short_frame_max_tx_count);
4327 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4328 libconf->conf->long_frame_max_tx_count);
4329 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4330 }
4331
4332 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4333 struct rt2x00lib_conf *libconf)
4334 {
4335 enum dev_state state =
4336 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4337 STATE_SLEEP : STATE_AWAKE;
4338 u32 reg;
4339
4340 if (state == STATE_SLEEP) {
4341 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4342
4343 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4344 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4345 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4346 libconf->conf->listen_interval - 1);
4347 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4348 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4349
4350 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4351 } else {
4352 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4353 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4354 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4355 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4356 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4357
4358 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4359 }
4360 }
4361
4362 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4363 struct rt2x00lib_conf *libconf,
4364 const unsigned int flags)
4365 {
4366 /* Always recalculate LNA gain before changing configuration */
4367 rt2800_config_lna_gain(rt2x00dev, libconf);
4368
4369 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4370 rt2800_config_channel(rt2x00dev, libconf->conf,
4371 &libconf->rf, &libconf->channel);
4372 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4373 libconf->conf->power_level);
4374 }
4375 if (flags & IEEE80211_CONF_CHANGE_POWER)
4376 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4377 libconf->conf->power_level);
4378 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4379 rt2800_config_retry_limit(rt2x00dev, libconf);
4380 if (flags & IEEE80211_CONF_CHANGE_PS)
4381 rt2800_config_ps(rt2x00dev, libconf);
4382 }
4383 EXPORT_SYMBOL_GPL(rt2800_config);
4384
4385 /*
4386 * Link tuning
4387 */
4388 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4389 {
4390 u32 reg;
4391
4392 /*
4393 * Update FCS error count from register.
4394 */
4395 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4396 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4397 }
4398 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4399
4400 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4401 {
4402 u8 vgc;
4403
4404 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4405 if (rt2x00_rt(rt2x00dev, RT3070) ||
4406 rt2x00_rt(rt2x00dev, RT3071) ||
4407 rt2x00_rt(rt2x00dev, RT3090) ||
4408 rt2x00_rt(rt2x00dev, RT3290) ||
4409 rt2x00_rt(rt2x00dev, RT3390) ||
4410 rt2x00_rt(rt2x00dev, RT3572) ||
4411 rt2x00_rt(rt2x00dev, RT5390) ||
4412 rt2x00_rt(rt2x00dev, RT5392) ||
4413 rt2x00_rt(rt2x00dev, RT5592))
4414 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4415 else
4416 vgc = 0x2e + rt2x00dev->lna_gain;
4417 } else { /* 5GHZ band */
4418 if (rt2x00_rt(rt2x00dev, RT3572))
4419 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
4420 else if (rt2x00_rt(rt2x00dev, RT5592))
4421 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4422 else {
4423 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4424 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4425 else
4426 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4427 }
4428 }
4429
4430 return vgc;
4431 }
4432
4433 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4434 struct link_qual *qual, u8 vgc_level)
4435 {
4436 if (qual->vgc_level != vgc_level) {
4437 if (rt2x00_rt(rt2x00dev, RT5592)) {
4438 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4439 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4440 } else
4441 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4442 qual->vgc_level = vgc_level;
4443 qual->vgc_level_reg = vgc_level;
4444 }
4445 }
4446
4447 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4448 {
4449 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4450 }
4451 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4452
4453 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4454 const u32 count)
4455 {
4456 u8 vgc;
4457
4458 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4459 return;
4460 /*
4461 * When RSSI is better then -80 increase VGC level with 0x10, except
4462 * for rt5592 chip.
4463 */
4464
4465 vgc = rt2800_get_default_vgc(rt2x00dev);
4466
4467 if (rt2x00_rt(rt2x00dev, RT5592)) {
4468 if (qual->rssi > -65)
4469 vgc += 0x20;
4470 } else {
4471 if (qual->rssi > -80)
4472 vgc += 0x10;
4473 }
4474
4475 rt2800_set_vgc(rt2x00dev, qual, vgc);
4476 }
4477 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4478
4479 /*
4480 * Initialization functions.
4481 */
4482 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4483 {
4484 u32 reg;
4485 u16 eeprom;
4486 unsigned int i;
4487 int ret;
4488
4489 rt2800_disable_wpdma(rt2x00dev);
4490
4491 ret = rt2800_drv_init_registers(rt2x00dev);
4492 if (ret)
4493 return ret;
4494
4495 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
4496 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0,
4497 rt2800_get_beacon_offset(rt2x00dev, 0));
4498 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1,
4499 rt2800_get_beacon_offset(rt2x00dev, 1));
4500 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2,
4501 rt2800_get_beacon_offset(rt2x00dev, 2));
4502 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3,
4503 rt2800_get_beacon_offset(rt2x00dev, 3));
4504 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4505
4506 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
4507 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4,
4508 rt2800_get_beacon_offset(rt2x00dev, 4));
4509 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5,
4510 rt2800_get_beacon_offset(rt2x00dev, 5));
4511 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6,
4512 rt2800_get_beacon_offset(rt2x00dev, 6));
4513 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7,
4514 rt2800_get_beacon_offset(rt2x00dev, 7));
4515 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4516
4517 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4518 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4519
4520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4521
4522 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4523 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4524 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4525 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4526 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4527 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4528 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4529 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4530
4531 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4532
4533 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4534 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4535 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4536 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4537
4538 if (rt2x00_rt(rt2x00dev, RT3290)) {
4539 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4540 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4541 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4542 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4543 }
4544
4545 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4546 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4547 rt2x00_set_field32(&reg, LDO0_EN, 1);
4548 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4549 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4550 }
4551
4552 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4553 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4554 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4555 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4556 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4557
4558 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4559 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4560 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4561
4562 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4563 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4564 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4565 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4566 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4567 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4568
4569 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4570 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4571 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4572 }
4573
4574 if (rt2x00_rt(rt2x00dev, RT3071) ||
4575 rt2x00_rt(rt2x00dev, RT3090) ||
4576 rt2x00_rt(rt2x00dev, RT3290) ||
4577 rt2x00_rt(rt2x00dev, RT3390)) {
4578
4579 if (rt2x00_rt(rt2x00dev, RT3290))
4580 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4581 0x00000404);
4582 else
4583 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4584 0x00000400);
4585
4586 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4587 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4588 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4589 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4590 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4591 &eeprom);
4592 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4593 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4594 0x0000002c);
4595 else
4596 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4597 0x0000000f);
4598 } else {
4599 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4600 }
4601 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4602 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4603
4604 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4605 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4606 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4607 } else {
4608 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4609 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4610 }
4611 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4612 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4613 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4614 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4615 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4616 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4617 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4618 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4619 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4620 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4621 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4622 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4623 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4624 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4625 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4626 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4627 &eeprom);
4628 if (rt2x00_get_field16(eeprom,
4629 EEPROM_NIC_CONF1_DAC_TEST))
4630 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4631 0x0000001f);
4632 else
4633 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4634 0x0000000f);
4635 } else {
4636 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4637 0x00000000);
4638 }
4639 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4640 rt2x00_rt(rt2x00dev, RT5392) ||
4641 rt2x00_rt(rt2x00dev, RT5592)) {
4642 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4643 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4644 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4645 } else {
4646 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4647 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4648 }
4649
4650 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4651 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4652 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4653 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4654 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4655 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4656 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4657 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4658 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4659 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4660
4661 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4662 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4663 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4664 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4665 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4666
4667 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4668 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4669 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4670 rt2x00_rt(rt2x00dev, RT2883) ||
4671 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4672 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4673 else
4674 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4675 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4676 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4677 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4678
4679 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4680 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4681 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4682 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4683 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4684 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4685 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4686 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4687 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4688
4689 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4690
4691 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4692 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4693 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4694 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4695 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4696 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4697 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4698 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4699
4700 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4701 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4702 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4703 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4704 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4705 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4706 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4707 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4708 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4709
4710 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4711 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4712 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4713 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4714 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4715 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4716 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4717 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4718 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4719 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4720 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4721 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4722
4723 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4724 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4725 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4726 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4727 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4728 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4729 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4730 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4731 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4732 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4734 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4735
4736 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4737 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4738 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4739 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4740 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4741 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4742 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4743 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4744 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4745 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4746 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4747 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4748
4749 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4750 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4751 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4752 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4753 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4754 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4755 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4756 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4757 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4758 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4759 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4760 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4761
4762 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4763 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4764 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4765 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4766 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4767 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4768 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4769 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4770 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4771 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4772 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4773 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4774
4775 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4776 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4777 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4778 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4779 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4780 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4781 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4782 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4783 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4784 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4785 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4786 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4787
4788 if (rt2x00_is_usb(rt2x00dev)) {
4789 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4790
4791 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4792 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4793 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4794 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4795 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4796 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4797 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4798 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4799 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4800 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4801 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4802 }
4803
4804 /*
4805 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4806 * although it is reserved.
4807 */
4808 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4809 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4810 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4811 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4812 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4813 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4814 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4815 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4816 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4817 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4818 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4819 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4820
4821 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4822 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4823
4824 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4825 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4826 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4827 IEEE80211_MAX_RTS_THRESHOLD);
4828 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4829 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4830
4831 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4832
4833 /*
4834 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4835 * time should be set to 16. However, the original Ralink driver uses
4836 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4837 * connection problems with 11g + CTS protection. Hence, use the same
4838 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4839 */
4840 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4841 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4842 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4843 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4844 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4845 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4846 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4847
4848 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4849
4850 /*
4851 * ASIC will keep garbage value after boot, clear encryption keys.
4852 */
4853 for (i = 0; i < 4; i++)
4854 rt2800_register_write(rt2x00dev,
4855 SHARED_KEY_MODE_ENTRY(i), 0);
4856
4857 for (i = 0; i < 256; i++) {
4858 rt2800_config_wcid(rt2x00dev, NULL, i);
4859 rt2800_delete_wcid_attr(rt2x00dev, i);
4860 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4861 }
4862
4863 /*
4864 * Clear all beacons
4865 */
4866 for (i = 0; i < 8; i++)
4867 rt2800_clear_beacon_register(rt2x00dev, i);
4868
4869 if (rt2x00_is_usb(rt2x00dev)) {
4870 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4871 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4872 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4873 } else if (rt2x00_is_pcie(rt2x00dev)) {
4874 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4875 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4876 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4877 }
4878
4879 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4880 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4881 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4882 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4883 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4884 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4885 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4886 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4887 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4888 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4889
4890 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4891 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4892 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4893 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4894 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4895 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4896 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4897 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4898 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4899 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4900
4901 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4902 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4903 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4904 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4905 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4906 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4907 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4908 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4909 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4910 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4911
4912 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4913 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4914 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4915 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4916 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4917 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4918
4919 /*
4920 * Do not force the BA window size, we use the TXWI to set it
4921 */
4922 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4923 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4924 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4925 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4926
4927 /*
4928 * We must clear the error counters.
4929 * These registers are cleared on read,
4930 * so we may pass a useless variable to store the value.
4931 */
4932 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4933 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4934 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4935 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4936 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4937 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4938
4939 /*
4940 * Setup leadtime for pre tbtt interrupt to 6ms
4941 */
4942 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4943 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4944 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4945
4946 /*
4947 * Set up channel statistics timer
4948 */
4949 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4950 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4951 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
4952 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
4953 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
4954 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
4955 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4956
4957 return 0;
4958 }
4959
4960 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4961 {
4962 unsigned int i;
4963 u32 reg;
4964
4965 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4966 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
4967 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4968 return 0;
4969
4970 udelay(REGISTER_BUSY_DELAY);
4971 }
4972
4973 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
4974 return -EACCES;
4975 }
4976
4977 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
4978 {
4979 unsigned int i;
4980 u8 value;
4981
4982 /*
4983 * BBP was enabled after firmware was loaded,
4984 * but we need to reactivate it now.
4985 */
4986 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
4987 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
4988 msleep(1);
4989
4990 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4991 rt2800_bbp_read(rt2x00dev, 0, &value);
4992 if ((value != 0xff) && (value != 0x00))
4993 return 0;
4994 udelay(REGISTER_BUSY_DELAY);
4995 }
4996
4997 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
4998 return -EACCES;
4999 }
5000
5001 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5002 {
5003 u8 value;
5004
5005 rt2800_bbp_read(rt2x00dev, 4, &value);
5006 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5007 rt2800_bbp_write(rt2x00dev, 4, value);
5008 }
5009
5010 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5011 {
5012 rt2800_bbp_write(rt2x00dev, 142, 1);
5013 rt2800_bbp_write(rt2x00dev, 143, 57);
5014 }
5015
5016 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5017 {
5018 const u8 glrt_table[] = {
5019 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5020 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5021 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5022 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5023 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5024 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5026 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5027 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5028 };
5029 int i;
5030
5031 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5032 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5033 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5034 }
5035 };
5036
5037 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5038 {
5039 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5040 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5041 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5042 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5043 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5044 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5045 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5046 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5047 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5048 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5049 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5050 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5051 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5052 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5053 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5054 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5055 }
5056
5057 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5058 {
5059 u16 eeprom;
5060 u8 value;
5061
5062 rt2800_bbp_read(rt2x00dev, 138, &value);
5063 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5064 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5065 value |= 0x20;
5066 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5067 value &= ~0x02;
5068 rt2800_bbp_write(rt2x00dev, 138, value);
5069 }
5070
5071 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5072 {
5073 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5074
5075 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5076 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5077
5078 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5079 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5080
5081 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5082
5083 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5084 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5085
5086 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5087
5088 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5089
5090 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5091
5092 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5093
5094 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5095
5096 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5097
5098 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5099
5100 rt2800_bbp_write(rt2x00dev, 105, 0x01);
5101
5102 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5103 }
5104
5105 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5106 {
5107 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5108 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5109
5110 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5111 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5112 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5113 } else {
5114 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5115 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5116 }
5117
5118 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5119
5120 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5121
5122 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5123
5124 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5125
5126 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5127 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5128 else
5129 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5130
5131 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5132
5133 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5134
5135 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5136
5137 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5138
5139 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5140
5141 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5142 }
5143
5144 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5145 {
5146 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5147 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5148
5149 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5150 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5151
5152 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5153
5154 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5155 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5156 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5157
5158 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5159
5160 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5161
5162 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5163
5164 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5165
5166 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5167
5168 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5169
5170 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5171 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5172 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5173 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5174 else
5175 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5176
5177 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5178
5179 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5180
5181 if (rt2x00_rt(rt2x00dev, RT3071) ||
5182 rt2x00_rt(rt2x00dev, RT3090))
5183 rt2800_disable_unused_dac_adc(rt2x00dev);
5184 }
5185
5186 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5187 {
5188 u8 value;
5189
5190 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5191
5192 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5193
5194 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5195 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5196
5197 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5198
5199 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5200 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5201 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5202 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5203
5204 rt2800_bbp_write(rt2x00dev, 77, 0x58);
5205
5206 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5207
5208 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5209 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5210 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5211 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5212
5213 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5214
5215 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5216
5217 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5218
5219 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5220
5221 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5222
5223 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5224
5225 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5226
5227 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5228
5229 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5230
5231 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5232
5233 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5234
5235 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5236 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5237 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5238 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5239 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5240 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5241 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5242 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5243 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5244 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5245
5246 rt2800_bbp_read(rt2x00dev, 47, &value);
5247 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5248 rt2800_bbp_write(rt2x00dev, 47, value);
5249
5250 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5251 rt2800_bbp_read(rt2x00dev, 3, &value);
5252 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5253 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5254 rt2800_bbp_write(rt2x00dev, 3, value);
5255 }
5256
5257 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5258 {
5259 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5260 rt2800_bbp_write(rt2x00dev, 4, 0x50);
5261
5262 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5263
5264 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5265
5266 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5267 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5268
5269 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5270
5271 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5272 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5273 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5274 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5275
5276 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5277
5278 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5279
5280 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5281 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5282 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5283
5284 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5285
5286 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5287
5288 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5289
5290 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5291
5292 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5293
5294 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5295
5296 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5297
5298 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5299
5300 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5301
5302 rt2800_bbp_write(rt2x00dev, 105, 0x34);
5303
5304 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5305
5306 rt2800_bbp_write(rt2x00dev, 120, 0x50);
5307
5308 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5309
5310 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5311 /* Set ITxBF timeout to 0x9c40=1000msec */
5312 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5313 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5314 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5315 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5316 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5317 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5318 /* Reprogram the inband interface to put right values in RXWI */
5319 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5320 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5321 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5322 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5323 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5324 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5325 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5326 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5327
5328 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5329 }
5330
5331 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5332 {
5333 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5334 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5335
5336 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5337 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5338
5339 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5340
5341 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5342 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5343 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5344
5345 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5346
5347 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5348
5349 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5350
5351 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5352
5353 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5354
5355 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5356
5357 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5358 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5359 else
5360 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5361
5362 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5363
5364 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5365
5366 rt2800_disable_unused_dac_adc(rt2x00dev);
5367 }
5368
5369 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5370 {
5371 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5372
5373 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5374 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5375
5376 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5377 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5378
5379 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5380
5381 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5382 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5383 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5384
5385 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5386
5387 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5388
5389 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5390
5391 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5392
5393 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5394
5395 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5396
5397 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5398
5399 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5400
5401 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5402
5403 rt2800_disable_unused_dac_adc(rt2x00dev);
5404 }
5405
5406 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5407 {
5408 rt2800_init_bbp_early(rt2x00dev);
5409
5410 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5411 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5412 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5413 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5414
5415 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5416
5417 /* Enable DC filter */
5418 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5419 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5420 }
5421
5422 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5423 {
5424 int ant, div_mode;
5425 u16 eeprom;
5426 u8 value;
5427
5428 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5429
5430 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5431
5432 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5433 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5434
5435 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5436
5437 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5438 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5439 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5440 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5441
5442 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5443
5444 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5445
5446 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5447 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5448 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5449
5450 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5451
5452 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5453
5454 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5455
5456 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5457
5458 if (rt2x00_rt(rt2x00dev, RT5392))
5459 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5460
5461 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5462
5463 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5464
5465 if (rt2x00_rt(rt2x00dev, RT5392)) {
5466 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5467 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5468 }
5469
5470 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5471
5472 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5473
5474 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5475
5476 if (rt2x00_rt(rt2x00dev, RT5390))
5477 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5478 else if (rt2x00_rt(rt2x00dev, RT5392))
5479 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5480 else
5481 WARN_ON(1);
5482
5483 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5484
5485 if (rt2x00_rt(rt2x00dev, RT5392)) {
5486 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5487 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5488 }
5489
5490 rt2800_disable_unused_dac_adc(rt2x00dev);
5491
5492 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5493 div_mode = rt2x00_get_field16(eeprom,
5494 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5495 ant = (div_mode == 3) ? 1 : 0;
5496
5497 /* check if this is a Bluetooth combo card */
5498 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
5499 u32 reg;
5500
5501 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5502 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5503 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5504 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5505 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5506 if (ant == 0)
5507 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5508 else if (ant == 1)
5509 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5510 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5511 }
5512
5513 /* This chip has hardware antenna diversity*/
5514 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5515 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5516 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5517 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5518 }
5519
5520 rt2800_bbp_read(rt2x00dev, 152, &value);
5521 if (ant == 0)
5522 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5523 else
5524 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5525 rt2800_bbp_write(rt2x00dev, 152, value);
5526
5527 rt2800_init_freq_calibration(rt2x00dev);
5528 }
5529
5530 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5531 {
5532 int ant, div_mode;
5533 u16 eeprom;
5534 u8 value;
5535
5536 rt2800_init_bbp_early(rt2x00dev);
5537
5538 rt2800_bbp_read(rt2x00dev, 105, &value);
5539 rt2x00_set_field8(&value, BBP105_MLD,
5540 rt2x00dev->default_ant.rx_chain_num == 2);
5541 rt2800_bbp_write(rt2x00dev, 105, value);
5542
5543 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5544
5545 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5546 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5547 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5548 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5549 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5550 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5551 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5552 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5553 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5554 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5555 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5556 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5557 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5558 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5559 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5560 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5561 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5562 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5563 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5564 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5565 /* FIXME BBP105 owerwrite */
5566 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5567 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5568 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5569 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5570 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5571 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5572
5573 /* Initialize GLRT (Generalized Likehood Radio Test) */
5574 rt2800_init_bbp_5592_glrt(rt2x00dev);
5575
5576 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5577
5578 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5579 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5580 ant = (div_mode == 3) ? 1 : 0;
5581 rt2800_bbp_read(rt2x00dev, 152, &value);
5582 if (ant == 0) {
5583 /* Main antenna */
5584 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5585 } else {
5586 /* Auxiliary antenna */
5587 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5588 }
5589 rt2800_bbp_write(rt2x00dev, 152, value);
5590
5591 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5592 rt2800_bbp_read(rt2x00dev, 254, &value);
5593 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5594 rt2800_bbp_write(rt2x00dev, 254, value);
5595 }
5596
5597 rt2800_init_freq_calibration(rt2x00dev);
5598
5599 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5600 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5601 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5602 }
5603
5604 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5605 {
5606 unsigned int i;
5607 u16 eeprom;
5608 u8 reg_id;
5609 u8 value;
5610
5611 if (rt2800_is_305x_soc(rt2x00dev))
5612 rt2800_init_bbp_305x_soc(rt2x00dev);
5613
5614 switch (rt2x00dev->chip.rt) {
5615 case RT2860:
5616 case RT2872:
5617 case RT2883:
5618 rt2800_init_bbp_28xx(rt2x00dev);
5619 break;
5620 case RT3070:
5621 case RT3071:
5622 case RT3090:
5623 rt2800_init_bbp_30xx(rt2x00dev);
5624 break;
5625 case RT3290:
5626 rt2800_init_bbp_3290(rt2x00dev);
5627 break;
5628 case RT3352:
5629 rt2800_init_bbp_3352(rt2x00dev);
5630 break;
5631 case RT3390:
5632 rt2800_init_bbp_3390(rt2x00dev);
5633 break;
5634 case RT3572:
5635 rt2800_init_bbp_3572(rt2x00dev);
5636 break;
5637 case RT3593:
5638 rt2800_init_bbp_3593(rt2x00dev);
5639 return;
5640 case RT5390:
5641 case RT5392:
5642 rt2800_init_bbp_53xx(rt2x00dev);
5643 break;
5644 case RT5592:
5645 rt2800_init_bbp_5592(rt2x00dev);
5646 return;
5647 }
5648
5649 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5650 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5651 &eeprom);
5652
5653 if (eeprom != 0xffff && eeprom != 0x0000) {
5654 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5655 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5656 rt2800_bbp_write(rt2x00dev, reg_id, value);
5657 }
5658 }
5659 }
5660
5661 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5662 {
5663 u32 reg;
5664
5665 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5666 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5667 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5668 }
5669
5670 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5671 u8 filter_target)
5672 {
5673 unsigned int i;
5674 u8 bbp;
5675 u8 rfcsr;
5676 u8 passband;
5677 u8 stopband;
5678 u8 overtuned = 0;
5679 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5680
5681 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5682
5683 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5684 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5685 rt2800_bbp_write(rt2x00dev, 4, bbp);
5686
5687 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5688 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5689 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5690
5691 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5692 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5693 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5694
5695 /*
5696 * Set power & frequency of passband test tone
5697 */
5698 rt2800_bbp_write(rt2x00dev, 24, 0);
5699
5700 for (i = 0; i < 100; i++) {
5701 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5702 msleep(1);
5703
5704 rt2800_bbp_read(rt2x00dev, 55, &passband);
5705 if (passband)
5706 break;
5707 }
5708
5709 /*
5710 * Set power & frequency of stopband test tone
5711 */
5712 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5713
5714 for (i = 0; i < 100; i++) {
5715 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5716 msleep(1);
5717
5718 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5719
5720 if ((passband - stopband) <= filter_target) {
5721 rfcsr24++;
5722 overtuned += ((passband - stopband) == filter_target);
5723 } else
5724 break;
5725
5726 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5727 }
5728
5729 rfcsr24 -= !!overtuned;
5730
5731 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5732 return rfcsr24;
5733 }
5734
5735 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5736 const unsigned int rf_reg)
5737 {
5738 u8 rfcsr;
5739
5740 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5741 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5742 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5743 msleep(1);
5744 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5745 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5746 }
5747
5748 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5749 {
5750 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5751 u8 filter_tgt_bw20;
5752 u8 filter_tgt_bw40;
5753 u8 rfcsr, bbp;
5754
5755 /*
5756 * TODO: sync filter_tgt values with vendor driver
5757 */
5758 if (rt2x00_rt(rt2x00dev, RT3070)) {
5759 filter_tgt_bw20 = 0x16;
5760 filter_tgt_bw40 = 0x19;
5761 } else {
5762 filter_tgt_bw20 = 0x13;
5763 filter_tgt_bw40 = 0x15;
5764 }
5765
5766 drv_data->calibration_bw20 =
5767 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5768 drv_data->calibration_bw40 =
5769 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5770
5771 /*
5772 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5773 */
5774 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5775 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5776
5777 /*
5778 * Set back to initial state
5779 */
5780 rt2800_bbp_write(rt2x00dev, 24, 0);
5781
5782 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5783 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5784 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5785
5786 /*
5787 * Set BBP back to BW20
5788 */
5789 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5790 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5791 rt2800_bbp_write(rt2x00dev, 4, bbp);
5792 }
5793
5794 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5795 {
5796 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5797 u8 min_gain, rfcsr, bbp;
5798 u16 eeprom;
5799
5800 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5801
5802 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5803 if (rt2x00_rt(rt2x00dev, RT3070) ||
5804 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5805 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5806 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5807 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
5808 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5809 }
5810
5811 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5812 if (drv_data->txmixer_gain_24g >= min_gain) {
5813 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5814 drv_data->txmixer_gain_24g);
5815 }
5816
5817 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5818
5819 if (rt2x00_rt(rt2x00dev, RT3090)) {
5820 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5821 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5822 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5823 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5824 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5825 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5826 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5827 rt2800_bbp_write(rt2x00dev, 138, bbp);
5828 }
5829
5830 if (rt2x00_rt(rt2x00dev, RT3070)) {
5831 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5832 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5833 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5834 else
5835 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5836 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5837 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5838 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5839 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5840 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5841 rt2x00_rt(rt2x00dev, RT3090) ||
5842 rt2x00_rt(rt2x00dev, RT3390)) {
5843 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5844 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5845 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5846 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5847 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5848 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5849 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5850
5851 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5852 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5853 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5854
5855 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5856 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5857 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5858
5859 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5860 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5861 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5862 }
5863 }
5864
5865 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5866 {
5867 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5868 u8 rfcsr;
5869 u8 tx_gain;
5870
5871 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5872 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5873 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5874
5875 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5876 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5877 RFCSR17_TXMIXER_GAIN);
5878 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5879 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5880
5881 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5882 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5883 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5884
5885 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5886 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5887 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5888
5889 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5890 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5891 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5892 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5893
5894 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5895 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5896 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5897
5898 /* TODO: enable stream mode */
5899 }
5900
5901 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5902 {
5903 u8 reg;
5904 u16 eeprom;
5905
5906 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5907 rt2800_bbp_read(rt2x00dev, 138, &reg);
5908 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5909 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5910 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5911 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5912 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5913 rt2800_bbp_write(rt2x00dev, 138, reg);
5914
5915 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5916 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5917 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5918
5919 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5920 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5921 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5922
5923 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5924
5925 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5926 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5927 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5928 }
5929
5930 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5931 {
5932 rt2800_rf_init_calibration(rt2x00dev, 30);
5933
5934 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5935 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5936 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5937 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5938 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5939 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5940 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5941 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5942 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5943 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5944 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5945 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5946 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5947 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5948 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5949 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5950 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5951 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5952 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5953 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5954 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5955 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5956 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5957 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5958 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5959 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5960 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5961 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5962 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5963 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5964 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5965 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5966 }
5967
5968 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5969 {
5970 u8 rfcsr;
5971 u16 eeprom;
5972 u32 reg;
5973
5974 /* XXX vendor driver do this only for 3070 */
5975 rt2800_rf_init_calibration(rt2x00dev, 30);
5976
5977 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5978 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5979 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5980 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
5981 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5982 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
5983 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5984 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
5985 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5986 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5987 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5988 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5989 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5990 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5991 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5992 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5993 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
5994 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5995 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
5996
5997 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5998 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
5999 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6000 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6001 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6002 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6003 rt2x00_rt(rt2x00dev, RT3090)) {
6004 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6005
6006 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6007 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6008 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6009
6010 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6011 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6012 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6013 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6014 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6015 &eeprom);
6016 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6017 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6018 else
6019 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6020 }
6021 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6022
6023 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6024 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6025 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6026 }
6027
6028 rt2800_rx_filter_calibration(rt2x00dev);
6029
6030 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6031 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6032 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6033 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6034
6035 rt2800_led_open_drain_enable(rt2x00dev);
6036 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6037 }
6038
6039 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6040 {
6041 u8 rfcsr;
6042
6043 rt2800_rf_init_calibration(rt2x00dev, 2);
6044
6045 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6046 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6047 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6048 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6049 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6050 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6051 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6052 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6053 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6054 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6055 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6056 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6057 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6058 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6059 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6060 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6061 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6062 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6063 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6064 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6065 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6066 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6067 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6068 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6069 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6070 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6071 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6072 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6073 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6074 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6075 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6076 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6077 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6078 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6079 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6080 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6081 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6082 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6083 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6084 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6085 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6086 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6087 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6088 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6089 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6090 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6091
6092 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6093 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6094 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6095
6096 rt2800_led_open_drain_enable(rt2x00dev);
6097 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6098 }
6099
6100 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6101 {
6102 rt2800_rf_init_calibration(rt2x00dev, 30);
6103
6104 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6105 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6106 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6107 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6108 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6109 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6110 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6111 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6112 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6113 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6114 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6115 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6116 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6117 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6118 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6119 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6120 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6121 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6122 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6123 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6124 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6125 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6126 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6127 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6128 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6129 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6130 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6131 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6132 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6133 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6134 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6135 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6136 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6137 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6138 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6139 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6140 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6141 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6142 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6143 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6144 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6145 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6146 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6147 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6148 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6149 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6150 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6151 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6152 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6154 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6155 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6156 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6157 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6158 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6159 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6160 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6161 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6162 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6163 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6164 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6165 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6166 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6167
6168 rt2800_rx_filter_calibration(rt2x00dev);
6169 rt2800_led_open_drain_enable(rt2x00dev);
6170 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6171 }
6172
6173 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6174 {
6175 u32 reg;
6176
6177 rt2800_rf_init_calibration(rt2x00dev, 30);
6178
6179 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6180 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6181 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6182 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6183 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6184 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6185 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6186 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6187 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6188 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6189 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6190 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6191 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6192 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6193 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6194 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6195 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6196 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6197 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6198 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6199 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6200 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6201 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6202 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6203 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6204 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6205 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6206 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6207 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6208 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6209 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6210 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6211
6212 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6213 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6214 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6215
6216 rt2800_rx_filter_calibration(rt2x00dev);
6217
6218 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6219 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6220
6221 rt2800_led_open_drain_enable(rt2x00dev);
6222 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6223 }
6224
6225 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6226 {
6227 u8 rfcsr;
6228 u32 reg;
6229
6230 rt2800_rf_init_calibration(rt2x00dev, 30);
6231
6232 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6233 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6234 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6235 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6236 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6237 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6238 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6239 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6240 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6241 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6242 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6243 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6244 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6245 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6246 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6247 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6248 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6249 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6250 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6251 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6252 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6253 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6254 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6255 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6256 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6257 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6258 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6259 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6260 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6261 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6262 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6263
6264 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6265 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6266 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6267
6268 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6269 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6270 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6271 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6272 msleep(1);
6273 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6274 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6275 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6276 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6277
6278 rt2800_rx_filter_calibration(rt2x00dev);
6279 rt2800_led_open_drain_enable(rt2x00dev);
6280 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6281 }
6282
6283 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6284 {
6285 u8 bbp;
6286 bool txbf_enabled = false; /* FIXME */
6287
6288 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6289 if (rt2x00dev->default_ant.rx_chain_num == 1)
6290 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6291 else
6292 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6293 rt2800_bbp_write(rt2x00dev, 105, bbp);
6294
6295 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6296
6297 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6298 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6299 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6300 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6301 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6302 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6303 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6304 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6305
6306 if (txbf_enabled)
6307 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6308 else
6309 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6310
6311 /* SNR mapping */
6312 rt2800_bbp_write(rt2x00dev, 142, 6);
6313 rt2800_bbp_write(rt2x00dev, 143, 160);
6314 rt2800_bbp_write(rt2x00dev, 142, 7);
6315 rt2800_bbp_write(rt2x00dev, 143, 161);
6316 rt2800_bbp_write(rt2x00dev, 142, 8);
6317 rt2800_bbp_write(rt2x00dev, 143, 162);
6318
6319 /* ADC/DAC control */
6320 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6321
6322 /* RX AGC energy lower bound in log2 */
6323 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6324
6325 /* FIXME: BBP 105 owerwrite? */
6326 rt2800_bbp_write(rt2x00dev, 105, 0x04);
6327
6328 }
6329
6330 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6331 {
6332 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6333 u32 reg;
6334 u8 rfcsr;
6335
6336 /* Disable GPIO #4 and #7 function for LAN PE control */
6337 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6338 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6339 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6340 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6341
6342 /* Initialize default register values */
6343 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6344 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6345 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6346 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6347 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6348 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6349 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6350 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6351 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6352 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6353 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6354 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6355 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6356 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6357 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6358 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6359 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6360 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6361 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6362 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6363 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6364 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6365 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6366 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6367 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6368 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6369 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6370 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6371 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6372 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6373 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6374 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6375
6376 /* Initiate calibration */
6377 /* TODO: use rt2800_rf_init_calibration ? */
6378 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6379 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6380 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6381
6382 rt2800_adjust_freq_offset(rt2x00dev);
6383
6384 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6385 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6386 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6387
6388 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6389 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6390 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6391 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6392 usleep_range(1000, 1500);
6393 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6394 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6395 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6396
6397 /* Set initial values for RX filter calibration */
6398 drv_data->calibration_bw20 = 0x1f;
6399 drv_data->calibration_bw40 = 0x2f;
6400
6401 /* Save BBP 25 & 26 values for later use in channel switching */
6402 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6403 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6404
6405 rt2800_led_open_drain_enable(rt2x00dev);
6406 rt2800_normal_mode_setup_3593(rt2x00dev);
6407
6408 rt3593_post_bbp_init(rt2x00dev);
6409
6410 /* TODO: enable stream mode support */
6411 }
6412
6413 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6414 {
6415 rt2800_rf_init_calibration(rt2x00dev, 2);
6416
6417 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6418 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6419 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6420 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6421 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6422 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6423 else
6424 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6425 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6426 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6427 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6428 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
6429 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6430 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6431 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6432 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6433 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6434 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6435
6436 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6437 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6438 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6439 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6440 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6441 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6442 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6443 else
6444 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6445 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6446 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6447 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6448 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6449
6450 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6451 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6452 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6453 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6454 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6455 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6456 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6457 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6458 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6459 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6460
6461 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6462 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6463 else
6464 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
6465 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6466 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6467 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6468 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6469 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6470 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6471 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6472 else
6473 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6474 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6475 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6476 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6477
6478 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6479 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6480 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6481 else
6482 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6483 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6484 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6485 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6486 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6487 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6488 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
6489
6490 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6491 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6492 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6493 else
6494 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6495 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6496 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6497
6498 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6499
6500 rt2800_led_open_drain_enable(rt2x00dev);
6501 }
6502
6503 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6504 {
6505 rt2800_rf_init_calibration(rt2x00dev, 2);
6506
6507 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6508 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6509 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6510 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6511 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6512 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6513 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6514 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6515 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6516 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6517 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6518 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6519 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6520 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6521 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6522 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6523 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6524 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6525 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6526 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6527 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6528 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6529 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6530 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6531 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6532 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6533 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6534 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6535 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6536 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6537 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6538 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6539 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6540 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6541 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6542 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6543 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6544 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6545 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6546 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6547 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6548 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6549 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6550 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6551 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6552 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6553 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6554 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6555 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6556 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6557 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6558 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6559 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6560 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6561 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6562 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6563 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6564 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6565 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6566
6567 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6568
6569 rt2800_led_open_drain_enable(rt2x00dev);
6570 }
6571
6572 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6573 {
6574 rt2800_rf_init_calibration(rt2x00dev, 30);
6575
6576 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6577 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6578 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6579 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6580 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6581 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6582 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6583 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6584 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6585 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6586 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6587 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6588 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6589 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6590 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6591 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6592 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6593 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6594 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6595 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6596 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6597 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6598
6599 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6600 msleep(1);
6601
6602 rt2800_adjust_freq_offset(rt2x00dev);
6603
6604 /* Enable DC filter */
6605 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6606 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6607
6608 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6609
6610 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6611 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6612
6613 rt2800_led_open_drain_enable(rt2x00dev);
6614 }
6615
6616 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6617 {
6618 if (rt2800_is_305x_soc(rt2x00dev)) {
6619 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6620 return;
6621 }
6622
6623 switch (rt2x00dev->chip.rt) {
6624 case RT3070:
6625 case RT3071:
6626 case RT3090:
6627 rt2800_init_rfcsr_30xx(rt2x00dev);
6628 break;
6629 case RT3290:
6630 rt2800_init_rfcsr_3290(rt2x00dev);
6631 break;
6632 case RT3352:
6633 rt2800_init_rfcsr_3352(rt2x00dev);
6634 break;
6635 case RT3390:
6636 rt2800_init_rfcsr_3390(rt2x00dev);
6637 break;
6638 case RT3572:
6639 rt2800_init_rfcsr_3572(rt2x00dev);
6640 break;
6641 case RT3593:
6642 rt2800_init_rfcsr_3593(rt2x00dev);
6643 break;
6644 case RT5390:
6645 rt2800_init_rfcsr_5390(rt2x00dev);
6646 break;
6647 case RT5392:
6648 rt2800_init_rfcsr_5392(rt2x00dev);
6649 break;
6650 case RT5592:
6651 rt2800_init_rfcsr_5592(rt2x00dev);
6652 break;
6653 }
6654 }
6655
6656 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6657 {
6658 u32 reg;
6659 u16 word;
6660
6661 /*
6662 * Initialize all registers.
6663 */
6664 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6665 rt2800_init_registers(rt2x00dev)))
6666 return -EIO;
6667
6668 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6669 return -EIO;
6670
6671 /*
6672 * Send signal to firmware during boot time.
6673 */
6674 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6675 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6676 if (rt2x00_is_usb(rt2x00dev))
6677 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6678 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6679 msleep(1);
6680
6681 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6682 return -EIO;
6683
6684 rt2800_init_bbp(rt2x00dev);
6685 rt2800_init_rfcsr(rt2x00dev);
6686
6687 if (rt2x00_is_usb(rt2x00dev) &&
6688 (rt2x00_rt(rt2x00dev, RT3070) ||
6689 rt2x00_rt(rt2x00dev, RT3071) ||
6690 rt2x00_rt(rt2x00dev, RT3572))) {
6691 udelay(200);
6692 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6693 udelay(10);
6694 }
6695
6696 /*
6697 * Enable RX.
6698 */
6699 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6700 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6701 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6702 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6703
6704 udelay(50);
6705
6706 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6707 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6708 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6709 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6710 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6711 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6712
6713 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6714 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6715 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6716 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6717
6718 /*
6719 * Initialize LED control
6720 */
6721 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6722 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6723 word & 0xff, (word >> 8) & 0xff);
6724
6725 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6726 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6727 word & 0xff, (word >> 8) & 0xff);
6728
6729 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6730 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6731 word & 0xff, (word >> 8) & 0xff);
6732
6733 return 0;
6734 }
6735 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6736
6737 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6738 {
6739 u32 reg;
6740
6741 rt2800_disable_wpdma(rt2x00dev);
6742
6743 /* Wait for DMA, ignore error */
6744 rt2800_wait_wpdma_ready(rt2x00dev);
6745
6746 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6747 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6748 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6749 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6750 }
6751 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6752
6753 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6754 {
6755 u32 reg;
6756 u16 efuse_ctrl_reg;
6757
6758 if (rt2x00_rt(rt2x00dev, RT3290))
6759 efuse_ctrl_reg = EFUSE_CTRL_3290;
6760 else
6761 efuse_ctrl_reg = EFUSE_CTRL;
6762
6763 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6764 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6765 }
6766 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6767
6768 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6769 {
6770 u32 reg;
6771 u16 efuse_ctrl_reg;
6772 u16 efuse_data0_reg;
6773 u16 efuse_data1_reg;
6774 u16 efuse_data2_reg;
6775 u16 efuse_data3_reg;
6776
6777 if (rt2x00_rt(rt2x00dev, RT3290)) {
6778 efuse_ctrl_reg = EFUSE_CTRL_3290;
6779 efuse_data0_reg = EFUSE_DATA0_3290;
6780 efuse_data1_reg = EFUSE_DATA1_3290;
6781 efuse_data2_reg = EFUSE_DATA2_3290;
6782 efuse_data3_reg = EFUSE_DATA3_3290;
6783 } else {
6784 efuse_ctrl_reg = EFUSE_CTRL;
6785 efuse_data0_reg = EFUSE_DATA0;
6786 efuse_data1_reg = EFUSE_DATA1;
6787 efuse_data2_reg = EFUSE_DATA2;
6788 efuse_data3_reg = EFUSE_DATA3;
6789 }
6790 mutex_lock(&rt2x00dev->csr_mutex);
6791
6792 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6793 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6794 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6795 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6796 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6797
6798 /* Wait until the EEPROM has been loaded */
6799 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6800 /* Apparently the data is read from end to start */
6801 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6802 /* The returned value is in CPU order, but eeprom is le */
6803 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6804 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6805 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6806 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6807 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6808 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6809 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6810
6811 mutex_unlock(&rt2x00dev->csr_mutex);
6812 }
6813
6814 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6815 {
6816 unsigned int i;
6817
6818 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6819 rt2800_efuse_read(rt2x00dev, i);
6820
6821 return 0;
6822 }
6823 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6824
6825 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6826 {
6827 u16 word;
6828
6829 if (rt2x00_rt(rt2x00dev, RT3593))
6830 return 0;
6831
6832 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6833 if ((word & 0x00ff) != 0x00ff)
6834 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6835
6836 return 0;
6837 }
6838
6839 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6840 {
6841 u16 word;
6842
6843 if (rt2x00_rt(rt2x00dev, RT3593))
6844 return 0;
6845
6846 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6847 if ((word & 0x00ff) != 0x00ff)
6848 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6849
6850 return 0;
6851 }
6852
6853 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6854 {
6855 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6856 u16 word;
6857 u8 *mac;
6858 u8 default_lna_gain;
6859 int retval;
6860
6861 /*
6862 * Read the EEPROM.
6863 */
6864 retval = rt2800_read_eeprom(rt2x00dev);
6865 if (retval)
6866 return retval;
6867
6868 /*
6869 * Start validation of the data that has been read.
6870 */
6871 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6872 if (!is_valid_ether_addr(mac)) {
6873 eth_random_addr(mac);
6874 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6875 }
6876
6877 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6878 if (word == 0xffff) {
6879 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6880 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6881 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6882 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6883 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6884 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6885 rt2x00_rt(rt2x00dev, RT2872)) {
6886 /*
6887 * There is a max of 2 RX streams for RT28x0 series
6888 */
6889 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6890 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6891 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6892 }
6893
6894 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6895 if (word == 0xffff) {
6896 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6897 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6898 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6899 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6900 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6901 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6902 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6903 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6904 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6905 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6906 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6907 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6908 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6909 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6910 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6911 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6912 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6913 }
6914
6915 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6916 if ((word & 0x00ff) == 0x00ff) {
6917 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6918 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6919 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6920 }
6921 if ((word & 0xff00) == 0xff00) {
6922 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6923 LED_MODE_TXRX_ACTIVITY);
6924 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6925 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6926 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6927 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6928 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6929 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6930 }
6931
6932 /*
6933 * During the LNA validation we are going to use
6934 * lna0 as correct value. Note that EEPROM_LNA
6935 * is never validated.
6936 */
6937 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6938 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6939
6940 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6941 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6942 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6943 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6944 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6945 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6946
6947 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6948
6949 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6950 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6951 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6952 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6953 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6954 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6955 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6956 default_lna_gain);
6957 }
6958 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6959
6960 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
6961
6962 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6963 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6964 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6965 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6966 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6967 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6968
6969 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6970 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6971 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6972 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6973 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6974 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6975 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6976 default_lna_gain);
6977 }
6978 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6979
6980 if (rt2x00_rt(rt2x00dev, RT3593)) {
6981 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
6982 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
6983 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
6984 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6985 default_lna_gain);
6986 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
6987 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
6988 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
6989 default_lna_gain);
6990 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
6991 }
6992
6993 return 0;
6994 }
6995
6996 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
6997 {
6998 u16 value;
6999 u16 eeprom;
7000 u16 rf;
7001
7002 /*
7003 * Read EEPROM word for configuration.
7004 */
7005 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7006
7007 /*
7008 * Identify RF chipset by EEPROM value
7009 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7010 * RT53xx: defined in "EEPROM_CHIP_ID" field
7011 */
7012 if (rt2x00_rt(rt2x00dev, RT3290) ||
7013 rt2x00_rt(rt2x00dev, RT5390) ||
7014 rt2x00_rt(rt2x00dev, RT5392))
7015 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7016 else
7017 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7018
7019 switch (rf) {
7020 case RF2820:
7021 case RF2850:
7022 case RF2720:
7023 case RF2750:
7024 case RF3020:
7025 case RF2020:
7026 case RF3021:
7027 case RF3022:
7028 case RF3052:
7029 case RF3053:
7030 case RF3070:
7031 case RF3290:
7032 case RF3320:
7033 case RF3322:
7034 case RF5360:
7035 case RF5370:
7036 case RF5372:
7037 case RF5390:
7038 case RF5392:
7039 case RF5592:
7040 break;
7041 default:
7042 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7043 rf);
7044 return -ENODEV;
7045 }
7046
7047 rt2x00_set_rf(rt2x00dev, rf);
7048
7049 /*
7050 * Identify default antenna configuration.
7051 */
7052 rt2x00dev->default_ant.tx_chain_num =
7053 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7054 rt2x00dev->default_ant.rx_chain_num =
7055 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7056
7057 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7058
7059 if (rt2x00_rt(rt2x00dev, RT3070) ||
7060 rt2x00_rt(rt2x00dev, RT3090) ||
7061 rt2x00_rt(rt2x00dev, RT3352) ||
7062 rt2x00_rt(rt2x00dev, RT3390)) {
7063 value = rt2x00_get_field16(eeprom,
7064 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7065 switch (value) {
7066 case 0:
7067 case 1:
7068 case 2:
7069 rt2x00dev->default_ant.tx = ANTENNA_A;
7070 rt2x00dev->default_ant.rx = ANTENNA_A;
7071 break;
7072 case 3:
7073 rt2x00dev->default_ant.tx = ANTENNA_A;
7074 rt2x00dev->default_ant.rx = ANTENNA_B;
7075 break;
7076 }
7077 } else {
7078 rt2x00dev->default_ant.tx = ANTENNA_A;
7079 rt2x00dev->default_ant.rx = ANTENNA_A;
7080 }
7081
7082 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7083 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7084 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7085 }
7086
7087 /*
7088 * Determine external LNA informations.
7089 */
7090 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7091 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7092 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7093 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7094
7095 /*
7096 * Detect if this device has an hardware controlled radio.
7097 */
7098 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7099 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7100
7101 /*
7102 * Detect if this device has Bluetooth co-existence.
7103 */
7104 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7105 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7106
7107 /*
7108 * Read frequency offset and RF programming sequence.
7109 */
7110 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7111 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7112
7113 /*
7114 * Store led settings, for correct led behaviour.
7115 */
7116 #ifdef CONFIG_RT2X00_LIB_LEDS
7117 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7118 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7119 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7120
7121 rt2x00dev->led_mcu_reg = eeprom;
7122 #endif /* CONFIG_RT2X00_LIB_LEDS */
7123
7124 /*
7125 * Check if support EIRP tx power limit feature.
7126 */
7127 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7128
7129 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7130 EIRP_MAX_TX_POWER_LIMIT)
7131 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7132
7133 return 0;
7134 }
7135
7136 /*
7137 * RF value list for rt28xx
7138 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7139 */
7140 static const struct rf_channel rf_vals[] = {
7141 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7142 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7143 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7144 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7145 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7146 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7147 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7148 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7149 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7150 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7151 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7152 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7153 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7154 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7155
7156 /* 802.11 UNI / HyperLan 2 */
7157 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7158 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7159 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7160 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7161 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7162 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7163 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7164 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7165 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7166 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7167 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7168 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7169
7170 /* 802.11 HyperLan 2 */
7171 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7172 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7173 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7174 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7175 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7176 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7177 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7178 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7179 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7180 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7181 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7182 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7183 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7184 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7185 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7186 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7187
7188 /* 802.11 UNII */
7189 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7190 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7191 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7192 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7193 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7194 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7195 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7196 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7197 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7198 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7199 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7200
7201 /* 802.11 Japan */
7202 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7203 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7204 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7205 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7206 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7207 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7208 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7209 };
7210
7211 /*
7212 * RF value list for rt3xxx
7213 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
7214 */
7215 static const struct rf_channel rf_vals_3x[] = {
7216 {1, 241, 2, 2 },
7217 {2, 241, 2, 7 },
7218 {3, 242, 2, 2 },
7219 {4, 242, 2, 7 },
7220 {5, 243, 2, 2 },
7221 {6, 243, 2, 7 },
7222 {7, 244, 2, 2 },
7223 {8, 244, 2, 7 },
7224 {9, 245, 2, 2 },
7225 {10, 245, 2, 7 },
7226 {11, 246, 2, 2 },
7227 {12, 246, 2, 7 },
7228 {13, 247, 2, 2 },
7229 {14, 248, 2, 4 },
7230
7231 /* 802.11 UNI / HyperLan 2 */
7232 {36, 0x56, 0, 4},
7233 {38, 0x56, 0, 6},
7234 {40, 0x56, 0, 8},
7235 {44, 0x57, 0, 0},
7236 {46, 0x57, 0, 2},
7237 {48, 0x57, 0, 4},
7238 {52, 0x57, 0, 8},
7239 {54, 0x57, 0, 10},
7240 {56, 0x58, 0, 0},
7241 {60, 0x58, 0, 4},
7242 {62, 0x58, 0, 6},
7243 {64, 0x58, 0, 8},
7244
7245 /* 802.11 HyperLan 2 */
7246 {100, 0x5b, 0, 8},
7247 {102, 0x5b, 0, 10},
7248 {104, 0x5c, 0, 0},
7249 {108, 0x5c, 0, 4},
7250 {110, 0x5c, 0, 6},
7251 {112, 0x5c, 0, 8},
7252 {116, 0x5d, 0, 0},
7253 {118, 0x5d, 0, 2},
7254 {120, 0x5d, 0, 4},
7255 {124, 0x5d, 0, 8},
7256 {126, 0x5d, 0, 10},
7257 {128, 0x5e, 0, 0},
7258 {132, 0x5e, 0, 4},
7259 {134, 0x5e, 0, 6},
7260 {136, 0x5e, 0, 8},
7261 {140, 0x5f, 0, 0},
7262
7263 /* 802.11 UNII */
7264 {149, 0x5f, 0, 9},
7265 {151, 0x5f, 0, 11},
7266 {153, 0x60, 0, 1},
7267 {157, 0x60, 0, 5},
7268 {159, 0x60, 0, 7},
7269 {161, 0x60, 0, 9},
7270 {165, 0x61, 0, 1},
7271 {167, 0x61, 0, 3},
7272 {169, 0x61, 0, 5},
7273 {171, 0x61, 0, 7},
7274 {173, 0x61, 0, 9},
7275 };
7276
7277 static const struct rf_channel rf_vals_5592_xtal20[] = {
7278 /* Channel, N, K, mod, R */
7279 {1, 482, 4, 10, 3},
7280 {2, 483, 4, 10, 3},
7281 {3, 484, 4, 10, 3},
7282 {4, 485, 4, 10, 3},
7283 {5, 486, 4, 10, 3},
7284 {6, 487, 4, 10, 3},
7285 {7, 488, 4, 10, 3},
7286 {8, 489, 4, 10, 3},
7287 {9, 490, 4, 10, 3},
7288 {10, 491, 4, 10, 3},
7289 {11, 492, 4, 10, 3},
7290 {12, 493, 4, 10, 3},
7291 {13, 494, 4, 10, 3},
7292 {14, 496, 8, 10, 3},
7293 {36, 172, 8, 12, 1},
7294 {38, 173, 0, 12, 1},
7295 {40, 173, 4, 12, 1},
7296 {42, 173, 8, 12, 1},
7297 {44, 174, 0, 12, 1},
7298 {46, 174, 4, 12, 1},
7299 {48, 174, 8, 12, 1},
7300 {50, 175, 0, 12, 1},
7301 {52, 175, 4, 12, 1},
7302 {54, 175, 8, 12, 1},
7303 {56, 176, 0, 12, 1},
7304 {58, 176, 4, 12, 1},
7305 {60, 176, 8, 12, 1},
7306 {62, 177, 0, 12, 1},
7307 {64, 177, 4, 12, 1},
7308 {100, 183, 4, 12, 1},
7309 {102, 183, 8, 12, 1},
7310 {104, 184, 0, 12, 1},
7311 {106, 184, 4, 12, 1},
7312 {108, 184, 8, 12, 1},
7313 {110, 185, 0, 12, 1},
7314 {112, 185, 4, 12, 1},
7315 {114, 185, 8, 12, 1},
7316 {116, 186, 0, 12, 1},
7317 {118, 186, 4, 12, 1},
7318 {120, 186, 8, 12, 1},
7319 {122, 187, 0, 12, 1},
7320 {124, 187, 4, 12, 1},
7321 {126, 187, 8, 12, 1},
7322 {128, 188, 0, 12, 1},
7323 {130, 188, 4, 12, 1},
7324 {132, 188, 8, 12, 1},
7325 {134, 189, 0, 12, 1},
7326 {136, 189, 4, 12, 1},
7327 {138, 189, 8, 12, 1},
7328 {140, 190, 0, 12, 1},
7329 {149, 191, 6, 12, 1},
7330 {151, 191, 10, 12, 1},
7331 {153, 192, 2, 12, 1},
7332 {155, 192, 6, 12, 1},
7333 {157, 192, 10, 12, 1},
7334 {159, 193, 2, 12, 1},
7335 {161, 193, 6, 12, 1},
7336 {165, 194, 2, 12, 1},
7337 {184, 164, 0, 12, 1},
7338 {188, 164, 4, 12, 1},
7339 {192, 165, 8, 12, 1},
7340 {196, 166, 0, 12, 1},
7341 };
7342
7343 static const struct rf_channel rf_vals_5592_xtal40[] = {
7344 /* Channel, N, K, mod, R */
7345 {1, 241, 2, 10, 3},
7346 {2, 241, 7, 10, 3},
7347 {3, 242, 2, 10, 3},
7348 {4, 242, 7, 10, 3},
7349 {5, 243, 2, 10, 3},
7350 {6, 243, 7, 10, 3},
7351 {7, 244, 2, 10, 3},
7352 {8, 244, 7, 10, 3},
7353 {9, 245, 2, 10, 3},
7354 {10, 245, 7, 10, 3},
7355 {11, 246, 2, 10, 3},
7356 {12, 246, 7, 10, 3},
7357 {13, 247, 2, 10, 3},
7358 {14, 248, 4, 10, 3},
7359 {36, 86, 4, 12, 1},
7360 {38, 86, 6, 12, 1},
7361 {40, 86, 8, 12, 1},
7362 {42, 86, 10, 12, 1},
7363 {44, 87, 0, 12, 1},
7364 {46, 87, 2, 12, 1},
7365 {48, 87, 4, 12, 1},
7366 {50, 87, 6, 12, 1},
7367 {52, 87, 8, 12, 1},
7368 {54, 87, 10, 12, 1},
7369 {56, 88, 0, 12, 1},
7370 {58, 88, 2, 12, 1},
7371 {60, 88, 4, 12, 1},
7372 {62, 88, 6, 12, 1},
7373 {64, 88, 8, 12, 1},
7374 {100, 91, 8, 12, 1},
7375 {102, 91, 10, 12, 1},
7376 {104, 92, 0, 12, 1},
7377 {106, 92, 2, 12, 1},
7378 {108, 92, 4, 12, 1},
7379 {110, 92, 6, 12, 1},
7380 {112, 92, 8, 12, 1},
7381 {114, 92, 10, 12, 1},
7382 {116, 93, 0, 12, 1},
7383 {118, 93, 2, 12, 1},
7384 {120, 93, 4, 12, 1},
7385 {122, 93, 6, 12, 1},
7386 {124, 93, 8, 12, 1},
7387 {126, 93, 10, 12, 1},
7388 {128, 94, 0, 12, 1},
7389 {130, 94, 2, 12, 1},
7390 {132, 94, 4, 12, 1},
7391 {134, 94, 6, 12, 1},
7392 {136, 94, 8, 12, 1},
7393 {138, 94, 10, 12, 1},
7394 {140, 95, 0, 12, 1},
7395 {149, 95, 9, 12, 1},
7396 {151, 95, 11, 12, 1},
7397 {153, 96, 1, 12, 1},
7398 {155, 96, 3, 12, 1},
7399 {157, 96, 5, 12, 1},
7400 {159, 96, 7, 12, 1},
7401 {161, 96, 9, 12, 1},
7402 {165, 97, 1, 12, 1},
7403 {184, 82, 0, 12, 1},
7404 {188, 82, 4, 12, 1},
7405 {192, 82, 8, 12, 1},
7406 {196, 83, 0, 12, 1},
7407 };
7408
7409 static const struct rf_channel rf_vals_3053[] = {
7410 /* Channel, N, R, K */
7411 {1, 241, 2, 2},
7412 {2, 241, 2, 7},
7413 {3, 242, 2, 2},
7414 {4, 242, 2, 7},
7415 {5, 243, 2, 2},
7416 {6, 243, 2, 7},
7417 {7, 244, 2, 2},
7418 {8, 244, 2, 7},
7419 {9, 245, 2, 2},
7420 {10, 245, 2, 7},
7421 {11, 246, 2, 2},
7422 {12, 246, 2, 7},
7423 {13, 247, 2, 2},
7424 {14, 248, 2, 4},
7425
7426 {36, 0x56, 0, 4},
7427 {38, 0x56, 0, 6},
7428 {40, 0x56, 0, 8},
7429 {44, 0x57, 0, 0},
7430 {46, 0x57, 0, 2},
7431 {48, 0x57, 0, 4},
7432 {52, 0x57, 0, 8},
7433 {54, 0x57, 0, 10},
7434 {56, 0x58, 0, 0},
7435 {60, 0x58, 0, 4},
7436 {62, 0x58, 0, 6},
7437 {64, 0x58, 0, 8},
7438
7439 {100, 0x5B, 0, 8},
7440 {102, 0x5B, 0, 10},
7441 {104, 0x5C, 0, 0},
7442 {108, 0x5C, 0, 4},
7443 {110, 0x5C, 0, 6},
7444 {112, 0x5C, 0, 8},
7445
7446 /* NOTE: Channel 114 has been removed intentionally.
7447 * The EEPROM contains no TX power values for that,
7448 * and it is disabled in the vendor driver as well.
7449 */
7450
7451 {116, 0x5D, 0, 0},
7452 {118, 0x5D, 0, 2},
7453 {120, 0x5D, 0, 4},
7454 {124, 0x5D, 0, 8},
7455 {126, 0x5D, 0, 10},
7456 {128, 0x5E, 0, 0},
7457 {132, 0x5E, 0, 4},
7458 {134, 0x5E, 0, 6},
7459 {136, 0x5E, 0, 8},
7460 {140, 0x5F, 0, 0},
7461
7462 {149, 0x5F, 0, 9},
7463 {151, 0x5F, 0, 11},
7464 {153, 0x60, 0, 1},
7465 {157, 0x60, 0, 5},
7466 {159, 0x60, 0, 7},
7467 {161, 0x60, 0, 9},
7468 {165, 0x61, 0, 1},
7469 {167, 0x61, 0, 3},
7470 {169, 0x61, 0, 5},
7471 {171, 0x61, 0, 7},
7472 {173, 0x61, 0, 9},
7473 };
7474
7475 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7476 {
7477 struct hw_mode_spec *spec = &rt2x00dev->spec;
7478 struct channel_info *info;
7479 char *default_power1;
7480 char *default_power2;
7481 char *default_power3;
7482 unsigned int i;
7483 u16 eeprom;
7484 u32 reg;
7485
7486 /*
7487 * Disable powersaving as default on PCI devices.
7488 */
7489 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
7490 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7491
7492 /*
7493 * Initialize all hw fields.
7494 */
7495 rt2x00dev->hw->flags =
7496 IEEE80211_HW_SIGNAL_DBM |
7497 IEEE80211_HW_SUPPORTS_PS |
7498 IEEE80211_HW_PS_NULLFUNC_STACK |
7499 IEEE80211_HW_AMPDU_AGGREGATION |
7500 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7501 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7502
7503 /*
7504 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7505 * unless we are capable of sending the buffered frames out after the
7506 * DTIM transmission using rt2x00lib_beacondone. This will send out
7507 * multicast and broadcast traffic immediately instead of buffering it
7508 * infinitly and thus dropping it after some time.
7509 */
7510 if (!rt2x00_is_usb(rt2x00dev))
7511 rt2x00dev->hw->flags |=
7512 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7513
7514 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7515 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7516 rt2800_eeprom_addr(rt2x00dev,
7517 EEPROM_MAC_ADDR_0));
7518
7519 /*
7520 * As rt2800 has a global fallback table we cannot specify
7521 * more then one tx rate per frame but since the hw will
7522 * try several rates (based on the fallback table) we should
7523 * initialize max_report_rates to the maximum number of rates
7524 * we are going to try. Otherwise mac80211 will truncate our
7525 * reported tx rates and the rc algortihm will end up with
7526 * incorrect data.
7527 */
7528 rt2x00dev->hw->max_rates = 1;
7529 rt2x00dev->hw->max_report_rates = 7;
7530 rt2x00dev->hw->max_rate_tries = 1;
7531
7532 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7533
7534 /*
7535 * Initialize hw_mode information.
7536 */
7537 spec->supported_bands = SUPPORT_BAND_2GHZ;
7538 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7539
7540 if (rt2x00_rf(rt2x00dev, RF2820) ||
7541 rt2x00_rf(rt2x00dev, RF2720)) {
7542 spec->num_channels = 14;
7543 spec->channels = rf_vals;
7544 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
7545 rt2x00_rf(rt2x00dev, RF2750)) {
7546 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7547 spec->num_channels = ARRAY_SIZE(rf_vals);
7548 spec->channels = rf_vals;
7549 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
7550 rt2x00_rf(rt2x00dev, RF2020) ||
7551 rt2x00_rf(rt2x00dev, RF3021) ||
7552 rt2x00_rf(rt2x00dev, RF3022) ||
7553 rt2x00_rf(rt2x00dev, RF3070) ||
7554 rt2x00_rf(rt2x00dev, RF3290) ||
7555 rt2x00_rf(rt2x00dev, RF3320) ||
7556 rt2x00_rf(rt2x00dev, RF3322) ||
7557 rt2x00_rf(rt2x00dev, RF5360) ||
7558 rt2x00_rf(rt2x00dev, RF5370) ||
7559 rt2x00_rf(rt2x00dev, RF5372) ||
7560 rt2x00_rf(rt2x00dev, RF5390) ||
7561 rt2x00_rf(rt2x00dev, RF5392)) {
7562 spec->num_channels = 14;
7563 spec->channels = rf_vals_3x;
7564 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
7565 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7566 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7567 spec->channels = rf_vals_3x;
7568 } else if (rt2x00_rf(rt2x00dev, RF3053)) {
7569 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7570 spec->num_channels = ARRAY_SIZE(rf_vals_3053);
7571 spec->channels = rf_vals_3053;
7572 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
7573 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7574
7575 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7576 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7577 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7578 spec->channels = rf_vals_5592_xtal40;
7579 } else {
7580 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7581 spec->channels = rf_vals_5592_xtal20;
7582 }
7583 }
7584
7585 if (WARN_ON_ONCE(!spec->channels))
7586 return -ENODEV;
7587
7588 /*
7589 * Initialize HT information.
7590 */
7591 if (!rt2x00_rf(rt2x00dev, RF2020))
7592 spec->ht.ht_supported = true;
7593 else
7594 spec->ht.ht_supported = false;
7595
7596 spec->ht.cap =
7597 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7598 IEEE80211_HT_CAP_GRN_FLD |
7599 IEEE80211_HT_CAP_SGI_20 |
7600 IEEE80211_HT_CAP_SGI_40;
7601
7602 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
7603 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7604
7605 spec->ht.cap |=
7606 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
7607 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7608
7609 spec->ht.ampdu_factor = 3;
7610 spec->ht.ampdu_density = 4;
7611 spec->ht.mcs.tx_params =
7612 IEEE80211_HT_MCS_TX_DEFINED |
7613 IEEE80211_HT_MCS_TX_RX_DIFF |
7614 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
7615 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7616
7617 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
7618 case 3:
7619 spec->ht.mcs.rx_mask[2] = 0xff;
7620 case 2:
7621 spec->ht.mcs.rx_mask[1] = 0xff;
7622 case 1:
7623 spec->ht.mcs.rx_mask[0] = 0xff;
7624 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7625 break;
7626 }
7627
7628 /*
7629 * Create channel information array
7630 */
7631 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7632 if (!info)
7633 return -ENOMEM;
7634
7635 spec->channels_info = info;
7636
7637 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7638 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7639
7640 if (rt2x00dev->default_ant.tx_chain_num > 2)
7641 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7642 EEPROM_EXT_TXPOWER_BG3);
7643 else
7644 default_power3 = NULL;
7645
7646 for (i = 0; i < 14; i++) {
7647 info[i].default_power1 = default_power1[i];
7648 info[i].default_power2 = default_power2[i];
7649 if (default_power3)
7650 info[i].default_power3 = default_power3[i];
7651 }
7652
7653 if (spec->num_channels > 14) {
7654 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7655 EEPROM_TXPOWER_A1);
7656 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7657 EEPROM_TXPOWER_A2);
7658
7659 if (rt2x00dev->default_ant.tx_chain_num > 2)
7660 default_power3 =
7661 rt2800_eeprom_addr(rt2x00dev,
7662 EEPROM_EXT_TXPOWER_A3);
7663 else
7664 default_power3 = NULL;
7665
7666 for (i = 14; i < spec->num_channels; i++) {
7667 info[i].default_power1 = default_power1[i - 14];
7668 info[i].default_power2 = default_power2[i - 14];
7669 if (default_power3)
7670 info[i].default_power3 = default_power3[i - 14];
7671 }
7672 }
7673
7674 switch (rt2x00dev->chip.rf) {
7675 case RF2020:
7676 case RF3020:
7677 case RF3021:
7678 case RF3022:
7679 case RF3320:
7680 case RF3052:
7681 case RF3053:
7682 case RF3070:
7683 case RF3290:
7684 case RF5360:
7685 case RF5370:
7686 case RF5372:
7687 case RF5390:
7688 case RF5392:
7689 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7690 break;
7691 }
7692
7693 return 0;
7694 }
7695
7696 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7697 {
7698 u32 reg;
7699 u32 rt;
7700 u32 rev;
7701
7702 if (rt2x00_rt(rt2x00dev, RT3290))
7703 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7704 else
7705 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7706
7707 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7708 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7709
7710 switch (rt) {
7711 case RT2860:
7712 case RT2872:
7713 case RT2883:
7714 case RT3070:
7715 case RT3071:
7716 case RT3090:
7717 case RT3290:
7718 case RT3352:
7719 case RT3390:
7720 case RT3572:
7721 case RT3593:
7722 case RT5390:
7723 case RT5392:
7724 case RT5592:
7725 break;
7726 default:
7727 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7728 rt, rev);
7729 return -ENODEV;
7730 }
7731
7732 rt2x00_set_rt(rt2x00dev, rt, rev);
7733
7734 return 0;
7735 }
7736
7737 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7738 {
7739 int retval;
7740 u32 reg;
7741
7742 retval = rt2800_probe_rt(rt2x00dev);
7743 if (retval)
7744 return retval;
7745
7746 /*
7747 * Allocate eeprom data.
7748 */
7749 retval = rt2800_validate_eeprom(rt2x00dev);
7750 if (retval)
7751 return retval;
7752
7753 retval = rt2800_init_eeprom(rt2x00dev);
7754 if (retval)
7755 return retval;
7756
7757 /*
7758 * Enable rfkill polling by setting GPIO direction of the
7759 * rfkill switch GPIO pin correctly.
7760 */
7761 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7762 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7763 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7764
7765 /*
7766 * Initialize hw specifications.
7767 */
7768 retval = rt2800_probe_hw_mode(rt2x00dev);
7769 if (retval)
7770 return retval;
7771
7772 /*
7773 * Set device capabilities.
7774 */
7775 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7776 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7777 if (!rt2x00_is_usb(rt2x00dev))
7778 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7779
7780 /*
7781 * Set device requirements.
7782 */
7783 if (!rt2x00_is_soc(rt2x00dev))
7784 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7785 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7786 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7787 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7788 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7789 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7790 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7791 if (rt2x00_is_usb(rt2x00dev))
7792 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7793 else {
7794 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7795 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7796 }
7797
7798 /*
7799 * Set the rssi offset.
7800 */
7801 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7802
7803 return 0;
7804 }
7805 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7806
7807 /*
7808 * IEEE80211 stack callback functions.
7809 */
7810 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7811 u16 *iv16)
7812 {
7813 struct rt2x00_dev *rt2x00dev = hw->priv;
7814 struct mac_iveiv_entry iveiv_entry;
7815 u32 offset;
7816
7817 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7818 rt2800_register_multiread(rt2x00dev, offset,
7819 &iveiv_entry, sizeof(iveiv_entry));
7820
7821 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7822 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7823 }
7824 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7825
7826 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7827 {
7828 struct rt2x00_dev *rt2x00dev = hw->priv;
7829 u32 reg;
7830 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7831
7832 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7833 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7834 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7835
7836 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7837 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7838 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7839
7840 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7841 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7842 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7843
7844 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7845 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7846 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7847
7848 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7849 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7850 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7851
7852 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7853 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7854 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7855
7856 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7857 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7858 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7859
7860 return 0;
7861 }
7862 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7863
7864 int rt2800_conf_tx(struct ieee80211_hw *hw,
7865 struct ieee80211_vif *vif, u16 queue_idx,
7866 const struct ieee80211_tx_queue_params *params)
7867 {
7868 struct rt2x00_dev *rt2x00dev = hw->priv;
7869 struct data_queue *queue;
7870 struct rt2x00_field32 field;
7871 int retval;
7872 u32 reg;
7873 u32 offset;
7874
7875 /*
7876 * First pass the configuration through rt2x00lib, that will
7877 * update the queue settings and validate the input. After that
7878 * we are free to update the registers based on the value
7879 * in the queue parameter.
7880 */
7881 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7882 if (retval)
7883 return retval;
7884
7885 /*
7886 * We only need to perform additional register initialization
7887 * for WMM queues/
7888 */
7889 if (queue_idx >= 4)
7890 return 0;
7891
7892 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7893
7894 /* Update WMM TXOP register */
7895 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7896 field.bit_offset = (queue_idx & 1) * 16;
7897 field.bit_mask = 0xffff << field.bit_offset;
7898
7899 rt2800_register_read(rt2x00dev, offset, &reg);
7900 rt2x00_set_field32(&reg, field, queue->txop);
7901 rt2800_register_write(rt2x00dev, offset, reg);
7902
7903 /* Update WMM registers */
7904 field.bit_offset = queue_idx * 4;
7905 field.bit_mask = 0xf << field.bit_offset;
7906
7907 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7908 rt2x00_set_field32(&reg, field, queue->aifs);
7909 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7910
7911 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7912 rt2x00_set_field32(&reg, field, queue->cw_min);
7913 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7914
7915 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7916 rt2x00_set_field32(&reg, field, queue->cw_max);
7917 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7918
7919 /* Update EDCA registers */
7920 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7921
7922 rt2800_register_read(rt2x00dev, offset, &reg);
7923 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7924 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7925 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7926 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7927 rt2800_register_write(rt2x00dev, offset, reg);
7928
7929 return 0;
7930 }
7931 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7932
7933 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7934 {
7935 struct rt2x00_dev *rt2x00dev = hw->priv;
7936 u64 tsf;
7937 u32 reg;
7938
7939 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7940 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7941 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7942 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7943
7944 return tsf;
7945 }
7946 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7947
7948 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7949 enum ieee80211_ampdu_mlme_action action,
7950 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7951 u8 buf_size)
7952 {
7953 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7954 int ret = 0;
7955
7956 /*
7957 * Don't allow aggregation for stations the hardware isn't aware
7958 * of because tx status reports for frames to an unknown station
7959 * always contain wcid=255 and thus we can't distinguish between
7960 * multiple stations which leads to unwanted situations when the
7961 * hw reorders frames due to aggregation.
7962 */
7963 if (sta_priv->wcid < 0)
7964 return 1;
7965
7966 switch (action) {
7967 case IEEE80211_AMPDU_RX_START:
7968 case IEEE80211_AMPDU_RX_STOP:
7969 /*
7970 * The hw itself takes care of setting up BlockAck mechanisms.
7971 * So, we only have to allow mac80211 to nagotiate a BlockAck
7972 * agreement. Once that is done, the hw will BlockAck incoming
7973 * AMPDUs without further setup.
7974 */
7975 break;
7976 case IEEE80211_AMPDU_TX_START:
7977 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7978 break;
7979 case IEEE80211_AMPDU_TX_STOP_CONT:
7980 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7981 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7982 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7983 break;
7984 case IEEE80211_AMPDU_TX_OPERATIONAL:
7985 break;
7986 default:
7987 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7988 "Unknown AMPDU action\n");
7989 }
7990
7991 return ret;
7992 }
7993 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7994
7995 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7996 struct survey_info *survey)
7997 {
7998 struct rt2x00_dev *rt2x00dev = hw->priv;
7999 struct ieee80211_conf *conf = &hw->conf;
8000 u32 idle, busy, busy_ext;
8001
8002 if (idx != 0)
8003 return -ENOENT;
8004
8005 survey->channel = conf->chandef.chan;
8006
8007 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8008 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8009 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8010
8011 if (idle || busy) {
8012 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8013 SURVEY_INFO_CHANNEL_TIME_BUSY |
8014 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8015
8016 survey->channel_time = (idle + busy) / 1000;
8017 survey->channel_time_busy = busy / 1000;
8018 survey->channel_time_ext_busy = busy_ext / 1000;
8019 }
8020
8021 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8022 survey->filled |= SURVEY_INFO_IN_USE;
8023
8024 return 0;
8025
8026 }
8027 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8028
8029 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8030 MODULE_VERSION(DRV_VERSION);
8031 MODULE_DESCRIPTION("Ralink RT2800 library");
8032 MODULE_LICENSE("GPL");
Linux with added FPC-III support