drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2013 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 #define SLI2_IOCB_CMD_SIZE      32
  63 #define SLI2_IOCB_RSP_SIZE      32
  64 #define SLI3_IOCB_CMD_SIZE      128
  65 #define SLI3_IOCB_RSP_SIZE      64
  66
  67 #define LPFC_UNREG_ALL_RPIS_VPORT       0xffff
  68 #define LPFC_UNREG_ALL_DFLT_RPIS        0xffffffff
  69
  70 /* vendor ID used in SCSI netlink calls */
  71 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
  72
  73 #define FW_REV_STR_SIZE 32
  74 /* Common Transport structures and definitions */
  75
  76 union CtRevisionId {
  77         /* Structure is in Big Endian format */
  78         struct {
  79                 uint32_t Revision:8;
  80                 uint32_t InId:24;
  81         } bits;
  82         uint32_t word;
  83 };
  84
  85 union CtCommandResponse {
  86         /* Structure is in Big Endian format */
  87         struct {
  88                 uint32_t CmdRsp:16;
  89                 uint32_t Size:16;
  90         } bits;
  91         uint32_t word;
  92 };
  93
  94 #define FC4_FEATURE_INIT 0x2
  95 #define FC4_FEATURE_TARGET 0x1
  96
  97 struct lpfc_sli_ct_request {
  98         /* Structure is in Big Endian format */
  99         union CtRevisionId RevisionId;
 100         uint8_t FsType;
 101         uint8_t FsSubType;
 102         uint8_t Options;
 103         uint8_t Rsrvd1;
 104         union CtCommandResponse CommandResponse;
 105         uint8_t Rsrvd2;
 106         uint8_t ReasonCode;
 107         uint8_t Explanation;
 108         uint8_t VendorUnique;
 109
 110         union {
 111                 uint32_t PortID;
 112                 struct gid {
 113                         uint8_t PortType;       /* for GID_PT requests */
 114                         uint8_t DomainScope;
 115                         uint8_t AreaScope;
 116                         uint8_t Fc4Type;        /* for GID_FT requests */
 117                 } gid;
 118                 struct rft {
 119                         uint32_t PortId;        /* For RFT_ID requests */
 120
 121 #ifdef __BIG_ENDIAN_BITFIELD
 122                         uint32_t rsvd0:16;
 123                         uint32_t rsvd1:7;
 124                         uint32_t fcpReg:1;      /* Type 8 */
 125                         uint32_t rsvd2:2;
 126                         uint32_t ipReg:1;       /* Type 5 */
 127                         uint32_t rsvd3:5;
 128 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 129                         uint32_t rsvd0:16;
 130                         uint32_t fcpReg:1;      /* Type 8 */
 131                         uint32_t rsvd1:7;
 132                         uint32_t rsvd3:5;
 133                         uint32_t ipReg:1;       /* Type 5 */
 134                         uint32_t rsvd2:2;
 135 #endif
 136
 137                         uint32_t rsvd[7];
 138                 } rft;
 139                 struct rnn {
 140                         uint32_t PortId;        /* For RNN_ID requests */
 141                         uint8_t wwnn[8];
 142                 } rnn;
 143                 struct rsnn {   /* For RSNN_ID requests */
 144                         uint8_t wwnn[8];
 145                         uint8_t len;
 146                         uint8_t symbname[255];
 147                 } rsnn;
 148                 struct da_id { /* For DA_ID requests */
 149                         uint32_t port_id;
 150                 } da_id;
 151                 struct rspn {   /* For RSPN_ID requests */
 152                         uint32_t PortId;
 153                         uint8_t len;
 154                         uint8_t symbname[255];
 155                 } rspn;
 156                 struct gff {
 157                         uint32_t PortId;
 158                 } gff;
 159                 struct gff_acc {
 160                         uint8_t fbits[128];
 161                 } gff_acc;
 162 #define FCP_TYPE_FEATURE_OFFSET 7
 163                 struct rff {
 164                         uint32_t PortId;
 165                         uint8_t reserved[2];
 166                         uint8_t fbits;
 167                         uint8_t type_code;     /* type=8 for FCP */
 168                 } rff;
 169         } un;
 170 };
 171
 172 #define  SLI_CT_REVISION        1
 173 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 174                            sizeof(struct gid))
 175 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 176                            sizeof(struct gff))
 177 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 178                            sizeof(struct rft))
 179 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 180                            sizeof(struct rff))
 181 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 182                            sizeof(struct rnn))
 183 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 184                            sizeof(struct rsnn))
 185 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 186                           sizeof(struct da_id))
 187 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 188                            sizeof(struct rspn))
 189
 190 /*
 191  * FsType Definitions
 192  */
 193
 194 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 195 #define  SLI_CT_TIME_SERVICE              0xFB
 196 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 197 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 198
 199 /*
 200  * Directory Service Subtypes
 201  */
 202
 203 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 204
 205 /*
 206  * Response Codes
 207  */
 208
 209 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 210 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 211
 212 /*
 213  * Reason Codes
 214  */
 215
 216 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 217 #define  SLI_CT_INVALID_COMMAND           0x01
 218 #define  SLI_CT_INVALID_VERSION           0x02
 219 #define  SLI_CT_LOGICAL_ERROR             0x03
 220 #define  SLI_CT_INVALID_IU_SIZE           0x04
 221 #define  SLI_CT_LOGICAL_BUSY              0x05
 222 #define  SLI_CT_PROTOCOL_ERROR            0x07
 223 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 224 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 225 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 226 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 227 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 228 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 229 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 230 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 231 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 232 #define  SLI_CT_VENDOR_UNIQUE             0xff
 233
 234 /*
 235  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 236  */
 237
 238 #define  SLI_CT_NO_PORT_ID                0x01
 239 #define  SLI_CT_NO_PORT_NAME              0x02
 240 #define  SLI_CT_NO_NODE_NAME              0x03
 241 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 242 #define  SLI_CT_NO_IP_ADDRESS             0x05
 243 #define  SLI_CT_NO_IPA                    0x06
 244 #define  SLI_CT_NO_FC4_TYPES              0x07
 245 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 246 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 247 #define  SLI_CT_NO_PORT_TYPE              0x0A
 248 #define  SLI_CT_ACCESS_DENIED             0x10
 249 #define  SLI_CT_INVALID_PORT_ID           0x11
 250 #define  SLI_CT_DATABASE_EMPTY            0x12
 251
 252 /*
 253  * Name Server Command Codes
 254  */
 255
 256 #define  SLI_CTNS_GA_NXT      0x0100
 257 #define  SLI_CTNS_GPN_ID      0x0112
 258 #define  SLI_CTNS_GNN_ID      0x0113
 259 #define  SLI_CTNS_GCS_ID      0x0114
 260 #define  SLI_CTNS_GFT_ID      0x0117
 261 #define  SLI_CTNS_GSPN_ID     0x0118
 262 #define  SLI_CTNS_GPT_ID      0x011A
 263 #define  SLI_CTNS_GFF_ID      0x011F
 264 #define  SLI_CTNS_GID_PN      0x0121
 265 #define  SLI_CTNS_GID_NN      0x0131
 266 #define  SLI_CTNS_GIP_NN      0x0135
 267 #define  SLI_CTNS_GIPA_NN     0x0136
 268 #define  SLI_CTNS_GSNN_NN     0x0139
 269 #define  SLI_CTNS_GNN_IP      0x0153
 270 #define  SLI_CTNS_GIPA_IP     0x0156
 271 #define  SLI_CTNS_GID_FT      0x0171
 272 #define  SLI_CTNS_GID_PT      0x01A1
 273 #define  SLI_CTNS_RPN_ID      0x0212
 274 #define  SLI_CTNS_RNN_ID      0x0213
 275 #define  SLI_CTNS_RCS_ID      0x0214
 276 #define  SLI_CTNS_RFT_ID      0x0217
 277 #define  SLI_CTNS_RSPN_ID     0x0218
 278 #define  SLI_CTNS_RPT_ID      0x021A
 279 #define  SLI_CTNS_RFF_ID      0x021F
 280 #define  SLI_CTNS_RIP_NN      0x0235
 281 #define  SLI_CTNS_RIPA_NN     0x0236
 282 #define  SLI_CTNS_RSNN_NN     0x0239
 283 #define  SLI_CTNS_DA_ID       0x0300
 284
 285 /*
 286  * Port Types
 287  */
 288
 289 #define  SLI_CTPT_N_PORT      0x01
 290 #define  SLI_CTPT_NL_PORT     0x02
 291 #define  SLI_CTPT_FNL_PORT    0x03
 292 #define  SLI_CTPT_IP          0x04
 293 #define  SLI_CTPT_FCP         0x08
 294 #define  SLI_CTPT_NX_PORT     0x7F
 295 #define  SLI_CTPT_F_PORT      0x81
 296 #define  SLI_CTPT_FL_PORT     0x82
 297 #define  SLI_CTPT_E_PORT      0x84
 298
 299 #define SLI_CT_LAST_ENTRY     0x80000000
 300
 301 /* Fibre Channel Service Parameter definitions */
 302
 303 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 304 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 305 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 306 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 307
 308 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 309 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 310 #define FC_PH3   0x20           /* FC-PH-3 version */
 311
 312 #define FF_FRAME_SIZE     2048
 313
 314 struct lpfc_name {
 315         union {
 316                 struct {
 317 #ifdef __BIG_ENDIAN_BITFIELD
 318                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 319                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 320                                                    8:11 of IEEE ext */
 321 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 322                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 323                                                    8:11 of IEEE ext */
 324                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 325 #endif
 326
 327 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 328 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 329 #define NAME_FC_TYPE        0x3 /* FC native name type */
 330 #define NAME_IP_TYPE        0x4 /* IP address */
 331 #define NAME_CCITT_TYPE     0xC
 332 #define NAME_CCITT_GR_TYPE  0xE
 333                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 334                                                    extended Lsb */
 335                         uint8_t IEEE[6];        /* FC IEEE address */
 336                 } s;
 337                 uint8_t wwn[8];
 338         } u;
 339 };
 340
 341 struct csp {
 342         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 343         uint8_t fcphLow;
 344         uint8_t bbCreditMsb;
 345         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 346
 347 /*
 348  * Word 1 Bit 31 in common service parameter is overloaded.
 349  * Word 1 Bit 31 in FLOGI request is multiple NPort request
 350  * Word 1 Bit 31 in FLOGI response is clean address bit
 351  */
 352 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
 353 /*
 354  * Word 1 Bit 30 in common service parameter is overloaded.
 355  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
 356  * Word 1 Bit 30 in PLOGI request is random offset
 357  */
 358 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
 359 #ifdef __BIG_ENDIAN_BITFIELD
 360         uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 361         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 362         uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 363         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 364         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 365         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 366         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 367         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 368
 369         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 370         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 371         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 372         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 373         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 374         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 375 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 376         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 377         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 378         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 379         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 380         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 381         uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 382         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 383         uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 384
 385         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 386         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 387         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 388         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 389         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 390         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 391 #endif
 392
 393         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 394         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 395         union {
 396                 struct {
 397                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 398
 399                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 400                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 401
 402                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 403                 } nPort;
 404                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 405         } w2;
 406
 407         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 408 };
 409
 410 struct class_parms {
 411 #ifdef __BIG_ENDIAN_BITFIELD
 412         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 413         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 414         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 415         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 416         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 417         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 418 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 419         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 420         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 421         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 422         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 423         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 424         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 425
 426 #endif
 427
 428         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 429
 430 #ifdef __BIG_ENDIAN_BITFIELD
 431         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 432         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 433         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 434         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 435         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 436 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 437         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 438         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 439         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 440         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 441         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 442 #endif
 443
 444         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 445
 446 #ifdef __BIG_ENDIAN_BITFIELD
 447         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 448         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 449         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 450         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 451         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 452         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 453 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 454         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 455         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 456         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 457         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 458         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 459         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 460 #endif
 461
 462         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 463         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 464         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 465
 466         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 467         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 468         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 469         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 470
 471         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 472         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 473         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 474         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 475 };
 476
 477 struct serv_parm {      /* Structure is in Big Endian format */
 478         struct csp cmn;
 479         struct lpfc_name portName;
 480         struct lpfc_name nodeName;
 481         struct class_parms cls1;
 482         struct class_parms cls2;
 483         struct class_parms cls3;
 484         struct class_parms cls4;
 485         uint8_t vendorVersion[16];
 486 };
 487
 488 /*
 489  * Virtual Fabric Tagging Header
 490  */
 491 struct fc_vft_header {
 492          uint32_t word0;
 493 #define fc_vft_hdr_r_ctl_SHIFT          24
 494 #define fc_vft_hdr_r_ctl_MASK           0xFF
 495 #define fc_vft_hdr_r_ctl_WORD           word0
 496 #define fc_vft_hdr_ver_SHIFT            22
 497 #define fc_vft_hdr_ver_MASK             0x3
 498 #define fc_vft_hdr_ver_WORD             word0
 499 #define fc_vft_hdr_type_SHIFT           18
 500 #define fc_vft_hdr_type_MASK            0xF
 501 #define fc_vft_hdr_type_WORD            word0
 502 #define fc_vft_hdr_e_SHIFT              16
 503 #define fc_vft_hdr_e_MASK               0x1
 504 #define fc_vft_hdr_e_WORD               word0
 505 #define fc_vft_hdr_priority_SHIFT       13
 506 #define fc_vft_hdr_priority_MASK        0x7
 507 #define fc_vft_hdr_priority_WORD        word0
 508 #define fc_vft_hdr_vf_id_SHIFT          1
 509 #define fc_vft_hdr_vf_id_MASK           0xFFF
 510 #define fc_vft_hdr_vf_id_WORD           word0
 511         uint32_t word1;
 512 #define fc_vft_hdr_hopct_SHIFT          24
 513 #define fc_vft_hdr_hopct_MASK           0xFF
 514 #define fc_vft_hdr_hopct_WORD           word1
 515 };
 516
 517 /*
 518  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 519  */
 520 #ifdef __BIG_ENDIAN_BITFIELD
 521 #define ELS_CMD_MASK      0xffff0000
 522 #define ELS_RSP_MASK      0xff000000
 523 #define ELS_CMD_LS_RJT    0x01000000
 524 #define ELS_CMD_ACC       0x02000000
 525 #define ELS_CMD_PLOGI     0x03000000
 526 #define ELS_CMD_FLOGI     0x04000000
 527 #define ELS_CMD_LOGO      0x05000000
 528 #define ELS_CMD_ABTX      0x06000000
 529 #define ELS_CMD_RCS       0x07000000
 530 #define ELS_CMD_RES       0x08000000
 531 #define ELS_CMD_RSS       0x09000000
 532 #define ELS_CMD_RSI       0x0A000000
 533 #define ELS_CMD_ESTS      0x0B000000
 534 #define ELS_CMD_ESTC      0x0C000000
 535 #define ELS_CMD_ADVC      0x0D000000
 536 #define ELS_CMD_RTV       0x0E000000
 537 #define ELS_CMD_RLS       0x0F000000
 538 #define ELS_CMD_ECHO      0x10000000
 539 #define ELS_CMD_TEST      0x11000000
 540 #define ELS_CMD_RRQ       0x12000000
 541 #define ELS_CMD_REC       0x13000000
 542 #define ELS_CMD_PRLI      0x20100014
 543 #define ELS_CMD_PRLO      0x21100014
 544 #define ELS_CMD_PRLO_ACC  0x02100014
 545 #define ELS_CMD_PDISC     0x50000000
 546 #define ELS_CMD_FDISC     0x51000000
 547 #define ELS_CMD_ADISC     0x52000000
 548 #define ELS_CMD_FARP      0x54000000
 549 #define ELS_CMD_FARPR     0x55000000
 550 #define ELS_CMD_RPS       0x56000000
 551 #define ELS_CMD_RPL       0x57000000
 552 #define ELS_CMD_FAN       0x60000000
 553 #define ELS_CMD_RSCN      0x61040000
 554 #define ELS_CMD_SCR       0x62000000
 555 #define ELS_CMD_RNID      0x78000000
 556 #define ELS_CMD_LIRR      0x7A000000
 557 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 558 #define ELS_CMD_MASK      0xffff
 559 #define ELS_RSP_MASK      0xff
 560 #define ELS_CMD_LS_RJT    0x01
 561 #define ELS_CMD_ACC       0x02
 562 #define ELS_CMD_PLOGI     0x03
 563 #define ELS_CMD_FLOGI     0x04
 564 #define ELS_CMD_LOGO      0x05
 565 #define ELS_CMD_ABTX      0x06
 566 #define ELS_CMD_RCS       0x07
 567 #define ELS_CMD_RES       0x08
 568 #define ELS_CMD_RSS       0x09
 569 #define ELS_CMD_RSI       0x0A
 570 #define ELS_CMD_ESTS      0x0B
 571 #define ELS_CMD_ESTC      0x0C
 572 #define ELS_CMD_ADVC      0x0D
 573 #define ELS_CMD_RTV       0x0E
 574 #define ELS_CMD_RLS       0x0F
 575 #define ELS_CMD_ECHO      0x10
 576 #define ELS_CMD_TEST      0x11
 577 #define ELS_CMD_RRQ       0x12
 578 #define ELS_CMD_REC       0x13
 579 #define ELS_CMD_PRLI      0x14001020
 580 #define ELS_CMD_PRLO      0x14001021
 581 #define ELS_CMD_PRLO_ACC  0x14001002
 582 #define ELS_CMD_PDISC     0x50
 583 #define ELS_CMD_FDISC     0x51
 584 #define ELS_CMD_ADISC     0x52
 585 #define ELS_CMD_FARP      0x54
 586 #define ELS_CMD_FARPR     0x55
 587 #define ELS_CMD_RPS       0x56
 588 #define ELS_CMD_RPL       0x57
 589 #define ELS_CMD_FAN       0x60
 590 #define ELS_CMD_RSCN      0x0461
 591 #define ELS_CMD_SCR       0x62
 592 #define ELS_CMD_RNID      0x78
 593 #define ELS_CMD_LIRR      0x7A
 594 #endif
 595
 596 /*
 597  *  LS_RJT Payload Definition
 598  */
 599
 600 struct ls_rjt { /* Structure is in Big Endian format */
 601         union {
 602                 uint32_t lsRjtError;
 603                 struct {
 604                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 605
 606                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 607                         /* LS_RJT reason codes */
 608 #define LSRJT_INVALID_CMD     0x01
 609 #define LSRJT_LOGICAL_ERR     0x03
 610 #define LSRJT_LOGICAL_BSY     0x05
 611 #define LSRJT_PROTOCOL_ERR    0x07
 612 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 613 #define LSRJT_CMD_UNSUPPORTED 0x0B
 614 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 615
 616                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 617                         /* LS_RJT reason explanation */
 618 #define LSEXP_NOTHING_MORE      0x00
 619 #define LSEXP_SPARM_OPTIONS     0x01
 620 #define LSEXP_SPARM_ICTL        0x03
 621 #define LSEXP_SPARM_RCTL        0x05
 622 #define LSEXP_SPARM_RCV_SIZE    0x07
 623 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 624 #define LSEXP_SPARM_CREDIT      0x0B
 625 #define LSEXP_INVALID_PNAME     0x0D
 626 #define LSEXP_INVALID_NNAME     0x0E
 627 #define LSEXP_INVALID_CSP       0x0F
 628 #define LSEXP_INVALID_ASSOC_HDR 0x11
 629 #define LSEXP_ASSOC_HDR_REQ     0x13
 630 #define LSEXP_INVALID_O_SID     0x15
 631 #define LSEXP_INVALID_OX_RX     0x17
 632 #define LSEXP_CMD_IN_PROGRESS   0x19
 633 #define LSEXP_PORT_LOGIN_REQ    0x1E
 634 #define LSEXP_INVALID_NPORT_ID  0x1F
 635 #define LSEXP_INVALID_SEQ_ID    0x21
 636 #define LSEXP_INVALID_XCHG      0x23
 637 #define LSEXP_INACTIVE_XCHG     0x25
 638 #define LSEXP_RQ_REQUIRED       0x27
 639 #define LSEXP_OUT_OF_RESOURCE   0x29
 640 #define LSEXP_CANT_GIVE_DATA    0x2A
 641 #define LSEXP_REQ_UNSUPPORTED   0x2C
 642                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 643                 } b;
 644         } un;
 645 };
 646
 647 /*
 648  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 649  */
 650
 651 typedef struct _LOGO {          /* Structure is in Big Endian format */
 652         union {
 653                 uint32_t nPortId32;     /* Access nPortId as a word */
 654                 struct {
 655                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 656                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 657                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 658                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 659                 } b;
 660         } un;
 661         struct lpfc_name portName;      /* N_port name field */
 662 } LOGO;
 663
 664 /*
 665  *  FCP Login (PRLI Request / ACC) Payload Definition
 666  */
 667
 668 #define PRLX_PAGE_LEN   0x10
 669 #define TPRLO_PAGE_LEN  0x14
 670
 671 typedef struct _PRLI {          /* Structure is in Big Endian format */
 672         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 673
 674 #define PRLI_FCP_TYPE 0x08
 675         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 676
 677 #ifdef __BIG_ENDIAN_BITFIELD
 678         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 679         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 680         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 681
 682         /*    ACC = imagePairEstablished */
 683         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 684         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 685 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 686         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 687         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 688         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 689         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 690         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 691         /*    ACC = imagePairEstablished */
 692 #endif
 693
 694 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 695 #define PRLI_NO_RESOURCES     0x2
 696 #define PRLI_INIT_INCOMPLETE  0x3
 697 #define PRLI_NO_SUCH_PA       0x4
 698 #define PRLI_PREDEF_CONFIG    0x5
 699 #define PRLI_PARTIAL_SUCCESS  0x6
 700 #define PRLI_INVALID_PAGE_CNT 0x7
 701         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 702
 703         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 704
 705         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 706
 707         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 708         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 709
 710 #ifdef __BIG_ENDIAN_BITFIELD
 711         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 712         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 713         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 714         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 715         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 716         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 717         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 718         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 719         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 720         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 721         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 722         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 723         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 724         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 725         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 726         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 727 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 728         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 729         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 730         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 731         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 732         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 733         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 734         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 735         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 736         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 737         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 738         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 739         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 740         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 741         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 742         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 743         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 744 #endif
 745 } PRLI;
 746
 747 /*
 748  *  FCP Logout (PRLO Request / ACC) Payload Definition
 749  */
 750
 751 typedef struct _PRLO {          /* Structure is in Big Endian format */
 752         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 753
 754 #define PRLO_FCP_TYPE  0x08
 755         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 756
 757 #ifdef __BIG_ENDIAN_BITFIELD
 758         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 759         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 760         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 761         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 762 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 763         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 764         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 765         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 766         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 767 #endif
 768
 769 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 770 #define PRLO_NO_SUCH_IMAGE    0x4
 771 #define PRLO_INVALID_PAGE_CNT 0x7
 772
 773         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 774
 775         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 776
 777         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 778
 779         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 780 } PRLO;
 781
 782 typedef struct _ADISC {         /* Structure is in Big Endian format */
 783         uint32_t hardAL_PA;
 784         struct lpfc_name portName;
 785         struct lpfc_name nodeName;
 786         uint32_t DID;
 787 } ADISC;
 788
 789 typedef struct _FARP {          /* Structure is in Big Endian format */
 790         uint32_t Mflags:8;
 791         uint32_t Odid:24;
 792 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 793                                            action */
 794 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 795 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 796 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 797 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 798                                            supported */
 799 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 800                                            supported */
 801         uint32_t Rflags:8;
 802         uint32_t Rdid:24;
 803 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 804 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 805         struct lpfc_name OportName;
 806         struct lpfc_name OnodeName;
 807         struct lpfc_name RportName;
 808         struct lpfc_name RnodeName;
 809         uint8_t Oipaddr[16];
 810         uint8_t Ripaddr[16];
 811 } FARP;
 812
 813 typedef struct _FAN {           /* Structure is in Big Endian format */
 814         uint32_t Fdid;
 815         struct lpfc_name FportName;
 816         struct lpfc_name FnodeName;
 817 } FAN;
 818
 819 typedef struct _SCR {           /* Structure is in Big Endian format */
 820         uint8_t resvd1;
 821         uint8_t resvd2;
 822         uint8_t resvd3;
 823         uint8_t Function;
 824 #define  SCR_FUNC_FABRIC     0x01
 825 #define  SCR_FUNC_NPORT      0x02
 826 #define  SCR_FUNC_FULL       0x03
 827 #define  SCR_CLEAR           0xff
 828 } SCR;
 829
 830 typedef struct _RNID_TOP_DISC {
 831         struct lpfc_name portName;
 832         uint8_t resvd[8];
 833         uint32_t unitType;
 834 #define RNID_HBA            0x7
 835 #define RNID_HOST           0xa
 836 #define RNID_DRIVER         0xd
 837         uint32_t physPort;
 838         uint32_t attachedNodes;
 839         uint16_t ipVersion;
 840 #define RNID_IPV4           0x1
 841 #define RNID_IPV6           0x2
 842         uint16_t UDPport;
 843         uint8_t ipAddr[16];
 844         uint16_t resvd1;
 845         uint16_t flags;
 846 #define RNID_TD_SUPPORT     0x1
 847 #define RNID_LP_VALID       0x2
 848 } RNID_TOP_DISC;
 849
 850 typedef struct _RNID {          /* Structure is in Big Endian format */
 851         uint8_t Format;
 852 #define RNID_TOPOLOGY_DISC  0xdf
 853         uint8_t CommonLen;
 854         uint8_t resvd1;
 855         uint8_t SpecificLen;
 856         struct lpfc_name portName;
 857         struct lpfc_name nodeName;
 858         union {
 859                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 860         } un;
 861 } RNID;
 862
 863 typedef struct  _RPS {          /* Structure is in Big Endian format */
 864         union {
 865                 uint32_t portNum;
 866                 struct lpfc_name portName;
 867         } un;
 868 } RPS;
 869
 870 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 871         uint16_t rsvd1;
 872         uint16_t portStatus;
 873         uint32_t linkFailureCnt;
 874         uint32_t lossSyncCnt;
 875         uint32_t lossSignalCnt;
 876         uint32_t primSeqErrCnt;
 877         uint32_t invalidXmitWord;
 878         uint32_t crcCnt;
 879 } RPS_RSP;
 880
 881 struct RLS {                    /* Structure is in Big Endian format */
 882         uint32_t rls;
 883 #define rls_rsvd_SHIFT          24
 884 #define rls_rsvd_MASK           0x000000ff
 885 #define rls_rsvd_WORD           rls
 886 #define rls_did_SHIFT           0
 887 #define rls_did_MASK            0x00ffffff
 888 #define rls_did_WORD            rls
 889 };
 890
 891 struct  RLS_RSP {               /* Structure is in Big Endian format */
 892         uint32_t linkFailureCnt;
 893         uint32_t lossSyncCnt;
 894         uint32_t lossSignalCnt;
 895         uint32_t primSeqErrCnt;
 896         uint32_t invalidXmitWord;
 897         uint32_t crcCnt;
 898 };
 899
 900 struct RRQ {                    /* Structure is in Big Endian format */
 901         uint32_t rrq;
 902 #define rrq_rsvd_SHIFT          24
 903 #define rrq_rsvd_MASK           0x000000ff
 904 #define rrq_rsvd_WORD           rrq
 905 #define rrq_did_SHIFT           0
 906 #define rrq_did_MASK            0x00ffffff
 907 #define rrq_did_WORD            rrq
 908         uint32_t rrq_exchg;
 909 #define rrq_oxid_SHIFT          16
 910 #define rrq_oxid_MASK           0xffff
 911 #define rrq_oxid_WORD           rrq_exchg
 912 #define rrq_rxid_SHIFT          0
 913 #define rrq_rxid_MASK           0xffff
 914 #define rrq_rxid_WORD           rrq_exchg
 915 };
 916
 917 #define LPFC_MAX_VFN_PER_PFN    255 /* Maximum VFs allowed per ARI */
 918 #define LPFC_DEF_VFN_PER_PFN    0   /* Default VFs due to platform limitation*/
 919
 920 struct RTV_RSP {                /* Structure is in Big Endian format */
 921         uint32_t ratov;
 922         uint32_t edtov;
 923         uint32_t qtov;
 924 #define qtov_rsvd0_SHIFT        28
 925 #define qtov_rsvd0_MASK         0x0000000f
 926 #define qtov_rsvd0_WORD         qtov            /* reserved */
 927 #define qtov_edtovres_SHIFT     27
 928 #define qtov_edtovres_MASK      0x00000001
 929 #define qtov_edtovres_WORD      qtov            /* E_D_TOV Resolution */
 930 #define qtov__rsvd1_SHIFT       19
 931 #define qtov_rsvd1_MASK         0x0000003f
 932 #define qtov_rsvd1_WORD         qtov            /* reserved */
 933 #define qtov_rttov_SHIFT        18
 934 #define qtov_rttov_MASK         0x00000001
 935 #define qtov_rttov_WORD         qtov            /* R_T_TOV value */
 936 #define qtov_rsvd2_SHIFT        0
 937 #define qtov_rsvd2_MASK         0x0003ffff
 938 #define qtov_rsvd2_WORD         qtov            /* reserved */
 939 };
 940
 941
 942 typedef struct  _RPL {          /* Structure is in Big Endian format */
 943         uint32_t maxsize;
 944         uint32_t index;
 945 } RPL;
 946
 947 typedef struct  _PORT_NUM_BLK {
 948         uint32_t portNum;
 949         uint32_t portID;
 950         struct lpfc_name portName;
 951 } PORT_NUM_BLK;
 952
 953 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 954         uint32_t listLen;
 955         uint32_t index;
 956         PORT_NUM_BLK port_num_blk;
 957 } RPL_RSP;
 958
 959 /* This is used for RSCN command */
 960 typedef struct _D_ID {          /* Structure is in Big Endian format */
 961         union {
 962                 uint32_t word;
 963                 struct {
 964 #ifdef __BIG_ENDIAN_BITFIELD
 965                         uint8_t resv;
 966                         uint8_t domain;
 967                         uint8_t area;
 968                         uint8_t id;
 969 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 970                         uint8_t id;
 971                         uint8_t area;
 972                         uint8_t domain;
 973                         uint8_t resv;
 974 #endif
 975                 } b;
 976         } un;
 977 } D_ID;
 978
 979 #define RSCN_ADDRESS_FORMAT_PORT        0x0
 980 #define RSCN_ADDRESS_FORMAT_AREA        0x1
 981 #define RSCN_ADDRESS_FORMAT_DOMAIN      0x2
 982 #define RSCN_ADDRESS_FORMAT_FABRIC      0x3
 983 #define RSCN_ADDRESS_FORMAT_MASK        0x3
 984
 985 /*
 986  *  Structure to define all ELS Payload types
 987  */
 988
 989 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 990         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 991         uint8_t elsByte1;
 992         uint8_t elsByte2;
 993         uint8_t elsByte3;
 994         union {
 995                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 996                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 997                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 998                 PRLI prli;      /* Payload for PRLI/ACC */
 999                 PRLO prlo;      /* Payload for PRLO/ACC */
1000                 ADISC adisc;    /* Payload for ADISC/ACC */
1001                 FARP farp;      /* Payload for FARP/ACC */
1002                 FAN fan;        /* Payload for FAN */
1003                 SCR scr;        /* Payload for SCR/ACC */
1004                 RNID rnid;      /* Payload for RNID */
1005                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
1006         } un;
1007 } ELS_PKT;
1008
1009 /*
1010  * FDMI
1011  * HBA MAnagement Operations Command Codes
1012  */
1013 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
1014 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
1015 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
1016 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
1017 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
1018 #define  SLI_MGMT_RHAT     0x201        /* Register HBA attributes */
1019 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
1020 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
1021 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
1022 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
1023
1024 /*
1025  * Management Service Subtypes
1026  */
1027 #define  SLI_CT_FDMI_Subtypes     0x10
1028
1029 /*
1030  * HBA Management Service Reject Code
1031  */
1032 #define  REJECT_CODE             0x9    /* Unable to perform command request */
1033
1034 /*
1035  * HBA Management Service Reject Reason Code
1036  * Please refer to the Reason Codes above
1037  */
1038
1039 /*
1040  * HBA Attribute Types
1041  */
1042 #define  NODE_NAME               0x1
1043 #define  MANUFACTURER            0x2
1044 #define  SERIAL_NUMBER           0x3
1045 #define  MODEL                   0x4
1046 #define  MODEL_DESCRIPTION       0x5
1047 #define  HARDWARE_VERSION        0x6
1048 #define  DRIVER_VERSION          0x7
1049 #define  OPTION_ROM_VERSION      0x8
1050 #define  FIRMWARE_VERSION        0x9
1051 #define  OS_NAME_VERSION         0xa
1052 #define  MAX_CT_PAYLOAD_LEN      0xb
1053
1054 /*
1055  * Port Attrubute Types
1056  */
1057 #define  SUPPORTED_FC4_TYPES     0x1
1058 #define  SUPPORTED_SPEED         0x2
1059 #define  PORT_SPEED              0x3
1060 #define  MAX_FRAME_SIZE          0x4
1061 #define  OS_DEVICE_NAME          0x5
1062 #define  HOST_NAME               0x6
1063
1064 union AttributesDef {
1065         /* Structure is in Big Endian format */
1066         struct {
1067                 uint32_t AttrType:16;
1068                 uint32_t AttrLen:16;
1069         } bits;
1070         uint32_t word;
1071 };
1072
1073
1074 /*
1075  * HBA Attribute Entry (8 - 260 bytes)
1076  */
1077 typedef struct {
1078         union AttributesDef ad;
1079         union {
1080                 uint32_t VendorSpecific;
1081                 uint8_t Manufacturer[64];
1082                 uint8_t SerialNumber[64];
1083                 uint8_t Model[256];
1084                 uint8_t ModelDescription[256];
1085                 uint8_t HardwareVersion[256];
1086                 uint8_t DriverVersion[256];
1087                 uint8_t OptionROMVersion[256];
1088                 uint8_t FirmwareVersion[256];
1089                 struct lpfc_name NodeName;
1090                 uint8_t SupportFC4Types[32];
1091                 uint32_t SupportSpeed;
1092                 uint32_t PortSpeed;
1093                 uint32_t MaxFrameSize;
1094                 uint8_t OsDeviceName[256];
1095                 uint8_t OsNameVersion[256];
1096                 uint32_t MaxCTPayloadLen;
1097                 uint8_t HostName[256];
1098         } un;
1099 } ATTRIBUTE_ENTRY;
1100
1101 /*
1102  * HBA Attribute Block
1103  */
1104 typedef struct {
1105         uint32_t EntryCnt;      /* Number of HBA attribute entries */
1106         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
1107 } ATTRIBUTE_BLOCK;
1108
1109 /*
1110  * Port Entry
1111  */
1112 typedef struct {
1113         struct lpfc_name PortName;
1114 } PORT_ENTRY;
1115
1116 /*
1117  * HBA Identifier
1118  */
1119 typedef struct {
1120         struct lpfc_name PortName;
1121 } HBA_IDENTIFIER;
1122
1123 /*
1124  * Registered Port List Format
1125  */
1126 typedef struct {
1127         uint32_t EntryCnt;
1128         PORT_ENTRY pe;          /* Variable-length array */
1129 } REG_PORT_LIST;
1130
1131 /*
1132  * Register HBA(RHBA)
1133  */
1134 typedef struct {
1135         HBA_IDENTIFIER hi;
1136         REG_PORT_LIST rpl;      /* variable-length array */
1137 /* ATTRIBUTE_BLOCK   ab; */
1138 } REG_HBA;
1139
1140 /*
1141  * Register HBA Attributes (RHAT)
1142  */
1143 typedef struct {
1144         struct lpfc_name HBA_PortName;
1145         ATTRIBUTE_BLOCK ab;
1146 } REG_HBA_ATTRIBUTE;
1147
1148 /*
1149  * Register Port Attributes (RPA)
1150  */
1151 typedef struct {
1152         struct lpfc_name PortName;
1153         ATTRIBUTE_BLOCK ab;
1154 } REG_PORT_ATTRIBUTE;
1155
1156 /*
1157  * Get Registered HBA List (GRHL) Accept Payload Format
1158  */
1159 typedef struct {
1160         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1161         struct lpfc_name HBA_PortName;  /* Variable-length array */
1162 } GRHL_ACC_PAYLOAD;
1163
1164 /*
1165  * Get Registered Port List (GRPL) Accept Payload Format
1166  */
1167 typedef struct {
1168         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1169         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1170 } GRPL_ACC_PAYLOAD;
1171
1172 /*
1173  * Get Port Attributes (GPAT) Accept Payload Format
1174  */
1175
1176 typedef struct {
1177         ATTRIBUTE_BLOCK pab;
1178 } GPAT_ACC_PAYLOAD;
1179
1180
1181 /*
1182  *  Begin HBA configuration parameters.
1183  *  The PCI configuration register BAR assignments are:
1184  *  BAR0, offset 0x10 - SLIM base memory address
1185  *  BAR1, offset 0x14 - SLIM base memory high address
1186  *  BAR2, offset 0x18 - REGISTER base memory address
1187  *  BAR3, offset 0x1c - REGISTER base memory high address
1188  *  BAR4, offset 0x20 - BIU I/O registers
1189  *  BAR5, offset 0x24 - REGISTER base io high address
1190  */
1191
1192 /* Number of rings currently used and available. */
1193 #define MAX_SLI3_CONFIGURED_RINGS     3
1194 #define MAX_SLI3_RINGS                4
1195
1196 /* IOCB / Mailbox is owned by FireFly */
1197 #define OWN_CHIP        1
1198
1199 /* IOCB / Mailbox is owned by Host */
1200 #define OWN_HOST        0
1201
1202 /* Number of 4-byte words in an IOCB. */
1203 #define IOCB_WORD_SZ    8
1204
1205 /* network headers for Dfctl field */
1206 #define FC_NET_HDR      0x20
1207
1208 /* Start FireFly Register definitions */
1209 #define PCI_VENDOR_ID_EMULEX        0x10df
1210 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1211 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1212 #define PCI_DEVICE_ID_BALIUS        0xe131
1213 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1214 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1215 #define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1216 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1217 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1218 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1219 #define PCI_DEVICE_ID_SAT_MID       0xf015
1220 #define PCI_DEVICE_ID_RFLY          0xf095
1221 #define PCI_DEVICE_ID_PFLY          0xf098
1222 #define PCI_DEVICE_ID_LP101         0xf0a1
1223 #define PCI_DEVICE_ID_TFLY          0xf0a5
1224 #define PCI_DEVICE_ID_BSMB          0xf0d1
1225 #define PCI_DEVICE_ID_BMID          0xf0d5
1226 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1227 #define PCI_DEVICE_ID_ZMID          0xf0e5
1228 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1229 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1230 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1231 #define PCI_DEVICE_ID_SAT           0xf100
1232 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1233 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1234 #define PCI_DEVICE_ID_FALCON        0xf180
1235 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1236 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1237 #define PCI_DEVICE_ID_CENTAUR       0xf900
1238 #define PCI_DEVICE_ID_PEGASUS       0xf980
1239 #define PCI_DEVICE_ID_THOR          0xfa00
1240 #define PCI_DEVICE_ID_VIPER         0xfb00
1241 #define PCI_DEVICE_ID_LP10000S      0xfc00
1242 #define PCI_DEVICE_ID_LP11000S      0xfc10
1243 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1244 #define PCI_DEVICE_ID_SAT_S         0xfc40
1245 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1246 #define PCI_DEVICE_ID_HELIOS        0xfd00
1247 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1248 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1249 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1250 #define PCI_DEVICE_ID_HORNET        0xfe05
1251 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1252 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1253 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1254 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1255 #define PCI_DEVICE_ID_TOMCAT        0x0714
1256 #define PCI_DEVICE_ID_SKYHAWK       0x0724
1257 #define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1258
1259 #define JEDEC_ID_ADDRESS            0x0080001c
1260 #define FIREFLY_JEDEC_ID            0x1ACC
1261 #define SUPERFLY_JEDEC_ID           0x0020
1262 #define DRAGONFLY_JEDEC_ID          0x0021
1263 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1264 #define CENTAUR_2G_JEDEC_ID         0x0026
1265 #define CENTAUR_1G_JEDEC_ID         0x0028
1266 #define PEGASUS_ORION_JEDEC_ID      0x0036
1267 #define PEGASUS_JEDEC_ID            0x0038
1268 #define THOR_JEDEC_ID               0x0012
1269 #define HELIOS_JEDEC_ID             0x0364
1270 #define ZEPHYR_JEDEC_ID             0x0577
1271 #define VIPER_JEDEC_ID              0x4838
1272 #define SATURN_JEDEC_ID             0x1004
1273 #define HORNET_JDEC_ID              0x2057706D
1274
1275 #define JEDEC_ID_MASK               0x0FFFF000
1276 #define JEDEC_ID_SHIFT              12
1277 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1278
1279 typedef struct {                /* FireFly BIU registers */
1280         uint32_t hostAtt;       /* See definitions for Host Attention
1281                                    register */
1282         uint32_t chipAtt;       /* See definitions for Chip Attention
1283                                    register */
1284         uint32_t hostStatus;    /* See definitions for Host Status register */
1285         uint32_t hostControl;   /* See definitions for Host Control register */
1286         uint32_t buiConfig;     /* See definitions for BIU configuration
1287                                    register */
1288 } FF_REGS;
1289
1290 /* IO Register size in bytes */
1291 #define FF_REG_AREA_SIZE       256
1292
1293 /* Host Attention Register */
1294
1295 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1296
1297 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1298 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1299 #define HA_R0ATT       0x00000008       /* Bit  3 */
1300 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1301 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1302 #define HA_R1ATT       0x00000080       /* Bit  7 */
1303 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1304 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1305 #define HA_R2ATT       0x00000800       /* Bit 11 */
1306 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1307 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1308 #define HA_R3ATT       0x00008000       /* Bit 15 */
1309 #define HA_LATT        0x20000000       /* Bit 29 */
1310 #define HA_MBATT       0x40000000       /* Bit 30 */
1311 #define HA_ERATT       0x80000000       /* Bit 31 */
1312
1313 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1314 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1315 #define HA_RXATT       0x00000008       /* Bit  3 */
1316 #define HA_RXMASK      0x0000000f
1317
1318 #define HA_R0_CLR_MSK   (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1319 #define HA_R1_CLR_MSK   (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1320 #define HA_R2_CLR_MSK   (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1321 #define HA_R3_CLR_MSK   (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1322
1323 #define HA_R0_POS       3
1324 #define HA_R1_POS       7
1325 #define HA_R2_POS       11
1326 #define HA_R3_POS       15
1327 #define HA_LE_POS       29
1328 #define HA_MB_POS       30
1329 #define HA_ER_POS       31
1330 /* Chip Attention Register */
1331
1332 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1333
1334 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1335 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1336 #define CA_R0ATT       0x00000008       /* Bit  3 */
1337 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1338 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1339 #define CA_R1ATT       0x00000080       /* Bit  7 */
1340 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1341 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1342 #define CA_R2ATT       0x00000800       /* Bit 11 */
1343 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1344 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1345 #define CA_R3ATT       0x00008000       /* Bit 15 */
1346 #define CA_MBATT       0x40000000       /* Bit 30 */
1347
1348 /* Host Status Register */
1349
1350 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1351
1352 #define HS_MBRDY       0x00400000       /* Bit 22 */
1353 #define HS_FFRDY       0x00800000       /* Bit 23 */
1354 #define HS_FFER8       0x01000000       /* Bit 24 */
1355 #define HS_FFER7       0x02000000       /* Bit 25 */
1356 #define HS_FFER6       0x04000000       /* Bit 26 */
1357 #define HS_FFER5       0x08000000       /* Bit 27 */
1358 #define HS_FFER4       0x10000000       /* Bit 28 */
1359 #define HS_FFER3       0x20000000       /* Bit 29 */
1360 #define HS_FFER2       0x40000000       /* Bit 30 */
1361 #define HS_FFER1       0x80000000       /* Bit 31 */
1362 #define HS_CRIT_TEMP   0x00000100       /* Bit 8  */
1363 #define HS_FFERM       0xFF000100       /* Mask for error bits 31:24 and 8 */
1364 #define UNPLUG_ERR     0x00000001       /* Indicate pci hot unplug */
1365 /* Host Control Register */
1366
1367 #define HC_REG_OFFSET  12       /* Byte offset from register base address */
1368
1369 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1370 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1371 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1372 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1373 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1374 #define HC_INITHBI     0x02000000       /* Bit 25 */
1375 #define HC_INITMB      0x04000000       /* Bit 26 */
1376 #define HC_INITFF      0x08000000       /* Bit 27 */
1377 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1378 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1379
1380 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1381 #define MSIX_DFLT_ID    0
1382 #define MSIX_RNG0_ID    0
1383 #define MSIX_RNG1_ID    1
1384 #define MSIX_RNG2_ID    2
1385 #define MSIX_RNG3_ID    3
1386
1387 #define MSIX_LINK_ID    4
1388 #define MSIX_MBOX_ID    5
1389
1390 #define MSIX_SPARE0_ID  6
1391 #define MSIX_SPARE1_ID  7
1392
1393 /* Mailbox Commands */
1394 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1395 #define MBX_LOAD_SM         0x01
1396 #define MBX_READ_NV         0x02
1397 #define MBX_WRITE_NV        0x03
1398 #define MBX_RUN_BIU_DIAG    0x04
1399 #define MBX_INIT_LINK       0x05
1400 #define MBX_DOWN_LINK       0x06
1401 #define MBX_CONFIG_LINK     0x07
1402 #define MBX_CONFIG_RING     0x09
1403 #define MBX_RESET_RING      0x0A
1404 #define MBX_READ_CONFIG     0x0B
1405 #define MBX_READ_RCONFIG    0x0C
1406 #define MBX_READ_SPARM      0x0D
1407 #define MBX_READ_STATUS     0x0E
1408 #define MBX_READ_RPI        0x0F
1409 #define MBX_READ_XRI        0x10
1410 #define MBX_READ_REV        0x11
1411 #define MBX_READ_LNK_STAT   0x12
1412 #define MBX_REG_LOGIN       0x13
1413 #define MBX_UNREG_LOGIN     0x14
1414 #define MBX_CLEAR_LA        0x16
1415 #define MBX_DUMP_MEMORY     0x17
1416 #define MBX_DUMP_CONTEXT    0x18
1417 #define MBX_RUN_DIAGS       0x19
1418 #define MBX_RESTART         0x1A
1419 #define MBX_UPDATE_CFG      0x1B
1420 #define MBX_DOWN_LOAD       0x1C
1421 #define MBX_DEL_LD_ENTRY    0x1D
1422 #define MBX_RUN_PROGRAM     0x1E
1423 #define MBX_SET_MASK        0x20
1424 #define MBX_SET_VARIABLE    0x21
1425 #define MBX_UNREG_D_ID      0x23
1426 #define MBX_KILL_BOARD      0x24
1427 #define MBX_CONFIG_FARP     0x25
1428 #define MBX_BEACON          0x2A
1429 #define MBX_CONFIG_MSI      0x30
1430 #define MBX_HEARTBEAT       0x31
1431 #define MBX_WRITE_VPARMS    0x32
1432 #define MBX_ASYNCEVT_ENABLE 0x33
1433 #define MBX_READ_EVENT_LOG_STATUS 0x37
1434 #define MBX_READ_EVENT_LOG  0x38
1435 #define MBX_WRITE_EVENT_LOG 0x39
1436
1437 #define MBX_PORT_CAPABILITIES 0x3B
1438 #define MBX_PORT_IOV_CONTROL 0x3C
1439
1440 #define MBX_CONFIG_HBQ      0x7C
1441 #define MBX_LOAD_AREA       0x81
1442 #define MBX_RUN_BIU_DIAG64  0x84
1443 #define MBX_CONFIG_PORT     0x88
1444 #define MBX_READ_SPARM64    0x8D
1445 #define MBX_READ_RPI64      0x8F
1446 #define MBX_REG_LOGIN64     0x93
1447 #define MBX_READ_TOPOLOGY   0x95
1448 #define MBX_REG_VPI         0x96
1449 #define MBX_UNREG_VPI       0x97
1450
1451 #define MBX_WRITE_WWN       0x98
1452 #define MBX_SET_DEBUG       0x99
1453 #define MBX_LOAD_EXP_ROM    0x9C
1454 #define MBX_SLI4_CONFIG     0x9B
1455 #define MBX_SLI4_REQ_FTRS   0x9D
1456 #define MBX_MAX_CMDS        0x9E
1457 #define MBX_RESUME_RPI      0x9E
1458 #define MBX_SLI2_CMD_MASK   0x80
1459 #define MBX_REG_VFI         0x9F
1460 #define MBX_REG_FCFI        0xA0
1461 #define MBX_UNREG_VFI       0xA1
1462 #define MBX_UNREG_FCFI      0xA2
1463 #define MBX_INIT_VFI        0xA3
1464 #define MBX_INIT_VPI        0xA4
1465 #define MBX_ACCESS_VDATA    0xA5
1466
1467 #define MBX_AUTH_PORT       0xF8
1468 #define MBX_SECURITY_MGMT   0xF9
1469
1470 /* IOCB Commands */
1471
1472 #define CMD_RCV_SEQUENCE_CX     0x01
1473 #define CMD_XMIT_SEQUENCE_CR    0x02
1474 #define CMD_XMIT_SEQUENCE_CX    0x03
1475 #define CMD_XMIT_BCAST_CN       0x04
1476 #define CMD_XMIT_BCAST_CX       0x05
1477 #define CMD_QUE_RING_BUF_CN     0x06
1478 #define CMD_QUE_XRI_BUF_CX      0x07
1479 #define CMD_IOCB_CONTINUE_CN    0x08
1480 #define CMD_RET_XRI_BUF_CX      0x09
1481 #define CMD_ELS_REQUEST_CR      0x0A
1482 #define CMD_ELS_REQUEST_CX      0x0B
1483 #define CMD_RCV_ELS_REQ_CX      0x0D
1484 #define CMD_ABORT_XRI_CN        0x0E
1485 #define CMD_ABORT_XRI_CX        0x0F
1486 #define CMD_CLOSE_XRI_CN        0x10
1487 #define CMD_CLOSE_XRI_CX        0x11
1488 #define CMD_CREATE_XRI_CR       0x12
1489 #define CMD_CREATE_XRI_CX       0x13
1490 #define CMD_GET_RPI_CN          0x14
1491 #define CMD_XMIT_ELS_RSP_CX     0x15
1492 #define CMD_GET_RPI_CR          0x16
1493 #define CMD_XRI_ABORTED_CX      0x17
1494 #define CMD_FCP_IWRITE_CR       0x18
1495 #define CMD_FCP_IWRITE_CX       0x19
1496 #define CMD_FCP_IREAD_CR        0x1A
1497 #define CMD_FCP_IREAD_CX        0x1B
1498 #define CMD_FCP_ICMND_CR        0x1C
1499 #define CMD_FCP_ICMND_CX        0x1D
1500 #define CMD_FCP_TSEND_CX        0x1F
1501 #define CMD_FCP_TRECEIVE_CX     0x21
1502 #define CMD_FCP_TRSP_CX         0x23
1503 #define CMD_FCP_AUTO_TRSP_CX    0x29
1504
1505 #define CMD_ADAPTER_MSG         0x20
1506 #define CMD_ADAPTER_DUMP        0x22
1507
1508 /*  SLI_2 IOCB Command Set */
1509
1510 #define CMD_ASYNC_STATUS        0x7C
1511 #define CMD_RCV_SEQUENCE64_CX   0x81
1512 #define CMD_XMIT_SEQUENCE64_CR  0x82
1513 #define CMD_XMIT_SEQUENCE64_CX  0x83
1514 #define CMD_XMIT_BCAST64_CN     0x84
1515 #define CMD_XMIT_BCAST64_CX     0x85
1516 #define CMD_QUE_RING_BUF64_CN   0x86
1517 #define CMD_QUE_XRI_BUF64_CX    0x87
1518 #define CMD_IOCB_CONTINUE64_CN  0x88
1519 #define CMD_RET_XRI_BUF64_CX    0x89
1520 #define CMD_ELS_REQUEST64_CR    0x8A
1521 #define CMD_ELS_REQUEST64_CX    0x8B
1522 #define CMD_ABORT_MXRI64_CN     0x8C
1523 #define CMD_RCV_ELS_REQ64_CX    0x8D
1524 #define CMD_XMIT_ELS_RSP64_CX   0x95
1525 #define CMD_XMIT_BLS_RSP64_CX   0x97
1526 #define CMD_FCP_IWRITE64_CR     0x98
1527 #define CMD_FCP_IWRITE64_CX     0x99
1528 #define CMD_FCP_IREAD64_CR      0x9A
1529 #define CMD_FCP_IREAD64_CX      0x9B
1530 #define CMD_FCP_ICMND64_CR      0x9C
1531 #define CMD_FCP_ICMND64_CX      0x9D
1532 #define CMD_FCP_TSEND64_CX      0x9F
1533 #define CMD_FCP_TRECEIVE64_CX   0xA1
1534 #define CMD_FCP_TRSP64_CX       0xA3
1535
1536 #define CMD_QUE_XRI64_CX        0xB3
1537 #define CMD_IOCB_RCV_SEQ64_CX   0xB5
1538 #define CMD_IOCB_RCV_ELS64_CX   0xB7
1539 #define CMD_IOCB_RET_XRI64_CX   0xB9
1540 #define CMD_IOCB_RCV_CONT64_CX  0xBB
1541
1542 #define CMD_GEN_REQUEST64_CR    0xC2
1543 #define CMD_GEN_REQUEST64_CX    0xC3
1544
1545 /* Unhandled SLI-3 Commands */
1546 #define CMD_IOCB_XMIT_MSEQ64_CR         0xB0
1547 #define CMD_IOCB_XMIT_MSEQ64_CX         0xB1
1548 #define CMD_IOCB_RCV_SEQ_LIST64_CX      0xC1
1549 #define CMD_IOCB_RCV_ELS_LIST64_CX      0xCD
1550 #define CMD_IOCB_CLOSE_EXTENDED_CN      0xB6
1551 #define CMD_IOCB_ABORT_EXTENDED_CN      0xBA
1552 #define CMD_IOCB_RET_HBQE64_CN          0xCA
1553 #define CMD_IOCB_FCP_IBIDIR64_CR        0xAC
1554 #define CMD_IOCB_FCP_IBIDIR64_CX        0xAD
1555 #define CMD_IOCB_FCP_ITASKMGT64_CX      0xAF
1556 #define CMD_IOCB_LOGENTRY_CN            0x94
1557 #define CMD_IOCB_LOGENTRY_ASYNC_CN      0x96
1558
1559 /* Data Security SLI Commands */
1560 #define DSSCMD_IWRITE64_CR              0xF8
1561 #define DSSCMD_IWRITE64_CX              0xF9
1562 #define DSSCMD_IREAD64_CR               0xFA
1563 #define DSSCMD_IREAD64_CX               0xFB
1564
1565 #define CMD_MAX_IOCB_CMD        0xFB
1566 #define CMD_IOCB_MASK           0xff
1567
1568 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1569                                            iocb */
1570 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1571 /*
1572  *  Define Status
1573  */
1574 #define MBX_SUCCESS                 0
1575 #define MBXERR_NUM_RINGS            1
1576 #define MBXERR_NUM_IOCBS            2
1577 #define MBXERR_IOCBS_EXCEEDED       3
1578 #define MBXERR_BAD_RING_NUMBER      4
1579 #define MBXERR_MASK_ENTRIES_RANGE   5
1580 #define MBXERR_MASKS_EXCEEDED       6
1581 #define MBXERR_BAD_PROFILE          7
1582 #define MBXERR_BAD_DEF_CLASS        8
1583 #define MBXERR_BAD_MAX_RESPONDER    9
1584 #define MBXERR_BAD_MAX_ORIGINATOR   10
1585 #define MBXERR_RPI_REGISTERED       11
1586 #define MBXERR_RPI_FULL             12
1587 #define MBXERR_NO_RESOURCES         13
1588 #define MBXERR_BAD_RCV_LENGTH       14
1589 #define MBXERR_DMA_ERROR            15
1590 #define MBXERR_ERROR                16
1591 #define MBXERR_LINK_DOWN            0x33
1592 #define MBXERR_SEC_NO_PERMISSION    0xF02
1593 #define MBX_NOT_FINISHED            255
1594
1595 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1596 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1597
1598 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1599
1600 /*
1601  *    Begin Structure Definitions for Mailbox Commands
1602  */
1603
1604 typedef struct {
1605 #ifdef __BIG_ENDIAN_BITFIELD
1606         uint8_t tval;
1607         uint8_t tmask;
1608         uint8_t rval;
1609         uint8_t rmask;
1610 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1611         uint8_t rmask;
1612         uint8_t rval;
1613         uint8_t tmask;
1614         uint8_t tval;
1615 #endif
1616 } RR_REG;
1617
1618 struct ulp_bde {
1619         uint32_t bdeAddress;
1620 #ifdef __BIG_ENDIAN_BITFIELD
1621         uint32_t bdeReserved:4;
1622         uint32_t bdeAddrHigh:4;
1623         uint32_t bdeSize:24;
1624 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1625         uint32_t bdeSize:24;
1626         uint32_t bdeAddrHigh:4;
1627         uint32_t bdeReserved:4;
1628 #endif
1629 };
1630
1631 typedef struct ULP_BDL {        /* SLI-2 */
1632 #ifdef __BIG_ENDIAN_BITFIELD
1633         uint32_t bdeFlags:8;    /* BDL Flags */
1634         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1635 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1636         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1637         uint32_t bdeFlags:8;    /* BDL Flags */
1638 #endif
1639
1640         uint32_t addrLow;       /* Address 0:31 */
1641         uint32_t addrHigh;      /* Address 32:63 */
1642         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1643 } ULP_BDL;
1644
1645 /*
1646  * BlockGuard Definitions
1647  */
1648
1649 enum lpfc_protgrp_type {
1650         LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
1651         LPFC_PG_TYPE_NO_DIF,      /* no DIF data pointed to by prot grp       */
1652         LPFC_PG_TYPE_EMBD_DIF,    /* DIF is embedded (inline) with data       */
1653         LPFC_PG_TYPE_DIF_BUF      /* DIF has its own scatter/gather list      */
1654 };
1655
1656 /* PDE Descriptors */
1657 #define LPFC_PDE5_DESCRIPTOR            0x85
1658 #define LPFC_PDE6_DESCRIPTOR            0x86
1659 #define LPFC_PDE7_DESCRIPTOR            0x87
1660
1661 /* BlockGuard Opcodes */
1662 #define BG_OP_IN_NODIF_OUT_CRC          0x0
1663 #define BG_OP_IN_CRC_OUT_NODIF          0x1
1664 #define BG_OP_IN_NODIF_OUT_CSUM         0x2
1665 #define BG_OP_IN_CSUM_OUT_NODIF         0x3
1666 #define BG_OP_IN_CRC_OUT_CRC            0x4
1667 #define BG_OP_IN_CSUM_OUT_CSUM          0x5
1668 #define BG_OP_IN_CRC_OUT_CSUM           0x6
1669 #define BG_OP_IN_CSUM_OUT_CRC           0x7
1670 #define BG_OP_RAW_MODE                  0x8
1671
1672 struct lpfc_pde5 {
1673         uint32_t word0;
1674 #define pde5_type_SHIFT         24
1675 #define pde5_type_MASK          0x000000ff
1676 #define pde5_type_WORD          word0
1677 #define pde5_rsvd0_SHIFT        0
1678 #define pde5_rsvd0_MASK         0x00ffffff
1679 #define pde5_rsvd0_WORD         word0
1680         uint32_t reftag;        /* Reference Tag Value                  */
1681         uint32_t reftagtr;      /* Reference Tag Translation Value      */
1682 };
1683
1684 struct lpfc_pde6 {
1685         uint32_t word0;
1686 #define pde6_type_SHIFT         24
1687 #define pde6_type_MASK          0x000000ff
1688 #define pde6_type_WORD          word0
1689 #define pde6_rsvd0_SHIFT        0
1690 #define pde6_rsvd0_MASK         0x00ffffff
1691 #define pde6_rsvd0_WORD         word0
1692         uint32_t word1;
1693 #define pde6_rsvd1_SHIFT        26
1694 #define pde6_rsvd1_MASK         0x0000003f
1695 #define pde6_rsvd1_WORD         word1
1696 #define pde6_na_SHIFT           25
1697 #define pde6_na_MASK            0x00000001
1698 #define pde6_na_WORD            word1
1699 #define pde6_rsvd2_SHIFT        16
1700 #define pde6_rsvd2_MASK         0x000001FF
1701 #define pde6_rsvd2_WORD         word1
1702 #define pde6_apptagtr_SHIFT     0
1703 #define pde6_apptagtr_MASK      0x0000ffff
1704 #define pde6_apptagtr_WORD      word1
1705         uint32_t word2;
1706 #define pde6_optx_SHIFT         28
1707 #define pde6_optx_MASK          0x0000000f
1708 #define pde6_optx_WORD          word2
1709 #define pde6_oprx_SHIFT         24
1710 #define pde6_oprx_MASK          0x0000000f
1711 #define pde6_oprx_WORD          word2
1712 #define pde6_nr_SHIFT           23
1713 #define pde6_nr_MASK            0x00000001
1714 #define pde6_nr_WORD            word2
1715 #define pde6_ce_SHIFT           22
1716 #define pde6_ce_MASK            0x00000001
1717 #define pde6_ce_WORD            word2
1718 #define pde6_re_SHIFT           21
1719 #define pde6_re_MASK            0x00000001
1720 #define pde6_re_WORD            word2
1721 #define pde6_ae_SHIFT           20
1722 #define pde6_ae_MASK            0x00000001
1723 #define pde6_ae_WORD            word2
1724 #define pde6_ai_SHIFT           19
1725 #define pde6_ai_MASK            0x00000001
1726 #define pde6_ai_WORD            word2
1727 #define pde6_bs_SHIFT           16
1728 #define pde6_bs_MASK            0x00000007
1729 #define pde6_bs_WORD            word2
1730 #define pde6_apptagval_SHIFT    0
1731 #define pde6_apptagval_MASK     0x0000ffff
1732 #define pde6_apptagval_WORD     word2
1733 };
1734
1735 struct lpfc_pde7 {
1736         uint32_t word0;
1737 #define pde7_type_SHIFT         24
1738 #define pde7_type_MASK          0x000000ff
1739 #define pde7_type_WORD          word0
1740 #define pde7_rsvd0_SHIFT        0
1741 #define pde7_rsvd0_MASK         0x00ffffff
1742 #define pde7_rsvd0_WORD         word0
1743         uint32_t addrHigh;
1744         uint32_t addrLow;
1745 };
1746
1747 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1748
1749 typedef struct {
1750 #ifdef __BIG_ENDIAN_BITFIELD
1751         uint32_t rsvd2:25;
1752         uint32_t acknowledgment:1;
1753         uint32_t version:1;
1754         uint32_t erase_or_prog:1;
1755         uint32_t update_flash:1;
1756         uint32_t update_ram:1;
1757         uint32_t method:1;
1758         uint32_t load_cmplt:1;
1759 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1760         uint32_t load_cmplt:1;
1761         uint32_t method:1;
1762         uint32_t update_ram:1;
1763         uint32_t update_flash:1;
1764         uint32_t erase_or_prog:1;
1765         uint32_t version:1;
1766         uint32_t acknowledgment:1;
1767         uint32_t rsvd2:25;
1768 #endif
1769
1770         uint32_t dl_to_adr_low;
1771         uint32_t dl_to_adr_high;
1772         uint32_t dl_len;
1773         union {
1774                 uint32_t dl_from_mbx_offset;
1775                 struct ulp_bde dl_from_bde;
1776                 struct ulp_bde64 dl_from_bde64;
1777         } un;
1778
1779 } LOAD_SM_VAR;
1780
1781 /* Structure for MB Command READ_NVPARM (02) */
1782
1783 typedef struct {
1784         uint32_t rsvd1[3];      /* Read as all one's */
1785         uint32_t rsvd2;         /* Read as all zero's */
1786         uint32_t portname[2];   /* N_PORT name */
1787         uint32_t nodename[2];   /* NODE name */
1788
1789 #ifdef __BIG_ENDIAN_BITFIELD
1790         uint32_t pref_DID:24;
1791         uint32_t hardAL_PA:8;
1792 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1793         uint32_t hardAL_PA:8;
1794         uint32_t pref_DID:24;
1795 #endif
1796
1797         uint32_t rsvd3[21];     /* Read as all one's */
1798 } READ_NV_VAR;
1799
1800 /* Structure for MB Command WRITE_NVPARMS (03) */
1801
1802 typedef struct {
1803         uint32_t rsvd1[3];      /* Must be all one's */
1804         uint32_t rsvd2;         /* Must be all zero's */
1805         uint32_t portname[2];   /* N_PORT name */
1806         uint32_t nodename[2];   /* NODE name */
1807
1808 #ifdef __BIG_ENDIAN_BITFIELD
1809         uint32_t pref_DID:24;
1810         uint32_t hardAL_PA:8;
1811 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1812         uint32_t hardAL_PA:8;
1813         uint32_t pref_DID:24;
1814 #endif
1815
1816         uint32_t rsvd3[21];     /* Must be all one's */
1817 } WRITE_NV_VAR;
1818
1819 /* Structure for MB Command RUN_BIU_DIAG (04) */
1820 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1821
1822 typedef struct {
1823         uint32_t rsvd1;
1824         union {
1825                 struct {
1826                         struct ulp_bde xmit_bde;
1827                         struct ulp_bde rcv_bde;
1828                 } s1;
1829                 struct {
1830                         struct ulp_bde64 xmit_bde64;
1831                         struct ulp_bde64 rcv_bde64;
1832                 } s2;
1833         } un;
1834 } BIU_DIAG_VAR;
1835
1836 /* Structure for MB command READ_EVENT_LOG (0x38) */
1837 struct READ_EVENT_LOG_VAR {
1838         uint32_t word1;
1839 #define lpfc_event_log_SHIFT    29
1840 #define lpfc_event_log_MASK     0x00000001
1841 #define lpfc_event_log_WORD     word1
1842 #define USE_MAILBOX_RESPONSE    1
1843         uint32_t offset;
1844         struct ulp_bde64 rcv_bde64;
1845 };
1846
1847 /* Structure for MB Command INIT_LINK (05) */
1848
1849 typedef struct {
1850 #ifdef __BIG_ENDIAN_BITFIELD
1851         uint32_t rsvd1:24;
1852         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1853 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1854         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1855         uint32_t rsvd1:24;
1856 #endif
1857
1858 #ifdef __BIG_ENDIAN_BITFIELD
1859         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1860         uint8_t rsvd2;
1861         uint16_t link_flags;
1862 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1863         uint16_t link_flags;
1864         uint8_t rsvd2;
1865         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1866 #endif
1867
1868 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1869 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1870 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1871 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1872 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1873 #define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
1874 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1875
1876 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1877 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1878 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1879
1880         uint32_t link_speed;
1881 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
1882 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
1883 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
1884 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
1885 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
1886 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
1887 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
1888
1889 } INIT_LINK_VAR;
1890
1891 /* Structure for MB Command DOWN_LINK (06) */
1892
1893 typedef struct {
1894         uint32_t rsvd1;
1895 } DOWN_LINK_VAR;
1896
1897 /* Structure for MB Command CONFIG_LINK (07) */
1898
1899 typedef struct {
1900 #ifdef __BIG_ENDIAN_BITFIELD
1901         uint32_t cr:1;
1902         uint32_t ci:1;
1903         uint32_t cr_delay:6;
1904         uint32_t cr_count:8;
1905         uint32_t rsvd1:8;
1906         uint32_t MaxBBC:8;
1907 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1908         uint32_t MaxBBC:8;
1909         uint32_t rsvd1:8;
1910         uint32_t cr_count:8;
1911         uint32_t cr_delay:6;
1912         uint32_t ci:1;
1913         uint32_t cr:1;
1914 #endif
1915
1916         uint32_t myId;
1917         uint32_t rsvd2;
1918         uint32_t edtov;
1919         uint32_t arbtov;
1920         uint32_t ratov;
1921         uint32_t rttov;
1922         uint32_t altov;
1923         uint32_t crtov;
1924         uint32_t citov;
1925 #ifdef __BIG_ENDIAN_BITFIELD
1926         uint32_t rrq_enable:1;
1927         uint32_t rrq_immed:1;
1928         uint32_t rsvd4:29;
1929         uint32_t ack0_enable:1;
1930 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1931         uint32_t ack0_enable:1;
1932         uint32_t rsvd4:29;
1933         uint32_t rrq_immed:1;
1934         uint32_t rrq_enable:1;
1935 #endif
1936 } CONFIG_LINK;
1937
1938 /* Structure for MB Command PART_SLIM (08)
1939  * will be removed since SLI1 is no longer supported!
1940  */
1941 typedef struct {
1942 #ifdef __BIG_ENDIAN_BITFIELD
1943         uint16_t offCiocb;
1944         uint16_t numCiocb;
1945         uint16_t offRiocb;
1946         uint16_t numRiocb;
1947 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1948         uint16_t numCiocb;
1949         uint16_t offCiocb;
1950         uint16_t numRiocb;
1951         uint16_t offRiocb;
1952 #endif
1953 } RING_DEF;
1954
1955 typedef struct {
1956 #ifdef __BIG_ENDIAN_BITFIELD
1957         uint32_t unused1:24;
1958         uint32_t numRing:8;
1959 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1960         uint32_t numRing:8;
1961         uint32_t unused1:24;
1962 #endif
1963
1964         RING_DEF ringdef[4];
1965         uint32_t hbainit;
1966 } PART_SLIM_VAR;
1967
1968 /* Structure for MB Command CONFIG_RING (09) */
1969
1970 typedef struct {
1971 #ifdef __BIG_ENDIAN_BITFIELD
1972         uint32_t unused2:6;
1973         uint32_t recvSeq:1;
1974         uint32_t recvNotify:1;
1975         uint32_t numMask:8;
1976         uint32_t profile:8;
1977         uint32_t unused1:4;
1978         uint32_t ring:4;
1979 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1980         uint32_t ring:4;
1981         uint32_t unused1:4;
1982         uint32_t profile:8;
1983         uint32_t numMask:8;
1984         uint32_t recvNotify:1;
1985         uint32_t recvSeq:1;
1986         uint32_t unused2:6;
1987 #endif
1988
1989 #ifdef __BIG_ENDIAN_BITFIELD
1990         uint16_t maxRespXchg;
1991         uint16_t maxOrigXchg;
1992 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1993         uint16_t maxOrigXchg;
1994         uint16_t maxRespXchg;
1995 #endif
1996
1997         RR_REG rrRegs[6];
1998 } CONFIG_RING_VAR;
1999
2000 /* Structure for MB Command RESET_RING (10) */
2001
2002 typedef struct {
2003         uint32_t ring_no;
2004 } RESET_RING_VAR;
2005
2006 /* Structure for MB Command READ_CONFIG (11) */
2007
2008 typedef struct {
2009 #ifdef __BIG_ENDIAN_BITFIELD
2010         uint32_t cr:1;
2011         uint32_t ci:1;
2012         uint32_t cr_delay:6;
2013         uint32_t cr_count:8;
2014         uint32_t InitBBC:8;
2015         uint32_t MaxBBC:8;
2016 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2017         uint32_t MaxBBC:8;
2018         uint32_t InitBBC:8;
2019         uint32_t cr_count:8;
2020         uint32_t cr_delay:6;
2021         uint32_t ci:1;
2022         uint32_t cr:1;
2023 #endif
2024
2025 #ifdef __BIG_ENDIAN_BITFIELD
2026         uint32_t topology:8;
2027         uint32_t myDid:24;
2028 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2029         uint32_t myDid:24;
2030         uint32_t topology:8;
2031 #endif
2032
2033         /* Defines for topology (defined previously) */
2034 #ifdef __BIG_ENDIAN_BITFIELD
2035         uint32_t AR:1;
2036         uint32_t IR:1;
2037         uint32_t rsvd1:29;
2038         uint32_t ack0:1;
2039 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2040         uint32_t ack0:1;
2041         uint32_t rsvd1:29;
2042         uint32_t IR:1;
2043         uint32_t AR:1;
2044 #endif
2045
2046         uint32_t edtov;
2047         uint32_t arbtov;
2048         uint32_t ratov;
2049         uint32_t rttov;
2050         uint32_t altov;
2051         uint32_t lmt;
2052 #define LMT_RESERVED  0x000    /* Not used */
2053 #define LMT_1Gb       0x004
2054 #define LMT_2Gb       0x008
2055 #define LMT_4Gb       0x040
2056 #define LMT_8Gb       0x080
2057 #define LMT_10Gb      0x100
2058 #define LMT_16Gb      0x200
2059         uint32_t rsvd2;
2060         uint32_t rsvd3;
2061         uint32_t max_xri;
2062         uint32_t max_iocb;
2063         uint32_t max_rpi;
2064         uint32_t avail_xri;
2065         uint32_t avail_iocb;
2066         uint32_t avail_rpi;
2067         uint32_t max_vpi;
2068         uint32_t rsvd4;
2069         uint32_t rsvd5;
2070         uint32_t avail_vpi;
2071 } READ_CONFIG_VAR;
2072
2073 /* Structure for MB Command READ_RCONFIG (12) */
2074
2075 typedef struct {
2076 #ifdef __BIG_ENDIAN_BITFIELD
2077         uint32_t rsvd2:7;
2078         uint32_t recvNotify:1;
2079         uint32_t numMask:8;
2080         uint32_t profile:8;
2081         uint32_t rsvd1:4;
2082         uint32_t ring:4;
2083 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2084         uint32_t ring:4;
2085         uint32_t rsvd1:4;
2086         uint32_t profile:8;
2087         uint32_t numMask:8;
2088         uint32_t recvNotify:1;
2089         uint32_t rsvd2:7;
2090 #endif
2091
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093         uint16_t maxResp;
2094         uint16_t maxOrig;
2095 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2096         uint16_t maxOrig;
2097         uint16_t maxResp;
2098 #endif
2099
2100         RR_REG rrRegs[6];
2101
2102 #ifdef __BIG_ENDIAN_BITFIELD
2103         uint16_t cmdRingOffset;
2104         uint16_t cmdEntryCnt;
2105         uint16_t rspRingOffset;
2106         uint16_t rspEntryCnt;
2107         uint16_t nextCmdOffset;
2108         uint16_t rsvd3;
2109         uint16_t nextRspOffset;
2110         uint16_t rsvd4;
2111 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2112         uint16_t cmdEntryCnt;
2113         uint16_t cmdRingOffset;
2114         uint16_t rspEntryCnt;
2115         uint16_t rspRingOffset;
2116         uint16_t rsvd3;
2117         uint16_t nextCmdOffset;
2118         uint16_t rsvd4;
2119         uint16_t nextRspOffset;
2120 #endif
2121 } READ_RCONF_VAR;
2122
2123 /* Structure for MB Command READ_SPARM (13) */
2124 /* Structure for MB Command READ_SPARM64 (0x8D) */
2125
2126 typedef struct {
2127         uint32_t rsvd1;
2128         uint32_t rsvd2;
2129         union {
2130                 struct ulp_bde sp; /* This BDE points to struct serv_parm
2131                                       structure */
2132                 struct ulp_bde64 sp64;
2133         } un;
2134 #ifdef __BIG_ENDIAN_BITFIELD
2135         uint16_t rsvd3;
2136         uint16_t vpi;
2137 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2138         uint16_t vpi;
2139         uint16_t rsvd3;
2140 #endif
2141 } READ_SPARM_VAR;
2142
2143 /* Structure for MB Command READ_STATUS (14) */
2144
2145 typedef struct {
2146 #ifdef __BIG_ENDIAN_BITFIELD
2147         uint32_t rsvd1:31;
2148         uint32_t clrCounters:1;
2149         uint16_t activeXriCnt;
2150         uint16_t activeRpiCnt;
2151 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2152         uint32_t clrCounters:1;
2153         uint32_t rsvd1:31;
2154         uint16_t activeRpiCnt;
2155         uint16_t activeXriCnt;
2156 #endif
2157
2158         uint32_t xmitByteCnt;
2159         uint32_t rcvByteCnt;
2160         uint32_t xmitFrameCnt;
2161         uint32_t rcvFrameCnt;
2162         uint32_t xmitSeqCnt;
2163         uint32_t rcvSeqCnt;
2164         uint32_t totalOrigExchanges;
2165         uint32_t totalRespExchanges;
2166         uint32_t rcvPbsyCnt;
2167         uint32_t rcvFbsyCnt;
2168 } READ_STATUS_VAR;
2169
2170 /* Structure for MB Command READ_RPI (15) */
2171 /* Structure for MB Command READ_RPI64 (0x8F) */
2172
2173 typedef struct {
2174 #ifdef __BIG_ENDIAN_BITFIELD
2175         uint16_t nextRpi;
2176         uint16_t reqRpi;
2177         uint32_t rsvd2:8;
2178         uint32_t DID:24;
2179 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2180         uint16_t reqRpi;
2181         uint16_t nextRpi;
2182         uint32_t DID:24;
2183         uint32_t rsvd2:8;
2184 #endif
2185
2186         union {
2187                 struct ulp_bde sp;
2188                 struct ulp_bde64 sp64;
2189         } un;
2190
2191 } READ_RPI_VAR;
2192
2193 /* Structure for MB Command READ_XRI (16) */
2194
2195 typedef struct {
2196 #ifdef __BIG_ENDIAN_BITFIELD
2197         uint16_t nextXri;
2198         uint16_t reqXri;
2199         uint16_t rsvd1;
2200         uint16_t rpi;
2201         uint32_t rsvd2:8;
2202         uint32_t DID:24;
2203         uint32_t rsvd3:8;
2204         uint32_t SID:24;
2205         uint32_t rsvd4;
2206         uint8_t seqId;
2207         uint8_t rsvd5;
2208         uint16_t seqCount;
2209         uint16_t oxId;
2210         uint16_t rxId;
2211         uint32_t rsvd6:30;
2212         uint32_t si:1;
2213         uint32_t exchOrig:1;
2214 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2215         uint16_t reqXri;
2216         uint16_t nextXri;
2217         uint16_t rpi;
2218         uint16_t rsvd1;
2219         uint32_t DID:24;
2220         uint32_t rsvd2:8;
2221         uint32_t SID:24;
2222         uint32_t rsvd3:8;
2223         uint32_t rsvd4;
2224         uint16_t seqCount;
2225         uint8_t rsvd5;
2226         uint8_t seqId;
2227         uint16_t rxId;
2228         uint16_t oxId;
2229         uint32_t exchOrig:1;
2230         uint32_t si:1;
2231         uint32_t rsvd6:30;
2232 #endif
2233 } READ_XRI_VAR;
2234
2235 /* Structure for MB Command READ_REV (17) */
2236
2237 typedef struct {
2238 #ifdef __BIG_ENDIAN_BITFIELD
2239         uint32_t cv:1;
2240         uint32_t rr:1;
2241         uint32_t rsvd2:2;
2242         uint32_t v3req:1;
2243         uint32_t v3rsp:1;
2244         uint32_t rsvd1:25;
2245         uint32_t rv:1;
2246 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2247         uint32_t rv:1;
2248         uint32_t rsvd1:25;
2249         uint32_t v3rsp:1;
2250         uint32_t v3req:1;
2251         uint32_t rsvd2:2;
2252         uint32_t rr:1;
2253         uint32_t cv:1;
2254 #endif
2255
2256         uint32_t biuRev;
2257         uint32_t smRev;
2258         union {
2259                 uint32_t smFwRev;
2260                 struct {
2261 #ifdef __BIG_ENDIAN_BITFIELD
2262                         uint8_t ProgType;
2263                         uint8_t ProgId;
2264                         uint16_t ProgVer:4;
2265                         uint16_t ProgRev:4;
2266                         uint16_t ProgFixLvl:2;
2267                         uint16_t ProgDistType:2;
2268                         uint16_t DistCnt:4;
2269 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2270                         uint16_t DistCnt:4;
2271                         uint16_t ProgDistType:2;
2272                         uint16_t ProgFixLvl:2;
2273                         uint16_t ProgRev:4;
2274                         uint16_t ProgVer:4;
2275                         uint8_t ProgId;
2276                         uint8_t ProgType;
2277 #endif
2278
2279                 } b;
2280         } un;
2281         uint32_t endecRev;
2282 #ifdef __BIG_ENDIAN_BITFIELD
2283         uint8_t feaLevelHigh;
2284         uint8_t feaLevelLow;
2285         uint8_t fcphHigh;
2286         uint8_t fcphLow;
2287 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2288         uint8_t fcphLow;
2289         uint8_t fcphHigh;
2290         uint8_t feaLevelLow;
2291         uint8_t feaLevelHigh;
2292 #endif
2293
2294         uint32_t postKernRev;
2295         uint32_t opFwRev;
2296         uint8_t opFwName[16];
2297         uint32_t sli1FwRev;
2298         uint8_t sli1FwName[16];
2299         uint32_t sli2FwRev;
2300         uint8_t sli2FwName[16];
2301         uint32_t sli3Feat;
2302         uint32_t RandomData[6];
2303 } READ_REV_VAR;
2304
2305 /* Structure for MB Command READ_LINK_STAT (18) */
2306
2307 typedef struct {
2308         uint32_t rsvd1;
2309         uint32_t linkFailureCnt;
2310         uint32_t lossSyncCnt;
2311
2312         uint32_t lossSignalCnt;
2313         uint32_t primSeqErrCnt;
2314         uint32_t invalidXmitWord;
2315         uint32_t crcCnt;
2316         uint32_t primSeqTimeout;
2317         uint32_t elasticOverrun;
2318         uint32_t arbTimeout;
2319 } READ_LNK_VAR;
2320
2321 /* Structure for MB Command REG_LOGIN (19) */
2322 /* Structure for MB Command REG_LOGIN64 (0x93) */
2323
2324 typedef struct {
2325 #ifdef __BIG_ENDIAN_BITFIELD
2326         uint16_t rsvd1;
2327         uint16_t rpi;
2328         uint32_t rsvd2:8;
2329         uint32_t did:24;
2330 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2331         uint16_t rpi;
2332         uint16_t rsvd1;
2333         uint32_t did:24;
2334         uint32_t rsvd2:8;
2335 #endif
2336
2337         union {
2338                 struct ulp_bde sp;
2339                 struct ulp_bde64 sp64;
2340         } un;
2341
2342 #ifdef __BIG_ENDIAN_BITFIELD
2343         uint16_t rsvd6;
2344         uint16_t vpi;
2345 #else /* __LITTLE_ENDIAN_BITFIELD */
2346         uint16_t vpi;
2347         uint16_t rsvd6;
2348 #endif
2349
2350 } REG_LOGIN_VAR;
2351
2352 /* Word 30 contents for REG_LOGIN */
2353 typedef union {
2354         struct {
2355 #ifdef __BIG_ENDIAN_BITFIELD
2356                 uint16_t rsvd1:12;
2357                 uint16_t wd30_class:4;
2358                 uint16_t xri;
2359 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2360                 uint16_t xri;
2361                 uint16_t wd30_class:4;
2362                 uint16_t rsvd1:12;
2363 #endif
2364         } f;
2365         uint32_t word;
2366 } REG_WD30;
2367
2368 /* Structure for MB Command UNREG_LOGIN (20) */
2369
2370 typedef struct {
2371 #ifdef __BIG_ENDIAN_BITFIELD
2372         uint16_t rsvd1;
2373         uint16_t rpi;
2374         uint32_t rsvd2;
2375         uint32_t rsvd3;
2376         uint32_t rsvd4;
2377         uint32_t rsvd5;
2378         uint16_t rsvd6;
2379         uint16_t vpi;
2380 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2381         uint16_t rpi;
2382         uint16_t rsvd1;
2383         uint32_t rsvd2;
2384         uint32_t rsvd3;
2385         uint32_t rsvd4;
2386         uint32_t rsvd5;
2387         uint16_t vpi;
2388         uint16_t rsvd6;
2389 #endif
2390 } UNREG_LOGIN_VAR;
2391
2392 /* Structure for MB Command REG_VPI (0x96) */
2393 typedef struct {
2394 #ifdef __BIG_ENDIAN_BITFIELD
2395         uint32_t rsvd1;
2396         uint32_t rsvd2:7;
2397         uint32_t upd:1;
2398         uint32_t sid:24;
2399         uint32_t wwn[2];
2400         uint32_t rsvd5;
2401         uint16_t vfi;
2402         uint16_t vpi;
2403 #else   /*  __LITTLE_ENDIAN */
2404         uint32_t rsvd1;
2405         uint32_t sid:24;
2406         uint32_t upd:1;
2407         uint32_t rsvd2:7;
2408         uint32_t wwn[2];
2409         uint32_t rsvd5;
2410         uint16_t vpi;
2411         uint16_t vfi;
2412 #endif
2413 } REG_VPI_VAR;
2414
2415 /* Structure for MB Command UNREG_VPI (0x97) */
2416 typedef struct {
2417         uint32_t rsvd1;
2418 #ifdef __BIG_ENDIAN_BITFIELD
2419         uint16_t rsvd2;
2420         uint16_t sli4_vpi;
2421 #else   /*  __LITTLE_ENDIAN */
2422         uint16_t sli4_vpi;
2423         uint16_t rsvd2;
2424 #endif
2425         uint32_t rsvd3;
2426         uint32_t rsvd4;
2427         uint32_t rsvd5;
2428 #ifdef __BIG_ENDIAN_BITFIELD
2429         uint16_t rsvd6;
2430         uint16_t vpi;
2431 #else   /*  __LITTLE_ENDIAN */
2432         uint16_t vpi;
2433         uint16_t rsvd6;
2434 #endif
2435 } UNREG_VPI_VAR;
2436
2437 /* Structure for MB Command UNREG_D_ID (0x23) */
2438
2439 typedef struct {
2440         uint32_t did;
2441         uint32_t rsvd2;
2442         uint32_t rsvd3;
2443         uint32_t rsvd4;
2444         uint32_t rsvd5;
2445 #ifdef __BIG_ENDIAN_BITFIELD
2446         uint16_t rsvd6;
2447         uint16_t vpi;
2448 #else
2449         uint16_t vpi;
2450         uint16_t rsvd6;
2451 #endif
2452 } UNREG_D_ID_VAR;
2453
2454 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2455 struct lpfc_mbx_read_top {
2456         uint32_t eventTag;      /* Event tag */
2457         uint32_t word2;
2458 #define lpfc_mbx_read_top_fa_SHIFT              12
2459 #define lpfc_mbx_read_top_fa_MASK               0x00000001
2460 #define lpfc_mbx_read_top_fa_WORD               word2
2461 #define lpfc_mbx_read_top_mm_SHIFT              11
2462 #define lpfc_mbx_read_top_mm_MASK               0x00000001
2463 #define lpfc_mbx_read_top_mm_WORD               word2
2464 #define lpfc_mbx_read_top_pb_SHIFT              9
2465 #define lpfc_mbx_read_top_pb_MASK               0X00000001
2466 #define lpfc_mbx_read_top_pb_WORD               word2
2467 #define lpfc_mbx_read_top_il_SHIFT              8
2468 #define lpfc_mbx_read_top_il_MASK               0x00000001
2469 #define lpfc_mbx_read_top_il_WORD               word2
2470 #define lpfc_mbx_read_top_att_type_SHIFT        0
2471 #define lpfc_mbx_read_top_att_type_MASK         0x000000FF
2472 #define lpfc_mbx_read_top_att_type_WORD         word2
2473 #define LPFC_ATT_RESERVED    0x00       /* Reserved - attType */
2474 #define LPFC_ATT_LINK_UP     0x01       /* Link is up */
2475 #define LPFC_ATT_LINK_DOWN   0x02       /* Link is down */
2476         uint32_t word3;
2477 #define lpfc_mbx_read_top_alpa_granted_SHIFT    24
2478 #define lpfc_mbx_read_top_alpa_granted_MASK     0x000000FF
2479 #define lpfc_mbx_read_top_alpa_granted_WORD     word3
2480 #define lpfc_mbx_read_top_lip_alps_SHIFT        16
2481 #define lpfc_mbx_read_top_lip_alps_MASK         0x000000FF
2482 #define lpfc_mbx_read_top_lip_alps_WORD         word3
2483 #define lpfc_mbx_read_top_lip_type_SHIFT        8
2484 #define lpfc_mbx_read_top_lip_type_MASK         0x000000FF
2485 #define lpfc_mbx_read_top_lip_type_WORD         word3
2486 #define lpfc_mbx_read_top_topology_SHIFT        0
2487 #define lpfc_mbx_read_top_topology_MASK         0x000000FF
2488 #define lpfc_mbx_read_top_topology_WORD         word3
2489 #define LPFC_TOPOLOGY_PT_PT 0x01        /* Topology is pt-pt / pt-fabric */
2490 #define LPFC_TOPOLOGY_LOOP  0x02        /* Topology is FC-AL */
2491 #define LPFC_TOPOLOGY_MM    0x05        /* maint mode zephtr to menlo */
2492         /* store the LILP AL_PA position map into */
2493         struct ulp_bde64 lilpBde64;
2494 #define LPFC_ALPA_MAP_SIZE      128
2495         uint32_t word7;
2496 #define lpfc_mbx_read_top_ld_lu_SHIFT           31
2497 #define lpfc_mbx_read_top_ld_lu_MASK            0x00000001
2498 #define lpfc_mbx_read_top_ld_lu_WORD            word7
2499 #define lpfc_mbx_read_top_ld_tf_SHIFT           30
2500 #define lpfc_mbx_read_top_ld_tf_MASK            0x00000001
2501 #define lpfc_mbx_read_top_ld_tf_WORD            word7
2502 #define lpfc_mbx_read_top_ld_link_spd_SHIFT     8
2503 #define lpfc_mbx_read_top_ld_link_spd_MASK      0x000000FF
2504 #define lpfc_mbx_read_top_ld_link_spd_WORD      word7
2505 #define lpfc_mbx_read_top_ld_nl_port_SHIFT      4
2506 #define lpfc_mbx_read_top_ld_nl_port_MASK       0x0000000F
2507 #define lpfc_mbx_read_top_ld_nl_port_WORD       word7
2508 #define lpfc_mbx_read_top_ld_tx_SHIFT           2
2509 #define lpfc_mbx_read_top_ld_tx_MASK            0x00000003
2510 #define lpfc_mbx_read_top_ld_tx_WORD            word7
2511 #define lpfc_mbx_read_top_ld_rx_SHIFT           0
2512 #define lpfc_mbx_read_top_ld_rx_MASK            0x00000003
2513 #define lpfc_mbx_read_top_ld_rx_WORD            word7
2514         uint32_t word8;
2515 #define lpfc_mbx_read_top_lu_SHIFT              31
2516 #define lpfc_mbx_read_top_lu_MASK               0x00000001
2517 #define lpfc_mbx_read_top_lu_WORD               word8
2518 #define lpfc_mbx_read_top_tf_SHIFT              30
2519 #define lpfc_mbx_read_top_tf_MASK               0x00000001
2520 #define lpfc_mbx_read_top_tf_WORD               word8
2521 #define lpfc_mbx_read_top_link_spd_SHIFT        8
2522 #define lpfc_mbx_read_top_link_spd_MASK         0x000000FF
2523 #define lpfc_mbx_read_top_link_spd_WORD         word8
2524 #define lpfc_mbx_read_top_nl_port_SHIFT         4
2525 #define lpfc_mbx_read_top_nl_port_MASK          0x0000000F
2526 #define lpfc_mbx_read_top_nl_port_WORD          word8
2527 #define lpfc_mbx_read_top_tx_SHIFT              2
2528 #define lpfc_mbx_read_top_tx_MASK               0x00000003
2529 #define lpfc_mbx_read_top_tx_WORD               word8
2530 #define lpfc_mbx_read_top_rx_SHIFT              0
2531 #define lpfc_mbx_read_top_rx_MASK               0x00000003
2532 #define lpfc_mbx_read_top_rx_WORD               word8
2533 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2534 #define LPFC_LINK_SPEED_1GHZ    0x04
2535 #define LPFC_LINK_SPEED_2GHZ    0x08
2536 #define LPFC_LINK_SPEED_4GHZ    0x10
2537 #define LPFC_LINK_SPEED_8GHZ    0x20
2538 #define LPFC_LINK_SPEED_10GHZ   0x40
2539 #define LPFC_LINK_SPEED_16GHZ   0x80
2540 };
2541
2542 /* Structure for MB Command CLEAR_LA (22) */
2543
2544 typedef struct {
2545         uint32_t eventTag;      /* Event tag */
2546         uint32_t rsvd1;
2547 } CLEAR_LA_VAR;
2548
2549 /* Structure for MB Command DUMP */
2550
2551 typedef struct {
2552 #ifdef __BIG_ENDIAN_BITFIELD
2553         uint32_t rsvd:25;
2554         uint32_t ra:1;
2555         uint32_t co:1;
2556         uint32_t cv:1;
2557         uint32_t type:4;
2558         uint32_t entry_index:16;
2559         uint32_t region_id:16;
2560 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2561         uint32_t type:4;
2562         uint32_t cv:1;
2563         uint32_t co:1;
2564         uint32_t ra:1;
2565         uint32_t rsvd:25;
2566         uint32_t region_id:16;
2567         uint32_t entry_index:16;
2568 #endif
2569
2570         uint32_t sli4_length;
2571         uint32_t word_cnt;
2572         uint32_t resp_offset;
2573 } DUMP_VAR;
2574
2575 #define  DMP_MEM_REG             0x1
2576 #define  DMP_NV_PARAMS           0x2
2577 #define  DMP_LMSD                0x3 /* Link Module Serial Data */
2578 #define  DMP_WELL_KNOWN          0x4
2579
2580 #define  DMP_REGION_VPD          0xe
2581 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2582 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2583 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2584
2585 #define  DMP_REGION_VPORT        0x16   /* VPort info region */
2586 #define  DMP_VPORT_REGION_SIZE   0x200
2587 #define  DMP_MBOX_OFFSET_WORD    0x5
2588
2589 #define  DMP_REGION_23           0x17   /* fcoe param  and port state region */
2590 #define  DMP_RGN23_SIZE          0x400
2591
2592 #define  WAKE_UP_PARMS_REGION_ID    4
2593 #define  WAKE_UP_PARMS_WORD_SIZE   15
2594
2595 struct vport_rec {
2596         uint8_t wwpn[8];
2597         uint8_t wwnn[8];
2598 };
2599
2600 #define VPORT_INFO_SIG 0x32324752
2601 #define VPORT_INFO_REV_MASK 0xff
2602 #define VPORT_INFO_REV 0x1
2603 #define MAX_STATIC_VPORT_COUNT 16
2604 struct static_vport_info {
2605         uint32_t                signature;
2606         uint32_t                rev;
2607         struct vport_rec        vport_list[MAX_STATIC_VPORT_COUNT];
2608         uint32_t                resvd[66];
2609 };
2610
2611 /* Option rom version structure */
2612 struct prog_id {
2613 #ifdef __BIG_ENDIAN_BITFIELD
2614         uint8_t  type;
2615         uint8_t  id;
2616         uint32_t ver:4;  /* Major Version */
2617         uint32_t rev:4;  /* Revision */
2618         uint32_t lev:2;  /* Level */
2619         uint32_t dist:2; /* Dist Type */
2620         uint32_t num:4;  /* number after dist type */
2621 #else /*  __LITTLE_ENDIAN_BITFIELD */
2622         uint32_t num:4;  /* number after dist type */
2623         uint32_t dist:2; /* Dist Type */
2624         uint32_t lev:2;  /* Level */
2625         uint32_t rev:4;  /* Revision */
2626         uint32_t ver:4;  /* Major Version */
2627         uint8_t  id;
2628         uint8_t  type;
2629 #endif
2630 };
2631
2632 /* Structure for MB Command UPDATE_CFG (0x1B) */
2633
2634 struct update_cfg_var {
2635 #ifdef __BIG_ENDIAN_BITFIELD
2636         uint32_t rsvd2:16;
2637         uint32_t type:8;
2638         uint32_t rsvd:1;
2639         uint32_t ra:1;
2640         uint32_t co:1;
2641         uint32_t cv:1;
2642         uint32_t req:4;
2643         uint32_t entry_length:16;
2644         uint32_t region_id:16;
2645 #else  /*  __LITTLE_ENDIAN_BITFIELD */
2646         uint32_t req:4;
2647         uint32_t cv:1;
2648         uint32_t co:1;
2649         uint32_t ra:1;
2650         uint32_t rsvd:1;
2651         uint32_t type:8;
2652         uint32_t rsvd2:16;
2653         uint32_t region_id:16;
2654         uint32_t entry_length:16;
2655 #endif
2656
2657         uint32_t resp_info;
2658         uint32_t byte_cnt;
2659         uint32_t data_offset;
2660 };
2661
2662 struct hbq_mask {
2663 #ifdef __BIG_ENDIAN_BITFIELD
2664         uint8_t tmatch;
2665         uint8_t tmask;
2666         uint8_t rctlmatch;
2667         uint8_t rctlmask;
2668 #else   /*  __LITTLE_ENDIAN */
2669         uint8_t rctlmask;
2670         uint8_t rctlmatch;
2671         uint8_t tmask;
2672         uint8_t tmatch;
2673 #endif
2674 };
2675
2676
2677 /* Structure for MB Command CONFIG_HBQ (7c) */
2678
2679 struct config_hbq_var {
2680 #ifdef __BIG_ENDIAN_BITFIELD
2681         uint32_t rsvd1      :7;
2682         uint32_t recvNotify :1;     /* Receive Notification */
2683         uint32_t numMask    :8;     /* # Mask Entries       */
2684         uint32_t profile    :8;     /* Selection Profile    */
2685         uint32_t rsvd2      :8;
2686 #else   /*  __LITTLE_ENDIAN */
2687         uint32_t rsvd2      :8;
2688         uint32_t profile    :8;     /* Selection Profile    */
2689         uint32_t numMask    :8;     /* # Mask Entries       */
2690         uint32_t recvNotify :1;     /* Receive Notification */
2691         uint32_t rsvd1      :7;
2692 #endif
2693
2694 #ifdef __BIG_ENDIAN_BITFIELD
2695         uint32_t hbqId      :16;
2696         uint32_t rsvd3      :12;
2697         uint32_t ringMask   :4;
2698 #else   /*  __LITTLE_ENDIAN */
2699         uint32_t ringMask   :4;
2700         uint32_t rsvd3      :12;
2701         uint32_t hbqId      :16;
2702 #endif
2703
2704 #ifdef __BIG_ENDIAN_BITFIELD
2705         uint32_t entry_count :16;
2706         uint32_t rsvd4        :8;
2707         uint32_t headerLen    :8;
2708 #else   /*  __LITTLE_ENDIAN */
2709         uint32_t headerLen    :8;
2710         uint32_t rsvd4        :8;
2711         uint32_t entry_count :16;
2712 #endif
2713
2714         uint32_t hbqaddrLow;
2715         uint32_t hbqaddrHigh;
2716
2717 #ifdef __BIG_ENDIAN_BITFIELD
2718         uint32_t rsvd5      :31;
2719         uint32_t logEntry   :1;
2720 #else   /*  __LITTLE_ENDIAN */
2721         uint32_t logEntry   :1;
2722         uint32_t rsvd5      :31;
2723 #endif
2724
2725         uint32_t rsvd6;    /* w7 */
2726         uint32_t rsvd7;    /* w8 */
2727         uint32_t rsvd8;    /* w9 */
2728
2729         struct hbq_mask hbqMasks[6];
2730
2731
2732         union {
2733                 uint32_t allprofiles[12];
2734
2735                 struct {
2736                         #ifdef __BIG_ENDIAN_BITFIELD
2737                                 uint32_t        seqlenoff       :16;
2738                                 uint32_t        maxlen          :16;
2739                         #else   /*  __LITTLE_ENDIAN */
2740                                 uint32_t        maxlen          :16;
2741                                 uint32_t        seqlenoff       :16;
2742                         #endif
2743                         #ifdef __BIG_ENDIAN_BITFIELD
2744                                 uint32_t        rsvd1           :28;
2745                                 uint32_t        seqlenbcnt      :4;
2746                         #else   /*  __LITTLE_ENDIAN */
2747                                 uint32_t        seqlenbcnt      :4;
2748                                 uint32_t        rsvd1           :28;
2749                         #endif
2750                         uint32_t rsvd[10];
2751                 } profile2;
2752
2753                 struct {
2754                         #ifdef __BIG_ENDIAN_BITFIELD
2755                                 uint32_t        seqlenoff       :16;
2756                                 uint32_t        maxlen          :16;
2757                         #else   /*  __LITTLE_ENDIAN */
2758                                 uint32_t        maxlen          :16;
2759                                 uint32_t        seqlenoff       :16;
2760                         #endif
2761                         #ifdef __BIG_ENDIAN_BITFIELD
2762                                 uint32_t        cmdcodeoff      :28;
2763                                 uint32_t        rsvd1           :12;
2764                                 uint32_t        seqlenbcnt      :4;
2765                         #else   /*  __LITTLE_ENDIAN */
2766                                 uint32_t        seqlenbcnt      :4;
2767                                 uint32_t        rsvd1           :12;
2768                                 uint32_t        cmdcodeoff      :28;
2769                         #endif
2770                         uint32_t cmdmatch[8];
2771
2772                         uint32_t rsvd[2];
2773                 } profile3;
2774
2775                 struct {
2776                         #ifdef __BIG_ENDIAN_BITFIELD
2777                                 uint32_t        seqlenoff       :16;
2778                                 uint32_t        maxlen          :16;
2779                         #else   /*  __LITTLE_ENDIAN */
2780                                 uint32_t        maxlen          :16;
2781                                 uint32_t        seqlenoff       :16;
2782                         #endif
2783                         #ifdef __BIG_ENDIAN_BITFIELD
2784                                 uint32_t        cmdcodeoff      :28;
2785                                 uint32_t        rsvd1           :12;
2786                                 uint32_t        seqlenbcnt      :4;
2787                         #else   /*  __LITTLE_ENDIAN */
2788                                 uint32_t        seqlenbcnt      :4;
2789                                 uint32_t        rsvd1           :12;
2790                                 uint32_t        cmdcodeoff      :28;
2791                         #endif
2792                         uint32_t cmdmatch[8];
2793
2794                         uint32_t rsvd[2];
2795                 } profile5;
2796
2797         } profiles;
2798
2799 };
2800
2801
2802
2803 /* Structure for MB Command CONFIG_PORT (0x88) */
2804 typedef struct {
2805 #ifdef __BIG_ENDIAN_BITFIELD
2806         uint32_t cBE       :  1;
2807         uint32_t cET       :  1;
2808         uint32_t cHpcb     :  1;
2809         uint32_t cMA       :  1;
2810         uint32_t sli_mode  :  4;
2811         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2812                                         * config block */
2813 #else   /*  __LITTLE_ENDIAN */
2814         uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
2815                                         * config block */
2816         uint32_t sli_mode  :  4;
2817         uint32_t cMA       :  1;
2818         uint32_t cHpcb     :  1;
2819         uint32_t cET       :  1;
2820         uint32_t cBE       :  1;
2821 #endif
2822
2823         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2824         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2825         uint32_t hbainit[5];
2826 #ifdef __BIG_ENDIAN_BITFIELD
2827         uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
2828         uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
2829 #else   /*  __LITTLE_ENDIAN */
2830         uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
2831         uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
2832 #endif
2833
2834 #ifdef __BIG_ENDIAN_BITFIELD
2835         uint32_t rsvd1     : 19;  /* Reserved                             */
2836         uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2837         uint32_t casabt    :  1;  /* Configure async abts status notice   */
2838         uint32_t rsvd2     :  2;  /* Reserved                             */
2839         uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2840         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2841         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2842         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2843         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2844         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2845         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2846         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2847         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2848 #else   /*  __LITTLE_ENDIAN */
2849         uint32_t cmr       :  1;  /* Configure Max RPIs                   */
2850         uint32_t cmx       :  1;  /* Configure Max XRIs                   */
2851         uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
2852         uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
2853         uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
2854         uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
2855         uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
2856         uint32_t cmv       :  1;  /* Configure Max VPIs                   */
2857         uint32_t cbg       :  1;  /* Configure BlockGuard                 */
2858         uint32_t rsvd2     :  2;  /* Reserved                             */
2859         uint32_t casabt    :  1;  /* Configure async abts status notice   */
2860         uint32_t cdss      :  1;  /* Configure Data Security SLI          */
2861         uint32_t rsvd1     : 19;  /* Reserved                             */
2862 #endif
2863 #ifdef __BIG_ENDIAN_BITFIELD
2864         uint32_t rsvd3     : 19;  /* Reserved                             */
2865         uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2866         uint32_t gasabt    :  1;  /* Grant async abts status notice       */
2867         uint32_t rsvd4     :  2;  /* Reserved                             */
2868         uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2869         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2870         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2871         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2872         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2873         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2874         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2875         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2876         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2877 #else   /*  __LITTLE_ENDIAN */
2878         uint32_t gmr       :  1;  /* Grant Max RPIs                       */
2879         uint32_t gmx       :  1;  /* Grant Max XRIs                       */
2880         uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
2881         uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
2882         uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
2883         uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
2884         uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
2885         uint32_t gmv       :  1;  /* Grant Max VPIs                       */
2886         uint32_t gbg       :  1;  /* Grant BlockGuard                     */
2887         uint32_t rsvd4     :  2;  /* Reserved                             */
2888         uint32_t gasabt    :  1;  /* Grant async abts status notice       */
2889         uint32_t gdss      :  1;  /* Configure Data Security SLI          */
2890         uint32_t rsvd3     : 19;  /* Reserved                             */
2891 #endif
2892
2893 #ifdef __BIG_ENDIAN_BITFIELD
2894         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2895         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2896 #else   /*  __LITTLE_ENDIAN */
2897         uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
2898         uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
2899 #endif
2900
2901 #ifdef __BIG_ENDIAN_BITFIELD
2902         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2903         uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2904 #else   /*  __LITTLE_ENDIAN */
2905         uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
2906         uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
2907 #endif
2908
2909         uint32_t rsvd6;           /* Reserved                             */
2910
2911 #ifdef __BIG_ENDIAN_BITFIELD
2912         uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2913         uint32_t fips_level : 4;   /* FIPS Level                           */
2914         uint32_t sec_err    : 9;   /* security crypto error                */
2915         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2916 #else   /*  __LITTLE_ENDIAN */
2917         uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
2918         uint32_t sec_err    : 9;   /* security crypto error                */
2919         uint32_t fips_level : 4;   /* FIPS Level                           */
2920         uint32_t fips_rev   : 3;   /* FIPS Spec Revision                   */
2921 #endif
2922
2923 } CONFIG_PORT_VAR;
2924
2925 /* Structure for MB Command CONFIG_MSI (0x30) */
2926 struct config_msi_var {
2927 #ifdef __BIG_ENDIAN_BITFIELD
2928         uint32_t dfltMsgNum:8;  /* Default message number            */
2929         uint32_t rsvd1:11;      /* Reserved                          */
2930         uint32_t NID:5;         /* Number of secondary attention IDs */
2931         uint32_t rsvd2:5;       /* Reserved                          */
2932         uint32_t dfltPresent:1; /* Default message number present    */
2933         uint32_t addFlag:1;     /* Add association flag              */
2934         uint32_t reportFlag:1;  /* Report association flag           */
2935 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2936         uint32_t reportFlag:1;  /* Report association flag           */
2937         uint32_t addFlag:1;     /* Add association flag              */
2938         uint32_t dfltPresent:1; /* Default message number present    */
2939         uint32_t rsvd2:5;       /* Reserved                          */
2940         uint32_t NID:5;         /* Number of secondary attention IDs */
2941         uint32_t rsvd1:11;      /* Reserved                          */
2942         uint32_t dfltMsgNum:8;  /* Default message number            */
2943 #endif
2944         uint32_t attentionConditions[2];
2945         uint8_t  attentionId[16];
2946         uint8_t  messageNumberByHA[64];
2947         uint8_t  messageNumberByID[16];
2948         uint32_t autoClearHA[2];
2949 #ifdef __BIG_ENDIAN_BITFIELD
2950         uint32_t rsvd3:16;
2951         uint32_t autoClearID:16;
2952 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2953         uint32_t autoClearID:16;
2954         uint32_t rsvd3:16;
2955 #endif
2956         uint32_t rsvd4;
2957 };
2958
2959 /* SLI-2 Port Control Block */
2960
2961 /* SLIM POINTER */
2962 #define SLIMOFF 0x30            /* WORD */
2963
2964 typedef struct _SLI2_RDSC {
2965         uint32_t cmdEntries;
2966         uint32_t cmdAddrLow;
2967         uint32_t cmdAddrHigh;
2968
2969         uint32_t rspEntries;
2970         uint32_t rspAddrLow;
2971         uint32_t rspAddrHigh;
2972 } SLI2_RDSC;
2973
2974 typedef struct _PCB {
2975 #ifdef __BIG_ENDIAN_BITFIELD
2976         uint32_t type:8;
2977 #define TYPE_NATIVE_SLI2       0x01
2978         uint32_t feature:8;
2979 #define FEATURE_INITIAL_SLI2   0x01
2980         uint32_t rsvd:12;
2981         uint32_t maxRing:4;
2982 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2983         uint32_t maxRing:4;
2984         uint32_t rsvd:12;
2985         uint32_t feature:8;
2986 #define FEATURE_INITIAL_SLI2   0x01
2987         uint32_t type:8;
2988 #define TYPE_NATIVE_SLI2       0x01
2989 #endif
2990
2991         uint32_t mailBoxSize;
2992         uint32_t mbAddrLow;
2993         uint32_t mbAddrHigh;
2994
2995         uint32_t hgpAddrLow;
2996         uint32_t hgpAddrHigh;
2997
2998         uint32_t pgpAddrLow;
2999         uint32_t pgpAddrHigh;
3000         SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3001 } PCB_t;
3002
3003 /* NEW_FEATURE */
3004 typedef struct {
3005 #ifdef __BIG_ENDIAN_BITFIELD
3006         uint32_t rsvd0:27;
3007         uint32_t discardFarp:1;
3008         uint32_t IPEnable:1;
3009         uint32_t nodeName:1;
3010         uint32_t portName:1;
3011         uint32_t filterEnable:1;
3012 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3013         uint32_t filterEnable:1;
3014         uint32_t portName:1;
3015         uint32_t nodeName:1;
3016         uint32_t IPEnable:1;
3017         uint32_t discardFarp:1;
3018         uint32_t rsvd:27;
3019 #endif
3020
3021         uint8_t portname[8];    /* Used to be struct lpfc_name */
3022         uint8_t nodename[8];
3023         uint32_t rsvd1;
3024         uint32_t rsvd2;
3025         uint32_t rsvd3;
3026         uint32_t IPAddress;
3027 } CONFIG_FARP_VAR;
3028
3029 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3030
3031 typedef struct {
3032 #ifdef __BIG_ENDIAN_BITFIELD
3033         uint32_t rsvd:30;
3034         uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3035 #else /*  __LITTLE_ENDIAN */
3036         uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3037         uint32_t rsvd:30;
3038 #endif
3039 } ASYNCEVT_ENABLE_VAR;
3040
3041 /* Union of all Mailbox Command types */
3042 #define MAILBOX_CMD_WSIZE       32
3043 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3044 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3045 #define MAILBOX_EXT_WSIZE       512
3046 #define MAILBOX_EXT_SIZE        (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3047 #define MAILBOX_HBA_EXT_OFFSET  0x100
3048 /* max mbox xmit size is a page size for sysfs IO operations */
3049 #define MAILBOX_SYSFS_MAX       4096
3050
3051 typedef union {
3052         uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3053                                                     * feature/max ring number
3054                                                     */
3055         LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
3056         READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
3057         WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
3058         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
3059         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
3060         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
3061         CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
3062         PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
3063         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
3064         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
3065         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
3066         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
3067         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
3068         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
3069         READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
3070         READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
3071         READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
3072         READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
3073         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
3074         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
3075         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
3076         DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
3077         UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
3078         CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
3079                                          * NEW_FEATURE
3080                                          */
3081         struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3082         struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3083         CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
3084         struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3085         REG_VPI_VAR varRegVpi;          /* cmd = 0x96 (REG_VPI) */
3086         UNREG_VPI_VAR varUnregVpi;      /* cmd = 0x97 (UNREG_VPI) */
3087         ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3088         struct READ_EVENT_LOG_VAR varRdEventLog;        /* cmd = 0x38
3089                                                          * (READ_EVENT_LOG)
3090                                                          */
3091         struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3092 } MAILVARIANTS;
3093
3094 /*
3095  * SLI-2 specific structures
3096  */
3097
3098 struct lpfc_hgp {
3099         __le32 cmdPutInx;
3100         __le32 rspGetInx;
3101 };
3102
3103 struct lpfc_pgp {
3104         __le32 cmdGetInx;
3105         __le32 rspPutInx;
3106 };
3107
3108 struct sli2_desc {
3109         uint32_t unused1[16];
3110         struct lpfc_hgp host[MAX_SLI3_RINGS];
3111         struct lpfc_pgp port[MAX_SLI3_RINGS];
3112 };
3113
3114 struct sli3_desc {
3115         struct lpfc_hgp host[MAX_SLI3_RINGS];
3116         uint32_t reserved[8];
3117         uint32_t hbq_put[16];
3118 };
3119
3120 struct sli3_pgp {
3121         struct lpfc_pgp port[MAX_SLI3_RINGS];
3122         uint32_t hbq_get[16];
3123 };
3124
3125 union sli_var {
3126         struct sli2_desc        s2;
3127         struct sli3_desc        s3;
3128         struct sli3_pgp         s3_pgp;
3129 };
3130
3131 typedef struct {
3132 #ifdef __BIG_ENDIAN_BITFIELD
3133         uint16_t mbxStatus;
3134         uint8_t mbxCommand;
3135         uint8_t mbxReserved:6;
3136         uint8_t mbxHc:1;
3137         uint8_t mbxOwner:1;     /* Low order bit first word */
3138 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3139         uint8_t mbxOwner:1;     /* Low order bit first word */
3140         uint8_t mbxHc:1;
3141         uint8_t mbxReserved:6;
3142         uint8_t mbxCommand;
3143         uint16_t mbxStatus;
3144 #endif
3145
3146         MAILVARIANTS un;
3147         union sli_var us;
3148 } MAILBOX_t;
3149
3150 /*
3151  *    Begin Structure Definitions for IOCB Commands
3152  */
3153
3154 typedef struct {
3155 #ifdef __BIG_ENDIAN_BITFIELD
3156         uint8_t statAction;
3157         uint8_t statRsn;
3158         uint8_t statBaExp;
3159         uint8_t statLocalError;
3160 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3161         uint8_t statLocalError;
3162         uint8_t statBaExp;
3163         uint8_t statRsn;
3164         uint8_t statAction;
3165 #endif
3166         /* statRsn  P/F_RJT reason codes */
3167 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
3168 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
3169 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
3170 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
3171 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
3172 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
3173 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
3174 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
3175 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
3176 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
3177 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
3178 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
3179 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
3180 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
3181 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
3182 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
3183 #define RJT_XCHG_ERR       0x11 /* Exchange error */
3184 #define RJT_PROT_ERR       0x12 /* Protocol error */
3185 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
3186 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3187 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3188 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
3189 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
3190 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
3191 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
3192 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
3193
3194 #define IOERR_SUCCESS                 0x00      /* statLocalError */
3195 #define IOERR_MISSING_CONTINUE        0x01
3196 #define IOERR_SEQUENCE_TIMEOUT        0x02
3197 #define IOERR_INTERNAL_ERROR          0x03
3198 #define IOERR_INVALID_RPI             0x04
3199 #define IOERR_NO_XRI                  0x05
3200 #define IOERR_ILLEGAL_COMMAND         0x06
3201 #define IOERR_XCHG_DROPPED            0x07
3202 #define IOERR_ILLEGAL_FIELD           0x08
3203 #define IOERR_BAD_CONTINUE            0x09
3204 #define IOERR_TOO_MANY_BUFFERS        0x0A
3205 #define IOERR_RCV_BUFFER_WAITING      0x0B
3206 #define IOERR_NO_CONNECTION           0x0C
3207 #define IOERR_TX_DMA_FAILED           0x0D
3208 #define IOERR_RX_DMA_FAILED           0x0E
3209 #define IOERR_ILLEGAL_FRAME           0x0F
3210 #define IOERR_EXTRA_DATA              0x10
3211 #define IOERR_NO_RESOURCES            0x11
3212 #define IOERR_RESERVED                0x12
3213 #define IOERR_ILLEGAL_LENGTH          0x13
3214 #define IOERR_UNSUPPORTED_FEATURE     0x14
3215 #define IOERR_ABORT_IN_PROGRESS       0x15
3216 #define IOERR_ABORT_REQUESTED         0x16
3217 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3218 #define IOERR_LOOP_OPEN_FAILURE       0x18
3219 #define IOERR_RING_RESET              0x19
3220 #define IOERR_LINK_DOWN               0x1A
3221 #define IOERR_CORRUPTED_DATA          0x1B
3222 #define IOERR_CORRUPTED_RPI           0x1C
3223 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3224 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3225 #define IOERR_DUP_FRAME               0x1F
3226 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
3227 #define IOERR_BAD_HOST_ADDRESS        0x21
3228 #define IOERR_RCV_HDRBUF_WAITING      0x22
3229 #define IOERR_MISSING_HDR_BUFFER      0x23
3230 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3231 #define IOERR_ABORTMULT_REQUESTED     0x25
3232 #define IOERR_BUFFER_SHORTAGE         0x28
3233 #define IOERR_DEFAULT                 0x29
3234 #define IOERR_CNT                     0x2A
3235 #define IOERR_SLER_FAILURE            0x46
3236 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3237 #define IOERR_SLER_REC_RJT_ERR        0x48
3238 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3239 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3240 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3241 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3242 #define IOERR_SLER_ABTS_ERR           0x4E
3243 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR           0xF0
3244 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR   0xF1
3245 #define IOERR_ELXSEC_CRYPTO_ERROR               0xF2
3246 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR       0xF3
3247 #define IOERR_DRVR_MASK               0x100
3248 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3249 #define IOERR_SLI_BRESET              0x102
3250 #define IOERR_SLI_ABORTED             0x103
3251 #define IOERR_PARAM_MASK              0x1ff
3252 } PARM_ERR;
3253
3254 typedef union {
3255         struct {
3256 #ifdef __BIG_ENDIAN_BITFIELD
3257                 uint8_t Rctl;   /* R_CTL field */
3258                 uint8_t Type;   /* TYPE field */
3259                 uint8_t Dfctl;  /* DF_CTL field */
3260                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3261 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3262                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3263                 uint8_t Dfctl;  /* DF_CTL field */
3264                 uint8_t Type;   /* TYPE field */
3265                 uint8_t Rctl;   /* R_CTL field */
3266 #endif
3267
3268 #define BC      0x02            /* Broadcast Received  - Fctl */
3269 #define SI      0x04            /* Sequence Initiative */
3270 #define LA      0x08            /* Ignore Link Attention state */
3271 #define LS      0x80            /* Last Sequence */
3272         } hcsw;
3273         uint32_t reserved;
3274 } WORD5;
3275
3276 /* IOCB Command template for a generic response */
3277 typedef struct {
3278         uint32_t reserved[4];
3279         PARM_ERR perr;
3280 } GENERIC_RSP;
3281
3282 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3283 typedef struct {
3284         struct ulp_bde xrsqbde[2];
3285         uint32_t xrsqRo;        /* Starting Relative Offset */
3286         WORD5 w5;               /* Header control/status word */
3287 } XR_SEQ_FIELDS;
3288
3289 /* IOCB Command template for ELS_REQUEST */
3290 typedef struct {
3291         struct ulp_bde elsReq;
3292         struct ulp_bde elsRsp;
3293
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295         uint32_t word4Rsvd:7;
3296         uint32_t fl:1;
3297         uint32_t myID:24;
3298         uint32_t word5Rsvd:8;
3299         uint32_t remoteID:24;
3300 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3301         uint32_t myID:24;
3302         uint32_t fl:1;
3303         uint32_t word4Rsvd:7;
3304         uint32_t remoteID:24;
3305         uint32_t word5Rsvd:8;
3306 #endif
3307 } ELS_REQUEST;
3308
3309 /* IOCB Command template for RCV_ELS_REQ */
3310 typedef struct {
3311         struct ulp_bde elsReq[2];
3312         uint32_t parmRo;
3313
3314 #ifdef __BIG_ENDIAN_BITFIELD
3315         uint32_t word5Rsvd:8;
3316         uint32_t remoteID:24;
3317 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3318         uint32_t remoteID:24;
3319         uint32_t word5Rsvd:8;
3320 #endif
3321 } RCV_ELS_REQ;
3322
3323 /* IOCB Command template for ABORT / CLOSE_XRI */
3324 typedef struct {
3325         uint32_t rsvd[3];
3326         uint32_t abortType;
3327 #define ABORT_TYPE_ABTX  0x00000000
3328 #define ABORT_TYPE_ABTS  0x00000001
3329         uint32_t parm;
3330 #ifdef __BIG_ENDIAN_BITFIELD
3331         uint16_t abortContextTag; /* ulpContext from command to abort/close */
3332         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3333 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3334         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3335         uint16_t abortContextTag; /* ulpContext from command to abort/close */
3336 #endif
3337 } AC_XRI;
3338
3339 /* IOCB Command template for ABORT_MXRI64 */
3340 typedef struct {
3341         uint32_t rsvd[3];
3342         uint32_t abortType;
3343         uint32_t parm;
3344         uint32_t iotag32;
3345 } A_MXRI64;
3346
3347 /* IOCB Command template for GET_RPI */
3348 typedef struct {
3349         uint32_t rsvd[4];
3350         uint32_t parmRo;
3351 #ifdef __BIG_ENDIAN_BITFIELD
3352         uint32_t word5Rsvd:8;
3353         uint32_t remoteID:24;
3354 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3355         uint32_t remoteID:24;
3356         uint32_t word5Rsvd:8;
3357 #endif
3358 } GET_RPI;
3359
3360 /* IOCB Command template for all FCP Initiator commands */
3361 typedef struct {
3362         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
3363         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
3364         uint32_t fcpi_parm;
3365         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3366 } FCPI_FIELDS;
3367
3368 /* IOCB Command template for all FCP Target commands */
3369 typedef struct {
3370         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
3371         uint32_t fcpt_Offset;
3372         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3373 } FCPT_FIELDS;
3374
3375 /* SLI-2 IOCB structure definitions */
3376
3377 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3378 typedef struct {
3379         ULP_BDL bdl;
3380         uint32_t xrsqRo;        /* Starting Relative Offset */
3381         WORD5 w5;               /* Header control/status word */
3382 } XMT_SEQ_FIELDS64;
3383
3384 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3385 #define xmit_els_remoteID xrsqRo
3386
3387 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3388 typedef struct {
3389         struct ulp_bde64 rcvBde;
3390         uint32_t rsvd1;
3391         uint32_t xrsqRo;        /* Starting Relative Offset */
3392         WORD5 w5;               /* Header control/status word */
3393 } RCV_SEQ_FIELDS64;
3394
3395 /* IOCB Command template for ELS_REQUEST64 */
3396 typedef struct {
3397         ULP_BDL bdl;
3398 #ifdef __BIG_ENDIAN_BITFIELD
3399         uint32_t word4Rsvd:7;
3400         uint32_t fl:1;
3401         uint32_t myID:24;
3402         uint32_t word5Rsvd:8;
3403         uint32_t remoteID:24;
3404 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3405         uint32_t myID:24;
3406         uint32_t fl:1;
3407         uint32_t word4Rsvd:7;
3408         uint32_t remoteID:24;
3409         uint32_t word5Rsvd:8;
3410 #endif
3411 } ELS_REQUEST64;
3412
3413 /* IOCB Command template for GEN_REQUEST64 */
3414 typedef struct {
3415         ULP_BDL bdl;
3416         uint32_t xrsqRo;        /* Starting Relative Offset */
3417         WORD5 w5;               /* Header control/status word */
3418 } GEN_REQUEST64;
3419
3420 /* IOCB Command template for RCV_ELS_REQ64 */
3421 typedef struct {
3422         struct ulp_bde64 elsReq;
3423         uint32_t rcvd1;
3424         uint32_t parmRo;
3425
3426 #ifdef __BIG_ENDIAN_BITFIELD
3427         uint32_t word5Rsvd:8;
3428         uint32_t remoteID:24;
3429 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3430         uint32_t remoteID:24;
3431         uint32_t word5Rsvd:8;
3432 #endif
3433 } RCV_ELS_REQ64;
3434
3435 /* IOCB Command template for RCV_SEQ64 */
3436 struct rcv_seq64 {
3437         struct ulp_bde64 elsReq;
3438         uint32_t hbq_1;
3439         uint32_t parmRo;
3440 #ifdef __BIG_ENDIAN_BITFIELD
3441         uint32_t rctl:8;
3442         uint32_t type:8;
3443         uint32_t dfctl:8;
3444         uint32_t ls:1;
3445         uint32_t fs:1;
3446         uint32_t rsvd2:3;
3447         uint32_t si:1;
3448         uint32_t bc:1;
3449         uint32_t rsvd3:1;
3450 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3451         uint32_t rsvd3:1;
3452         uint32_t bc:1;
3453         uint32_t si:1;
3454         uint32_t rsvd2:3;
3455         uint32_t fs:1;
3456         uint32_t ls:1;
3457         uint32_t dfctl:8;
3458         uint32_t type:8;
3459         uint32_t rctl:8;
3460 #endif
3461 };
3462
3463 /* IOCB Command template for all 64 bit FCP Initiator commands */
3464 typedef struct {
3465         ULP_BDL bdl;
3466         uint32_t fcpi_parm;
3467         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3468 } FCPI_FIELDS64;
3469
3470 /* IOCB Command template for all 64 bit FCP Target commands */
3471 typedef struct {
3472         ULP_BDL bdl;
3473         uint32_t fcpt_Offset;
3474         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3475 } FCPT_FIELDS64;
3476
3477 /* IOCB Command template for Async Status iocb commands */
3478 typedef struct {
3479         uint32_t rsvd[4];
3480         uint32_t param;
3481 #ifdef __BIG_ENDIAN_BITFIELD
3482         uint16_t evt_code;              /* High order bits word 5 */
3483         uint16_t sub_ctxt_tag;          /* Low  order bits word 5 */
3484 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3485         uint16_t sub_ctxt_tag;          /* High order bits word 5 */
3486         uint16_t evt_code;              /* Low  order bits word 5 */
3487 #endif
3488 } ASYNCSTAT_FIELDS;
3489 #define ASYNC_TEMP_WARN         0x100
3490 #define ASYNC_TEMP_SAFE         0x101
3491 #define ASYNC_STATUS_CN         0x102
3492
3493 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3494    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3495
3496 struct rcv_sli3 {
3497 #ifdef __BIG_ENDIAN_BITFIELD
3498         uint16_t ox_id;
3499         uint16_t seq_cnt;
3500
3501         uint16_t vpi;
3502         uint16_t word9Rsvd;
3503 #else  /*  __LITTLE_ENDIAN */
3504         uint16_t seq_cnt;
3505         uint16_t ox_id;
3506
3507         uint16_t word9Rsvd;
3508         uint16_t vpi;
3509 #endif
3510         uint32_t word10Rsvd;
3511         uint32_t acc_len;      /* accumulated length */
3512         struct ulp_bde64 bde2;
3513 };
3514
3515 /* Structure used for a single HBQ entry */
3516 struct lpfc_hbq_entry {
3517         struct ulp_bde64 bde;
3518         uint32_t buffer_tag;
3519 };
3520
3521 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3522 typedef struct {
3523         struct lpfc_hbq_entry   buff;
3524         uint32_t                rsvd;
3525         uint32_t                rsvd1;
3526 } QUE_XRI64_CX_FIELDS;
3527
3528 struct que_xri64cx_ext_fields {
3529         uint32_t        iotag64_low;
3530         uint32_t        iotag64_high;
3531         uint32_t        ebde_count;
3532         uint32_t        rsvd;
3533         struct lpfc_hbq_entry   buff[5];
3534 };
3535
3536 struct sli3_bg_fields {
3537         uint32_t filler[6];     /* word 8-13 in IOCB */
3538         uint32_t bghm;          /* word 14 - BlockGuard High Water Mark */
3539 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3540 #define BGS_BIDIR_BG_PROF_MASK          0xff000000
3541 #define BGS_BIDIR_BG_PROF_SHIFT         24
3542 #define BGS_BIDIR_ERR_COND_FLAGS_MASK   0x003f0000
3543 #define BGS_BIDIR_ERR_COND_SHIFT        16
3544 #define BGS_BG_PROFILE_MASK             0x0000ff00
3545 #define BGS_BG_PROFILE_SHIFT            8
3546 #define BGS_INVALID_PROF_MASK           0x00000020
3547 #define BGS_INVALID_PROF_SHIFT          5
3548 #define BGS_UNINIT_DIF_BLOCK_MASK       0x00000010
3549 #define BGS_UNINIT_DIF_BLOCK_SHIFT      4
3550 #define BGS_HI_WATER_MARK_PRESENT_MASK  0x00000008
3551 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3552 #define BGS_REFTAG_ERR_MASK             0x00000004
3553 #define BGS_REFTAG_ERR_SHIFT            2
3554 #define BGS_APPTAG_ERR_MASK             0x00000002
3555 #define BGS_APPTAG_ERR_SHIFT            1
3556 #define BGS_GUARD_ERR_MASK              0x00000001
3557 #define BGS_GUARD_ERR_SHIFT             0
3558         uint32_t bgstat;        /* word 15 - BlockGuard Status */
3559 };
3560
3561 static inline uint32_t
3562 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3563 {
3564         return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3565                                 BGS_BIDIR_BG_PROF_SHIFT;
3566 }
3567
3568 static inline uint32_t
3569 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3570 {
3571         return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3572                                 BGS_BIDIR_ERR_COND_SHIFT;
3573 }
3574
3575 static inline uint32_t
3576 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3577 {
3578         return (bgstat & BGS_BG_PROFILE_MASK) >>
3579                                 BGS_BG_PROFILE_SHIFT;
3580 }
3581
3582 static inline uint32_t
3583 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3584 {
3585         return (bgstat & BGS_INVALID_PROF_MASK) >>
3586                                 BGS_INVALID_PROF_SHIFT;
3587 }
3588
3589 static inline uint32_t
3590 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3591 {
3592         return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3593                                 BGS_UNINIT_DIF_BLOCK_SHIFT;
3594 }
3595
3596 static inline uint32_t
3597 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3598 {
3599         return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3600                                 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3601 }
3602
3603 static inline uint32_t
3604 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3605 {
3606         return (bgstat & BGS_REFTAG_ERR_MASK) >>
3607                                 BGS_REFTAG_ERR_SHIFT;
3608 }
3609
3610 static inline uint32_t
3611 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3612 {
3613         return (bgstat & BGS_APPTAG_ERR_MASK) >>
3614                                 BGS_APPTAG_ERR_SHIFT;
3615 }
3616
3617 static inline uint32_t
3618 lpfc_bgs_get_guard_err(uint32_t bgstat)
3619 {
3620         return (bgstat & BGS_GUARD_ERR_MASK) >>
3621                                 BGS_GUARD_ERR_SHIFT;
3622 }
3623
3624 #define LPFC_EXT_DATA_BDE_COUNT 3
3625 struct fcp_irw_ext {
3626         uint32_t        io_tag64_low;
3627         uint32_t        io_tag64_high;
3628 #ifdef __BIG_ENDIAN_BITFIELD
3629         uint8_t         reserved1;
3630         uint8_t         reserved2;
3631         uint8_t         reserved3;
3632         uint8_t         ebde_count;
3633 #else  /* __LITTLE_ENDIAN */
3634         uint8_t         ebde_count;
3635         uint8_t         reserved3;
3636         uint8_t         reserved2;
3637         uint8_t         reserved1;
3638 #endif
3639         uint32_t        reserved4;
3640         struct ulp_bde64 rbde;          /* response bde */
3641         struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3642         uint8_t icd[32];                /* immediate command data (32 bytes) */
3643 };
3644
3645 typedef struct _IOCB {  /* IOCB structure */
3646         union {
3647                 GENERIC_RSP grsp;       /* Generic response */
3648                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
3649                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3650                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
3651                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
3652                 A_MXRI64 amxri; /* abort multiple xri command overlay */
3653                 GET_RPI getrpi; /* GET_RPI template */
3654                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
3655                 FCPT_FIELDS fcpt;       /* FCP target template */
3656
3657                 /* SLI-2 structures */
3658
3659                 struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
3660                                               * bde_64s */
3661                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3662                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3663                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3664                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
3665                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
3666                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
3667                 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3668                 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3669                 struct rcv_seq64 rcvseq64;      /* RCV_SEQ64 and RCV_CONT64 */
3670                 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3671                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
3672         } un;
3673         union {
3674                 struct {
3675 #ifdef __BIG_ENDIAN_BITFIELD
3676                         uint16_t ulpContext;    /* High order bits word 6 */
3677                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
3678 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3679                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
3680                         uint16_t ulpContext;    /* High order bits word 6 */
3681 #endif
3682                 } t1;
3683                 struct {
3684 #ifdef __BIG_ENDIAN_BITFIELD
3685                         uint16_t ulpContext;    /* High order bits word 6 */
3686                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
3687                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
3688 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3689                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
3690                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
3691                         uint16_t ulpContext;    /* High order bits word 6 */
3692 #endif
3693                 } t2;
3694         } un1;
3695 #define ulpContext un1.t1.ulpContext
3696 #define ulpIoTag   un1.t1.ulpIoTag
3697 #define ulpIoTag0  un1.t2.ulpIoTag0
3698
3699 #ifdef __BIG_ENDIAN_BITFIELD
3700         uint32_t ulpTimeout:8;
3701         uint32_t ulpXS:1;
3702         uint32_t ulpFCP2Rcvy:1;
3703         uint32_t ulpPU:2;
3704         uint32_t ulpIr:1;
3705         uint32_t ulpClass:3;
3706         uint32_t ulpCommand:8;
3707         uint32_t ulpStatus:4;
3708         uint32_t ulpBdeCount:2;
3709         uint32_t ulpLe:1;
3710         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3711 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3712         uint32_t ulpOwner:1;    /* Low order bit word 7 */
3713         uint32_t ulpLe:1;
3714         uint32_t ulpBdeCount:2;
3715         uint32_t ulpStatus:4;
3716         uint32_t ulpCommand:8;
3717         uint32_t ulpClass:3;
3718         uint32_t ulpIr:1;
3719         uint32_t ulpPU:2;
3720         uint32_t ulpFCP2Rcvy:1;
3721         uint32_t ulpXS:1;
3722         uint32_t ulpTimeout:8;
3723 #endif
3724
3725         union {
3726                 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3727
3728                 /* words 8-31 used for que_xri_cx iocb */
3729                 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3730                 struct fcp_irw_ext fcp_ext;
3731                 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3732
3733                 /* words 8-15 for BlockGuard */
3734                 struct sli3_bg_fields sli3_bg;
3735         } unsli3;
3736
3737 #define ulpCt_h ulpXS
3738 #define ulpCt_l ulpFCP2Rcvy
3739
3740 #define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3741 #define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
3742 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
3743 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
3744 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
3745 #define PARM_NPIV_DID      3
3746 #define CLASS1             0    /* Class 1 */
3747 #define CLASS2             1    /* Class 2 */
3748 #define CLASS3             2    /* Class 3 */
3749 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
3750
3751 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
3752 #define IOSTAT_FCP_RSP_ERROR   0x1
3753 #define IOSTAT_REMOTE_STOP     0x2
3754 #define IOSTAT_LOCAL_REJECT    0x3
3755 #define IOSTAT_NPORT_RJT       0x4
3756 #define IOSTAT_FABRIC_RJT      0x5
3757 #define IOSTAT_NPORT_BSY       0x6
3758 #define IOSTAT_FABRIC_BSY      0x7
3759 #define IOSTAT_INTERMED_RSP    0x8
3760 #define IOSTAT_LS_RJT          0x9
3761 #define IOSTAT_BA_RJT          0xA
3762 #define IOSTAT_RSVD1           0xB
3763 #define IOSTAT_RSVD2           0xC
3764 #define IOSTAT_RSVD3           0xD
3765 #define IOSTAT_RSVD4           0xE
3766 #define IOSTAT_NEED_BUFFER     0xF
3767 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
3768 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
3769 #define IOSTAT_CNT             0x11
3770
3771 } IOCB_t;
3772
3773
3774 #define SLI1_SLIM_SIZE   (4 * 1024)
3775
3776 /* Up to 498 IOCBs will fit into 16k
3777  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3778  */
3779 #define SLI2_SLIM_SIZE   (64 * 1024)
3780
3781 /* Maximum IOCBs that will fit in SLI2 slim */
3782 #define MAX_SLI2_IOCB    498
3783 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3784                             (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3785                             sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3786
3787 /* HBQ entries are 4 words each = 4k */
3788 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
3789                              lpfc_sli_hbq_count())
3790
3791 struct lpfc_sli2_slim {
3792         MAILBOX_t mbx;
3793         uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
3794         PCB_t pcb;
3795         IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3796 };
3797
3798 /*
3799  * This function checks PCI device to allow special handling for LC HBAs.
3800  *
3801  * Parameters:
3802  * device : struct pci_dev 's device field
3803  *
3804  * return 1 => TRUE
3805  *        0 => FALSE
3806  */
3807 static inline int
3808 lpfc_is_LC_HBA(unsigned short device)
3809 {
3810         if ((device == PCI_DEVICE_ID_TFLY) ||
3811             (device == PCI_DEVICE_ID_PFLY) ||
3812             (device == PCI_DEVICE_ID_LP101) ||
3813             (device == PCI_DEVICE_ID_BMID) ||
3814             (device == PCI_DEVICE_ID_BSMB) ||
3815             (device == PCI_DEVICE_ID_ZMID) ||
3816             (device == PCI_DEVICE_ID_ZSMB) ||
3817             (device == PCI_DEVICE_ID_SAT_MID) ||
3818             (device == PCI_DEVICE_ID_SAT_SMB) ||
3819             (device == PCI_DEVICE_ID_RFLY))
3820                 return 1;
3821         else
3822                 return 0;
3823 }
3824
3825 /*
3826  * Determine if an IOCB failed because of a link event or firmware reset.
3827  */
3828
3829 static inline int
3830 lpfc_error_lost_link(IOCB_t *iocbp)
3831 {
3832         return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3833                 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3834                  iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3835                  iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3836 }
3837
3838 #define MENLO_TRANSPORT_TYPE 0xfe
3839 #define MENLO_CONTEXT 0
3840 #define MENLO_PU 3
3841 #define MENLO_TIMEOUT 30
3842 #define SETVAR_MLOMNT 0x103107
3843 #define SETVAR_MLORST 0x103007
3844
3845 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */