drivers/scsi/mpt2sas/mpi/mpi2.h

   1 /*
   2  *  Copyright (c) 2000-2013 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2.h
   6  *          Title:  MPI Message independent structures and definitions
   7  *                  including System Interface Register Set and
   8  *                  scatter/gather formats.
   9  *  Creation Date:  June 21, 2006
  10  *
  11  *  mpi2.h Version:  02.00.28
  12  *
  13  *  Version History
  14  *  ---------------
  15  *
  16  *  Date      Version   Description
  17  *  --------  --------  ------------------------------------------------------
  18  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  19  *  06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
  20  *  06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
  21  *  08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
  22  *                      Moved ReplyPostHostIndex register to offset 0x6C of the
  23  *                      MPI2_SYSTEM_INTERFACE_REGS and modified the define for
  24  *                      MPI2_REPLY_POST_HOST_INDEX_OFFSET.
  25  *                      Added union of request descriptors.
  26  *                      Added union of reply descriptors.
  27  *  10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
  28  *                      Added define for MPI2_VERSION_02_00.
  29  *                      Fixed the size of the FunctionDependent5 field in the
  30  *                      MPI2_DEFAULT_REPLY structure.
  31  *  12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
  32  *                      Removed the MPI-defined Fault Codes and extended the
  33  *                      product specific codes up to 0xEFFF.
  34  *                      Added a sixth key value for the WriteSequence register
  35  *                      and changed the flush value to 0x0.
  36  *                      Added message function codes for Diagnostic Buffer Post
  37  *                      and Diagnsotic Release.
  38  *                      New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
  39  *                      Moved MPI2_VERSION_UNION from mpi2_ioc.h.
  40  *  02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
  41  *  03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
  42  *  05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
  43  *                      Added #defines for marking a reply descriptor as unused.
  44  *  06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
  45  *  10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
  46  *                      Moved LUN field defines from mpi2_init.h.
  47  *  01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
  48  *  05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
  49  *                      In all request and reply descriptors, replaced VF_ID
  50  *                      field with MSIxIndex field.
  51  *                      Removed DevHandle field from
  52  *                      MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
  53  *                      bytes reserved.
  54  *                      Added RAID Accelerator functionality.
  55  *  07-30-09  02.00.13  Bumped MPI2_HEADER_VERSION_UNIT.
  56  *  10-28-09  02.00.14  Bumped MPI2_HEADER_VERSION_UNIT.
  57  *                      Added MSI-x index mask and shift for Reply Post Host
  58  *                      Index register.
  59  *                      Added function code for Host Based Discovery Action.
  60  *  02-10-10  02.00.15  Bumped MPI2_HEADER_VERSION_UNIT.
  61  *                      Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
  62  *                      Added defines for product-specific range of message
  63  *                      function codes, 0xF0 to 0xFF.
  64  *  05-12-10  02.00.16  Bumped MPI2_HEADER_VERSION_UNIT.
  65  *                      Added alternative defines for the SGE Direction bit.
  66  *  08-11-10  02.00.17  Bumped MPI2_HEADER_VERSION_UNIT.
  67  *  11-10-10  02.00.18  Bumped MPI2_HEADER_VERSION_UNIT.
  68  *                      Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
  69  *  02-23-11  02.00.19  Bumped MPI2_HEADER_VERSION_UNIT.
  70  *                      Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
  71  *  03-09-11  02.00.20  Bumped MPI2_HEADER_VERSION_UNIT.
  72  *  05-25-11  02.00.21  Bumped MPI2_HEADER_VERSION_UNIT.
  73  *  08-24-11  02.00.22  Bumped MPI2_HEADER_VERSION_UNIT.
  74  *  11-18-11  02.00.23  Bumped MPI2_HEADER_VERSION_UNIT.
  75  *  02-06-12  02.00.24  Bumped MPI2_HEADER_VERSION_UNIT.
  76  *  03-29-12  02.00.25  Bumped MPI2_HEADER_VERSION_UNIT.
  77  *                      Added Hard Reset delay timings.
  78  *  07-10-12  02.00.26  Bumped MPI2_HEADER_VERSION_UNIT.
  79  *  07-26-12  02.00.27  Bumped MPI2_HEADER_VERSION_UNIT.
  80  *  11-27-12  02.00.28  Bumped MPI2_HEADER_VERSION_UNIT.
  81  *  --------------------------------------------------------------------------
  82  */
  83
  84 #ifndef MPI2_H
  85 #define MPI2_H
  86
  87
  88 /*****************************************************************************
  89 *
  90 *        MPI Version Definitions
  91 *
  92 *****************************************************************************/
  93
  94 #define MPI2_VERSION_MAJOR                  (0x02)
  95 #define MPI2_VERSION_MINOR                  (0x00)
  96 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
  97 #define MPI2_VERSION_MAJOR_SHIFT            (8)
  98 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
  99 #define MPI2_VERSION_MINOR_SHIFT            (0)
 100 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
 101                                       MPI2_VERSION_MINOR)
 102
 103 #define MPI2_VERSION_02_00                  (0x0200)
 104
 105 /* versioning for this MPI header set */
 106 #define MPI2_HEADER_VERSION_UNIT            (0x1C)
 107 #define MPI2_HEADER_VERSION_DEV             (0x00)
 108 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 109 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 110 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 111 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 112 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
 113
 114
 115 /*****************************************************************************
 116 *
 117 *        IOC State Definitions
 118 *
 119 *****************************************************************************/
 120
 121 #define MPI2_IOC_STATE_RESET               (0x00000000)
 122 #define MPI2_IOC_STATE_READY               (0x10000000)
 123 #define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
 124 #define MPI2_IOC_STATE_FAULT               (0x40000000)
 125
 126 #define MPI2_IOC_STATE_MASK                (0xF0000000)
 127 #define MPI2_IOC_STATE_SHIFT               (28)
 128
 129 /* Fault state range for prodcut specific codes */
 130 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
 131 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
 132
 133
 134 /*****************************************************************************
 135 *
 136 *        System Interface Register Definitions
 137 *
 138 *****************************************************************************/
 139
 140 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
 141 {
 142     U32         Doorbell;                   /* 0x00 */
 143     U32         WriteSequence;              /* 0x04 */
 144     U32         HostDiagnostic;             /* 0x08 */
 145     U32         Reserved1;                  /* 0x0C */
 146     U32         DiagRWData;                 /* 0x10 */
 147     U32         DiagRWAddressLow;           /* 0x14 */
 148     U32         DiagRWAddressHigh;          /* 0x18 */
 149     U32         Reserved2[5];               /* 0x1C */
 150     U32         HostInterruptStatus;        /* 0x30 */
 151     U32         HostInterruptMask;          /* 0x34 */
 152     U32         DCRData;                    /* 0x38 */
 153     U32         DCRAddress;                 /* 0x3C */
 154     U32         Reserved3[2];               /* 0x40 */
 155     U32         ReplyFreeHostIndex;         /* 0x48 */
 156     U32         Reserved4[8];               /* 0x4C */
 157     U32         ReplyPostHostIndex;         /* 0x6C */
 158     U32         Reserved5;                  /* 0x70 */
 159     U32         HCBSize;                    /* 0x74 */
 160     U32         HCBAddressLow;              /* 0x78 */
 161     U32         HCBAddressHigh;             /* 0x7C */
 162     U32         Reserved6[16];              /* 0x80 */
 163     U32         RequestDescriptorPostLow;   /* 0xC0 */
 164     U32         RequestDescriptorPostHigh;  /* 0xC4 */
 165     U32         Reserved7[14];              /* 0xC8 */
 166 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
 167   Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
 168
 169 /*
 170  * Defines for working with the Doorbell register.
 171  */
 172 #define MPI2_DOORBELL_OFFSET                    (0x00000000)
 173
 174 /* IOC --> System values */
 175 #define MPI2_DOORBELL_USED                      (0x08000000)
 176 #define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
 177 #define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
 178 #define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
 179 #define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
 180
 181 /* System --> IOC values */
 182 #define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
 183 #define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
 184 #define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
 185 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
 186
 187
 188 /*
 189  * Defines for the WriteSequence register
 190  */
 191 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 192 #define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
 193 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 194 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 195 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 196 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 197 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 198 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 199 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 200
 201 /*
 202  * Defines for the HostDiagnostic register
 203  */
 204 #define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
 205
 206 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
 207 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
 208 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
 209
 210 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
 211 #define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
 212 #define MPI2_DIAG_HCB_MODE                      (0x00000100)
 213 #define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
 214 #define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
 215 #define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
 216 #define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
 217 #define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
 218 #define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
 219
 220 /*
 221  * Offsets for DiagRWData and address
 222  */
 223 #define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
 224 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
 225 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
 226
 227 /*
 228  * Defines for the HostInterruptStatus register
 229  */
 230 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
 231 #define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
 232 #define MPI2_HIS_IOP_DOORBELL_STATUS            MPI2_HIS_SYS2IOC_DB_STATUS
 233 #define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
 234 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
 235 #define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
 236 #define MPI2_HIS_DOORBELL_INTERRUPT             MPI2_HIS_IOC2SYS_DB_STATUS
 237
 238 /*
 239  * Defines for the HostInterruptMask register
 240  */
 241 #define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
 242 #define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
 243 #define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
 244 #define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
 245 #define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
 246 #define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
 247
 248 /*
 249  * Offsets for DCRData and address
 250  */
 251 #define MPI2_DCR_DATA_OFFSET                    (0x00000038)
 252 #define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
 253
 254 /*
 255  * Offset for the Reply Free Queue
 256  */
 257 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
 258
 259 /*
 260  * Defines for the Reply Descriptor Post Queue
 261  */
 262 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
 263 #define MPI2_REPLY_POST_HOST_INDEX_MASK         (0x00FFFFFF)
 264 #define MPI2_RPHI_MSIX_INDEX_MASK               (0xFF000000)
 265 #define MPI2_RPHI_MSIX_INDEX_SHIFT              (24)
 266
 267 /*
 268  * Defines for the HCBSize and address
 269  */
 270 #define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
 271 #define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
 272 #define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
 273
 274 #define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
 275 #define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
 276
 277 /*
 278  * Offsets for the Request Queue
 279  */
 280 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
 281 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
 282
 283
 284 /* Hard Reset delay timings */
 285 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC     (50000)
 286 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC    (255000)
 287 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC    (256000)
 288
 289 /*****************************************************************************
 290 *
 291 *        Message Descriptors
 292 *
 293 *****************************************************************************/
 294
 295 /* Request Descriptors */
 296
 297 /* Default Request Descriptor */
 298 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
 299 {
 300     U8              RequestFlags;               /* 0x00 */
 301     U8              MSIxIndex;                  /* 0x01 */
 302     U16             SMID;                       /* 0x02 */
 303     U16             LMID;                       /* 0x04 */
 304     U16             DescriptorTypeDependent;    /* 0x06 */
 305 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 306   MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 307   Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 308
 309 /* defines for the RequestFlags field */
 310 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 311 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 312 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 313 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 314 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 315 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 316
 317 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 318
 319
 320 /* High Priority Request Descriptor */
 321 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
 322 {
 323     U8              RequestFlags;               /* 0x00 */
 324     U8              MSIxIndex;                  /* 0x01 */
 325     U16             SMID;                       /* 0x02 */
 326     U16             LMID;                       /* 0x04 */
 327     U16             Reserved1;                  /* 0x06 */
 328 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 329   MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 330   Mpi2HighPriorityRequestDescriptor_t,
 331   MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 332
 333
 334 /* SCSI IO Request Descriptor */
 335 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 336 {
 337     U8              RequestFlags;               /* 0x00 */
 338     U8              MSIxIndex;                  /* 0x01 */
 339     U16             SMID;                       /* 0x02 */
 340     U16             LMID;                       /* 0x04 */
 341     U16             DevHandle;                  /* 0x06 */
 342 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 343   MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 344   Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 345
 346
 347 /* SCSI Target Request Descriptor */
 348 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
 349 {
 350     U8              RequestFlags;               /* 0x00 */
 351     U8              MSIxIndex;                  /* 0x01 */
 352     U16             SMID;                       /* 0x02 */
 353     U16             LMID;                       /* 0x04 */
 354     U16             IoIndex;                    /* 0x06 */
 355 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 356   MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 357   Mpi2SCSITargetRequestDescriptor_t,
 358   MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 359
 360
 361 /* RAID Accelerator Request Descriptor */
 362 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 363     U8              RequestFlags;               /* 0x00 */
 364     U8              MSIxIndex;                  /* 0x01 */
 365     U16             SMID;                       /* 0x02 */
 366     U16             LMID;                       /* 0x04 */
 367     U16             Reserved;                   /* 0x06 */
 368 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 369   MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 370   Mpi2RAIDAcceleratorRequestDescriptor_t,
 371   MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 372
 373
 374 /* union of Request Descriptors */
 375 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
 376 {
 377     MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 378     MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 379     MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 380     MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 381     MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 382     U64                                         Words;
 383 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
 384   Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
 385
 386
 387 /* Reply Descriptors */
 388
 389 /* Default Reply Descriptor */
 390 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
 391 {
 392     U8              ReplyFlags;                 /* 0x00 */
 393     U8              MSIxIndex;                  /* 0x01 */
 394     U16             DescriptorTypeDependent1;   /* 0x02 */
 395     U32             DescriptorTypeDependent2;   /* 0x04 */
 396 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 397   Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 398
 399 /* defines for the ReplyFlags field */
 400 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 401 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 402 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 403 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 404 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 405 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 406 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 407
 408 /* values for marking a reply descriptor as unused */
 409 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 410 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 411
 412 /* Address Reply Descriptor */
 413 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
 414 {
 415     U8              ReplyFlags;                 /* 0x00 */
 416     U8              MSIxIndex;                  /* 0x01 */
 417     U16             SMID;                       /* 0x02 */
 418     U32             ReplyFrameAddress;          /* 0x04 */
 419 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 420   Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 421
 422 #define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
 423
 424
 425 /* SCSI IO Success Reply Descriptor */
 426 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
 427 {
 428     U8              ReplyFlags;                 /* 0x00 */
 429     U8              MSIxIndex;                  /* 0x01 */
 430     U16             SMID;                       /* 0x02 */
 431     U16             TaskTag;                    /* 0x04 */
 432     U16             Reserved1;                  /* 0x06 */
 433 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 434   MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 435   Mpi2SCSIIOSuccessReplyDescriptor_t,
 436   MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 437
 438
 439 /* TargetAssist Success Reply Descriptor */
 440 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
 441 {
 442     U8              ReplyFlags;                 /* 0x00 */
 443     U8              MSIxIndex;                  /* 0x01 */
 444     U16             SMID;                       /* 0x02 */
 445     U8              SequenceNumber;             /* 0x04 */
 446     U8              Reserved1;                  /* 0x05 */
 447     U16             IoIndex;                    /* 0x06 */
 448 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 449   MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 450   Mpi2TargetAssistSuccessReplyDescriptor_t,
 451   MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 452
 453
 454 /* Target Command Buffer Reply Descriptor */
 455 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
 456 {
 457     U8              ReplyFlags;                 /* 0x00 */
 458     U8              MSIxIndex;                  /* 0x01 */
 459     U8              VP_ID;                      /* 0x02 */
 460     U8              Flags;                      /* 0x03 */
 461     U16             InitiatorDevHandle;         /* 0x04 */
 462     U16             IoIndex;                    /* 0x06 */
 463 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 464   MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 465   Mpi2TargetCommandBufferReplyDescriptor_t,
 466   MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 467
 468 /* defines for Flags field */
 469 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
 470
 471
 472 /* RAID Accelerator Success Reply Descriptor */
 473 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 474     U8              ReplyFlags;                 /* 0x00 */
 475     U8              MSIxIndex;                  /* 0x01 */
 476     U16             SMID;                       /* 0x02 */
 477     U32             Reserved;                   /* 0x04 */
 478 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 479   MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 480   Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
 481   MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 482
 483
 484 /* union of Reply Descriptors */
 485 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
 486 {
 487     MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 488     MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 489     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 490     MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR      TargetAssistSuccess;
 491     MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR     TargetCommandBuffer;
 492     MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR  RAIDAcceleratorSuccess;
 493     U64                                             Words;
 494 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 495 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 496
 497
 498
 499 /*****************************************************************************
 500 *
 501 *        Message Functions
 502 *
 503 *****************************************************************************/
 504
 505 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 506 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 507 #define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 508 #define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 509 #define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 510 #define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 511 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 512 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 513 #define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 514 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 515 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 516 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 517 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 518 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 519 #define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 520 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 521 #define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 522 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 523 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 524 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 525 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 526 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 527 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 528 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 529 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 530 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator*/
 531 /* Host Based Discovery Action */
 532 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F)
 533 /* Power Management Control */
 534 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30)
 535 /* Send Host Message */
 536 #define MPI2_FUNCTION_SEND_HOST_MESSAGE             (0x31)
 537 /* beginning of product-specific range */
 538 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0)
 539 /* end of product-specific range */
 540 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF)
 541
 542
 543
 544
 545 /* Doorbell functions */
 546 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 547 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 548
 549
 550 /*****************************************************************************
 551 *
 552 *        IOC Status Values
 553 *
 554 *****************************************************************************/
 555
 556 /* mask for IOCStatus status value */
 557 #define MPI2_IOCSTATUS_MASK                     (0x7FFF)
 558
 559 /****************************************************************************
 560 *  Common IOCStatus values for all replies
 561 ****************************************************************************/
 562
 563 #define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
 564 #define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 565 #define MPI2_IOCSTATUS_BUSY                         (0x0002)
 566 #define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
 567 #define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 568 #define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
 569 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 570 #define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
 571 #define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
 572 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
 573
 574 /****************************************************************************
 575 *  Config IOCStatus values
 576 ****************************************************************************/
 577
 578 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 579 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 580 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 581 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 582 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 583 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 584
 585 /****************************************************************************
 586 *  SCSI IO Reply
 587 ****************************************************************************/
 588
 589 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 590 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 591 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 592 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 593 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 594 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 595 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 596 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 597 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 598 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
 599 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
 600 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
 601
 602 /****************************************************************************
 603 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
 604 ****************************************************************************/
 605
 606 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
 607 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
 608 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
 609
 610 /****************************************************************************
 611 *  SCSI Target values
 612 ****************************************************************************/
 613
 614 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 615 #define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
 616 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 617 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 618 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
 619 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
 620 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
 621 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
 622 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 623 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 624
 625 /****************************************************************************
 626 *  Serial Attached SCSI values
 627 ****************************************************************************/
 628
 629 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 630 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 631
 632 /****************************************************************************
 633 *  Diagnostic Buffer Post / Diagnostic Release values
 634 ****************************************************************************/
 635
 636 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
 637
 638 /****************************************************************************
 639 *  RAID Accelerator values
 640 ****************************************************************************/
 641
 642 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
 643
 644 /****************************************************************************
 645 *  IOCStatus flag to indicate that log info is available
 646 ****************************************************************************/
 647
 648 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
 649
 650 /****************************************************************************
 651 *  IOCLogInfo Types
 652 ****************************************************************************/
 653
 654 #define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
 655 #define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
 656 #define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
 657 #define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
 658 #define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
 659 #define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
 660 #define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
 661 #define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
 662
 663
 664 /*****************************************************************************
 665 *
 666 *        Standard Message Structures
 667 *
 668 *****************************************************************************/
 669
 670 /****************************************************************************
 671 * Request Message Header for all request messages
 672 ****************************************************************************/
 673
 674 typedef struct _MPI2_REQUEST_HEADER
 675 {
 676     U16             FunctionDependent1;         /* 0x00 */
 677     U8              ChainOffset;                /* 0x02 */
 678     U8              Function;                   /* 0x03 */
 679     U16             FunctionDependent2;         /* 0x04 */
 680     U8              FunctionDependent3;         /* 0x06 */
 681     U8              MsgFlags;                   /* 0x07 */
 682     U8              VP_ID;                      /* 0x08 */
 683     U8              VF_ID;                      /* 0x09 */
 684     U16             Reserved1;                  /* 0x0A */
 685 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
 686   MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
 687
 688
 689 /****************************************************************************
 690 *  Default Reply
 691 ****************************************************************************/
 692
 693 typedef struct _MPI2_DEFAULT_REPLY
 694 {
 695     U16             FunctionDependent1;         /* 0x00 */
 696     U8              MsgLength;                  /* 0x02 */
 697     U8              Function;                   /* 0x03 */
 698     U16             FunctionDependent2;         /* 0x04 */
 699     U8              FunctionDependent3;         /* 0x06 */
 700     U8              MsgFlags;                   /* 0x07 */
 701     U8              VP_ID;                      /* 0x08 */
 702     U8              VF_ID;                      /* 0x09 */
 703     U16             Reserved1;                  /* 0x0A */
 704     U16             FunctionDependent5;         /* 0x0C */
 705     U16             IOCStatus;                  /* 0x0E */
 706     U32             IOCLogInfo;                 /* 0x10 */
 707 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
 708   MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
 709
 710
 711 /* common version structure/union used in messages and configuration pages */
 712
 713 typedef struct _MPI2_VERSION_STRUCT
 714 {
 715     U8                      Dev;                        /* 0x00 */
 716     U8                      Unit;                       /* 0x01 */
 717     U8                      Minor;                      /* 0x02 */
 718     U8                      Major;                      /* 0x03 */
 719 } MPI2_VERSION_STRUCT;
 720
 721 typedef union _MPI2_VERSION_UNION
 722 {
 723     MPI2_VERSION_STRUCT     Struct;
 724     U32                     Word;
 725 } MPI2_VERSION_UNION;
 726
 727
 728 /* LUN field defines, common to many structures */
 729 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
 730 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
 731 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
 732 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
 733 #define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
 734 #define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
 735
 736
 737 /*****************************************************************************
 738 *
 739 *        Fusion-MPT MPI Scatter Gather Elements
 740 *
 741 *****************************************************************************/
 742
 743 /****************************************************************************
 744 *  MPI Simple Element structures
 745 ****************************************************************************/
 746
 747 typedef struct _MPI2_SGE_SIMPLE32
 748 {
 749     U32                     FlagsLength;
 750     U32                     Address;
 751 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
 752   Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
 753
 754 typedef struct _MPI2_SGE_SIMPLE64
 755 {
 756     U32                     FlagsLength;
 757     U64                     Address;
 758 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
 759   Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
 760
 761 typedef struct _MPI2_SGE_SIMPLE_UNION
 762 {
 763     U32                     FlagsLength;
 764     union
 765     {
 766         U32                 Address32;
 767         U64                 Address64;
 768     } u;
 769 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 770   Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 771
 772
 773 /****************************************************************************
 774 *  MPI Chain Element structures
 775 ****************************************************************************/
 776
 777 typedef struct _MPI2_SGE_CHAIN32
 778 {
 779     U16                     Length;
 780     U8                      NextChainOffset;
 781     U8                      Flags;
 782     U32                     Address;
 783 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
 784   Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
 785
 786 typedef struct _MPI2_SGE_CHAIN64
 787 {
 788     U16                     Length;
 789     U8                      NextChainOffset;
 790     U8                      Flags;
 791     U64                     Address;
 792 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
 793   Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
 794
 795 typedef struct _MPI2_SGE_CHAIN_UNION
 796 {
 797     U16                     Length;
 798     U8                      NextChainOffset;
 799     U8                      Flags;
 800     union
 801     {
 802         U32                 Address32;
 803         U64                 Address64;
 804     } u;
 805 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 806   Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 807
 808
 809 /****************************************************************************
 810 *  MPI Transaction Context Element structures
 811 ****************************************************************************/
 812
 813 typedef struct _MPI2_SGE_TRANSACTION32
 814 {
 815     U8                      Reserved;
 816     U8                      ContextSize;
 817     U8                      DetailsLength;
 818     U8                      Flags;
 819     U32                     TransactionContext[1];
 820     U32                     TransactionDetails[1];
 821 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
 822   Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
 823
 824 typedef struct _MPI2_SGE_TRANSACTION64
 825 {
 826     U8                      Reserved;
 827     U8                      ContextSize;
 828     U8                      DetailsLength;
 829     U8                      Flags;
 830     U32                     TransactionContext[2];
 831     U32                     TransactionDetails[1];
 832 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
 833   Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
 834
 835 typedef struct _MPI2_SGE_TRANSACTION96
 836 {
 837     U8                      Reserved;
 838     U8                      ContextSize;
 839     U8                      DetailsLength;
 840     U8                      Flags;
 841     U32                     TransactionContext[3];
 842     U32                     TransactionDetails[1];
 843 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
 844   Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
 845
 846 typedef struct _MPI2_SGE_TRANSACTION128
 847 {
 848     U8                      Reserved;
 849     U8                      ContextSize;
 850     U8                      DetailsLength;
 851     U8                      Flags;
 852     U32                     TransactionContext[4];
 853     U32                     TransactionDetails[1];
 854 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
 855   Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
 856
 857 typedef struct _MPI2_SGE_TRANSACTION_UNION
 858 {
 859     U8                      Reserved;
 860     U8                      ContextSize;
 861     U8                      DetailsLength;
 862     U8                      Flags;
 863     union
 864     {
 865         U32                 TransactionContext32[1];
 866         U32                 TransactionContext64[2];
 867         U32                 TransactionContext96[3];
 868         U32                 TransactionContext128[4];
 869     } u;
 870     U32                     TransactionDetails[1];
 871 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
 872   Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
 873
 874
 875 /****************************************************************************
 876 *  MPI SGE union for IO SGL's
 877 ****************************************************************************/
 878
 879 typedef struct _MPI2_MPI_SGE_IO_UNION
 880 {
 881     union
 882     {
 883         MPI2_SGE_SIMPLE_UNION   Simple;
 884         MPI2_SGE_CHAIN_UNION    Chain;
 885     } u;
 886 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
 887   Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
 888
 889
 890 /****************************************************************************
 891 *  MPI SGE union for SGL's with Simple and Transaction elements
 892 ****************************************************************************/
 893
 894 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
 895 {
 896     union
 897     {
 898         MPI2_SGE_SIMPLE_UNION       Simple;
 899         MPI2_SGE_TRANSACTION_UNION  Transaction;
 900     } u;
 901 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
 902   Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
 903
 904
 905 /****************************************************************************
 906 *  All MPI SGE types union
 907 ****************************************************************************/
 908
 909 typedef struct _MPI2_MPI_SGE_UNION
 910 {
 911     union
 912     {
 913         MPI2_SGE_SIMPLE_UNION       Simple;
 914         MPI2_SGE_CHAIN_UNION        Chain;
 915         MPI2_SGE_TRANSACTION_UNION  Transaction;
 916     } u;
 917 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
 918   Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
 919
 920
 921 /****************************************************************************
 922 *  MPI SGE field definition and masks
 923 ****************************************************************************/
 924
 925 /* Flags field bit definitions */
 926
 927 #define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
 928 #define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
 929 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
 930 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
 931 #define MPI2_SGE_FLAGS_DIRECTION                (0x04)
 932 #define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
 933 #define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
 934
 935 #define MPI2_SGE_FLAGS_SHIFT                    (24)
 936
 937 #define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
 938 #define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
 939
 940 /* Element Type */
 941
 942 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
 943 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
 944 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
 945 #define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
 946
 947 /* Address location */
 948
 949 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
 950
 951 /* Direction */
 952
 953 #define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
 954 #define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
 955
 956 #define MPI2_SGE_FLAGS_DEST                     (MPI2_SGE_FLAGS_IOC_TO_HOST)
 957 #define MPI2_SGE_FLAGS_SOURCE                   (MPI2_SGE_FLAGS_HOST_TO_IOC)
 958
 959 /* Address Size */
 960
 961 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 962 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 963
 964 /* Context Size */
 965
 966 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
 967 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
 968 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
 969 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
 970
 971 #define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
 972 #define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
 973
 974 /****************************************************************************
 975 *  MPI SGE operation Macros
 976 ****************************************************************************/
 977
 978 /* SIMPLE FlagsLength manipulations... */
 979 #define MPI2_SGE_SET_FLAGS(f)          ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
 980 #define MPI2_SGE_GET_FLAGS(f)          (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
 981 #define MPI2_SGE_LENGTH(f)             ((f) & MPI2_SGE_LENGTH_MASK)
 982 #define MPI2_SGE_CHAIN_LENGTH(f)       ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
 983
 984 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
 985
 986 #define MPI2_pSGE_GET_FLAGS(psg)            MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
 987 #define MPI2_pSGE_GET_LENGTH(psg)           MPI2_SGE_LENGTH((psg)->FlagsLength)
 988 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
 989
 990 /* CAUTION - The following are READ-MODIFY-WRITE! */
 991 #define MPI2_pSGE_SET_FLAGS(psg,f)      (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
 992 #define MPI2_pSGE_SET_LENGTH(psg,l)     (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
 993
 994 #define MPI2_GET_CHAIN_OFFSET(x)    ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
 995
 996
 997 /*****************************************************************************
 998 *
 999 *        Fusion-MPT IEEE Scatter Gather Elements
1000 *
1001 *****************************************************************************/
1002
1003 /****************************************************************************
1004 *  IEEE Simple Element structures
1005 ****************************************************************************/
1006
1007 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1008 {
1009     U32                     Address;
1010     U32                     FlagsLength;
1011 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1012   Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1013
1014 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1015 {
1016     U64                     Address;
1017     U32                     Length;
1018     U16                     Reserved1;
1019     U8                      Reserved2;
1020     U8                      Flags;
1021 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1022   Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1023
1024 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1025 {
1026     MPI2_IEEE_SGE_SIMPLE32  Simple32;
1027     MPI2_IEEE_SGE_SIMPLE64  Simple64;
1028 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1029   Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1030
1031
1032 /****************************************************************************
1033 *  IEEE Chain Element structures
1034 ****************************************************************************/
1035
1036 typedef MPI2_IEEE_SGE_SIMPLE32  MPI2_IEEE_SGE_CHAIN32;
1037
1038 typedef MPI2_IEEE_SGE_SIMPLE64  MPI2_IEEE_SGE_CHAIN64;
1039
1040 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1041 {
1042     MPI2_IEEE_SGE_CHAIN32   Chain32;
1043     MPI2_IEEE_SGE_CHAIN64   Chain64;
1044 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1045   Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1046
1047
1048 /****************************************************************************
1049 *  All IEEE SGE types union
1050 ****************************************************************************/
1051
1052 typedef struct _MPI2_IEEE_SGE_UNION
1053 {
1054     union
1055     {
1056         MPI2_IEEE_SGE_SIMPLE_UNION  Simple;
1057         MPI2_IEEE_SGE_CHAIN_UNION   Chain;
1058     } u;
1059 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1060   Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1061
1062
1063 /****************************************************************************
1064 *  IEEE SGE field definitions and masks
1065 ****************************************************************************/
1066
1067 /* Flags field bit definitions */
1068
1069 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1070
1071 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1072
1073 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1074
1075 /* Element Type */
1076
1077 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1078 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1079
1080 /* Data Location Address Space */
1081
1082 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1083 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1084                                                 /* IEEE Simple Element only */
1085 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1086                                                 /* IEEE Simple Element only */
1087 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1088 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1089                                                 /* IEEE Simple Element only */
1090 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR   (0x03)
1091                                                 /* IEEE Chain Element only */
1092 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR   \
1093         (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1094
1095 /****************************************************************************
1096 *  IEEE SGE operation Macros
1097 ****************************************************************************/
1098
1099 /* SIMPLE FlagsLength manipulations... */
1100 #define MPI2_IEEE32_SGE_SET_FLAGS(f)     ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1101 #define MPI2_IEEE32_SGE_GET_FLAGS(f)     (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1102 #define MPI2_IEEE32_SGE_LENGTH(f)        ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1103
1104 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)      (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1105
1106 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg)             MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1107 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg)            MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1108 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l)  (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1109
1110 /* CAUTION - The following are READ-MODIFY-WRITE! */
1111 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f)    (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1112 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l)   (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1113
1114
1115
1116
1117 /*****************************************************************************
1118 *
1119 *        Fusion-MPT MPI/IEEE Scatter Gather Unions
1120 *
1121 *****************************************************************************/
1122
1123 typedef union _MPI2_SIMPLE_SGE_UNION
1124 {
1125     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1126     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1127 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1128   Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1129
1130
1131 typedef union _MPI2_SGE_IO_UNION
1132 {
1133     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1134     MPI2_SGE_CHAIN_UNION        MpiChain;
1135     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1136     MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
1137 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1138   Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1139
1140
1141 /****************************************************************************
1142 *
1143 *  Values for SGLFlags field, used in many request messages with an SGL
1144 *
1145 ****************************************************************************/
1146
1147 /* values for MPI SGL Data Location Address Space subfield */
1148 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1149 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1150 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1151 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1152 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1153 /* values for SGL Type subfield */
1154 #define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1155 #define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1156 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1157 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1158
1159
1160 #endif
1161