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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm80xx_hwi.c
blob9f91030211e84e4edb8479e84ef26c8dabe509a0
1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48 /**
49 * read_main_config_table - read the configure table and save it.
50 * @pm8001_ha: our hba card information
51 */
52 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53 {
54 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
55
56 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
57 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
58 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
59 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
60 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
61 pm8001_mr32(address, MAIN_FW_REVISION);
62 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
63 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
64 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
65 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
67 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
68 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
69 pm8001_mr32(address, MAIN_GST_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
71 pm8001_mr32(address, MAIN_IBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
73 pm8001_mr32(address, MAIN_OBQ_OFFSET);
74
75 /* read Error Dump Offset and Length */
76 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
78 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
80 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
84
85 /* read GPIO LED settings from the configuration table */
86 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
87 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
88
89 /* read analog Setting offset from the configuration table */
90 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
91 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
92
93 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
94 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
95 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
96 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
97 }
98
99 /**
100 * read_general_status_table - read the general status table and save it.
101 * @pm8001_ha: our hba card information
102 */
103 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
104 {
105 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
106 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
107 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
108 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
109 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
110 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
111 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
112 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
113 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
114 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
115 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
116 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
117 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
118 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
119 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
120 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
121 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
122 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
123 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
124 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
125 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
126 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
127 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
128 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
129 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
130 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
131 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
132 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
133 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
134 }
135 /**
136 * read_phy_attr_table - read the phy attribute table and save it.
137 * @pm8001_ha: our hba card information
138 */
139 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
140 {
141 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
142 pm8001_ha->phy_attr_table.phystart1_16[0] =
143 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
144 pm8001_ha->phy_attr_table.phystart1_16[1] =
145 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
146 pm8001_ha->phy_attr_table.phystart1_16[2] =
147 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
148 pm8001_ha->phy_attr_table.phystart1_16[3] =
149 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
150 pm8001_ha->phy_attr_table.phystart1_16[4] =
151 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
152 pm8001_ha->phy_attr_table.phystart1_16[5] =
153 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
154 pm8001_ha->phy_attr_table.phystart1_16[6] =
155 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
156 pm8001_ha->phy_attr_table.phystart1_16[7] =
157 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
158 pm8001_ha->phy_attr_table.phystart1_16[8] =
159 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
160 pm8001_ha->phy_attr_table.phystart1_16[9] =
161 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
162 pm8001_ha->phy_attr_table.phystart1_16[10] =
163 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
164 pm8001_ha->phy_attr_table.phystart1_16[11] =
165 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
166 pm8001_ha->phy_attr_table.phystart1_16[12] =
167 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
168 pm8001_ha->phy_attr_table.phystart1_16[13] =
169 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
170 pm8001_ha->phy_attr_table.phystart1_16[14] =
171 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
172 pm8001_ha->phy_attr_table.phystart1_16[15] =
173 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
174
175 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
176 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
177 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
178 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
179 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
180 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
181 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
182 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
183 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
184 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
185 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
186 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
187 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
188 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
189 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
190 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
191 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
192 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
193 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
194 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
195 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
196 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
197 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
198 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
199 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
200 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
201 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
202 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
203 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
204 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
205 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
206 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
207
208 }
209
210 /**
211 * read_inbnd_queue_table - read the inbound queue table and save it.
212 * @pm8001_ha: our hba card information
213 */
214 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
215 {
216 int i;
217 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
218 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
219 u32 offset = i * 0x20;
220 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
221 get_pci_bar_index(pm8001_mr32(address,
222 (offset + IB_PIPCI_BAR)));
223 pm8001_ha->inbnd_q_tbl[i].pi_offset =
224 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
225 }
226 }
227
228 /**
229 * read_outbnd_queue_table - read the outbound queue table and save it.
230 * @pm8001_ha: our hba card information
231 */
232 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
233 {
234 int i;
235 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
236 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
237 u32 offset = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(address,
240 (offset + OB_CIPCI_BAR)));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
243 }
244 }
245
246 /**
247 * init_default_table_values - init the default table.
248 * @pm8001_ha: our hba card information
249 */
250 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
251 {
252 int i;
253 u32 offsetib, offsetob;
254 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
255 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
256
257 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
258 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
259 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
260 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
261 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
262 PM8001_EVENT_LOG_SIZE;
263 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
264 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
265 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
266 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
267 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
268 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
269 PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
272
273 /* Disable end to end CRC checking */
274 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
275
276 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
277 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
278 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
279 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
280 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
281 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
282 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
283 pm8001_ha->inbnd_q_tbl[i].base_virt =
284 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
285 pm8001_ha->inbnd_q_tbl[i].total_length =
286 pm8001_ha->memoryMap.region[IB + i].total_len;
287 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
288 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
289 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
290 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
291 pm8001_ha->inbnd_q_tbl[i].ci_virt =
292 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
293 offsetib = i * 0x20;
294 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
295 get_pci_bar_index(pm8001_mr32(addressib,
296 (offsetib + 0x14)));
297 pm8001_ha->inbnd_q_tbl[i].pi_offset =
298 pm8001_mr32(addressib, (offsetib + 0x18));
299 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
300 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
301 }
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
304 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
305 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
306 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
307 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
308 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
309 pm8001_ha->outbnd_q_tbl[i].base_virt =
310 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
311 pm8001_ha->outbnd_q_tbl[i].total_length =
312 pm8001_ha->memoryMap.region[OB + i].total_len;
313 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
314 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
315 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
316 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
317 /* interrupt vector based on oq */
318 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
319 pm8001_ha->outbnd_q_tbl[i].pi_virt =
320 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
321 offsetob = i * 0x24;
322 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
323 get_pci_bar_index(pm8001_mr32(addressob,
324 offsetob + 0x14));
325 pm8001_ha->outbnd_q_tbl[i].ci_offset =
326 pm8001_mr32(addressob, (offsetob + 0x18));
327 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
328 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
329 }
330 }
331
332 /**
333 * update_main_config_table - update the main default table to the HBA.
334 * @pm8001_ha: our hba card information
335 */
336 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
337 {
338 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
339 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
340 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
341 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
342 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
343 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
344 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
345 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
346 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
347 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
348 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
349 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
350 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
351 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
352 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
353 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
354 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
355 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
356 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
357 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
358 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
359 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
360 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
361
362 /* SPCv specific */
363 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
364 /* Set GPIOLED to 0x2 for LED indicator */
365 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
366 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
367 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
368
369 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
370 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
371 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
372 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
373 }
374
375 /**
376 * update_inbnd_queue_table - update the inbound queue table to the HBA.
377 * @pm8001_ha: our hba card information
378 */
379 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
380 int number)
381 {
382 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
383 u16 offset = number * 0x20;
384 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
385 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
386 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
387 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
388 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
389 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
390 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
391 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
392 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
393 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
394 }
395
396 /**
397 * update_outbnd_queue_table - update the outbound queue table to the HBA.
398 * @pm8001_ha: our hba card information
399 */
400 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
401 int number)
402 {
403 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
404 u16 offset = number * 0x24;
405 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
406 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
407 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
408 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
409 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
410 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
411 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
412 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
413 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
414 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
415 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
416 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
417 }
418
419 /**
420 * mpi_init_check - check firmware initialization status.
421 * @pm8001_ha: our hba card information
422 */
423 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
424 {
425 u32 max_wait_count;
426 u32 value;
427 u32 gst_len_mpistate;
428
429 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
430 table is updated */
431 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
432 /* wait until Inbound DoorBell Clear Register toggled */
433 max_wait_count = 2 * 1000 * 1000;/* 2 sec for spcv/ve */
434 do {
435 udelay(1);
436 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
437 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
438 } while ((value != 0) && (--max_wait_count));
439
440 if (!max_wait_count)
441 return -1;
442 /* check the MPI-State for initialization upto 100ms*/
443 max_wait_count = 100 * 1000;/* 100 msec */
444 do {
445 udelay(1);
446 gst_len_mpistate =
447 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
448 GST_GSTLEN_MPIS_OFFSET);
449 } while ((GST_MPI_STATE_INIT !=
450 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
451 if (!max_wait_count)
452 return -1;
453
454 /* check MPI Initialization error */
455 gst_len_mpistate = gst_len_mpistate >> 16;
456 if (0x0000 != gst_len_mpistate)
457 return -1;
458
459 return 0;
460 }
461
462 /**
463 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
464 * @pm8001_ha: our hba card information
465 */
466 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
467 {
468 u32 value;
469 u32 max_wait_count;
470 u32 max_wait_time;
471 int ret = 0;
472
473 /* reset / PCIe ready */
474 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
475 do {
476 udelay(1);
477 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
478 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
479
480 /* check ila status */
481 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
482 do {
483 udelay(1);
484 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
485 } while (((value & SCRATCH_PAD_ILA_READY) !=
486 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
487 if (!max_wait_count)
488 ret = -1;
489 else {
490 PM8001_MSG_DBG(pm8001_ha,
491 pm8001_printk(" ila ready status in %d millisec\n",
492 (max_wait_time - max_wait_count)));
493 }
494
495 /* check RAAE status */
496 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
497 do {
498 udelay(1);
499 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
500 } while (((value & SCRATCH_PAD_RAAE_READY) !=
501 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
502 if (!max_wait_count)
503 ret = -1;
504 else {
505 PM8001_MSG_DBG(pm8001_ha,
506 pm8001_printk(" raae ready status in %d millisec\n",
507 (max_wait_time - max_wait_count)));
508 }
509
510 /* check iop0 status */
511 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
512 do {
513 udelay(1);
514 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
515 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
516 (--max_wait_count));
517 if (!max_wait_count)
518 ret = -1;
519 else {
520 PM8001_MSG_DBG(pm8001_ha,
521 pm8001_printk(" iop0 ready status in %d millisec\n",
522 (max_wait_time - max_wait_count)));
523 }
524
525 /* check iop1 status only for 16 port controllers */
526 if ((pm8001_ha->chip_id != chip_8008) &&
527 (pm8001_ha->chip_id != chip_8009)) {
528 /* 200 milli sec */
529 max_wait_time = max_wait_count = 200 * 1000;
530 do {
531 udelay(1);
532 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
533 } while (((value & SCRATCH_PAD_IOP1_READY) !=
534 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
535 if (!max_wait_count)
536 ret = -1;
537 else {
538 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
539 "iop1 ready status in %d millisec\n",
540 (max_wait_time - max_wait_count)));
541 }
542 }
543
544 return ret;
545 }
546
547 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
548 {
549 void __iomem *base_addr;
550 u32 value;
551 u32 offset;
552 u32 pcibar;
553 u32 pcilogic;
554
555 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
556 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
557
558 PM8001_INIT_DBG(pm8001_ha,
559 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
560 offset, value));
561 pcilogic = (value & 0xFC000000) >> 26;
562 pcibar = get_pci_bar_index(pcilogic);
563 PM8001_INIT_DBG(pm8001_ha,
564 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
565 pm8001_ha->main_cfg_tbl_addr = base_addr =
566 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
567 pm8001_ha->general_stat_tbl_addr =
568 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
569 0xFFFFFF);
570 pm8001_ha->inbnd_q_tbl_addr =
571 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
572 0xFFFFFF);
573 pm8001_ha->outbnd_q_tbl_addr =
574 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
575 0xFFFFFF);
576 pm8001_ha->ivt_tbl_addr =
577 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
578 0xFFFFFF);
579 pm8001_ha->pspa_q_tbl_addr =
580 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
581 0xFFFFFF);
582
583 PM8001_INIT_DBG(pm8001_ha,
584 pm8001_printk("GST OFFSET 0x%x\n",
585 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
586 PM8001_INIT_DBG(pm8001_ha,
587 pm8001_printk("INBND OFFSET 0x%x\n",
588 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
589 PM8001_INIT_DBG(pm8001_ha,
590 pm8001_printk("OBND OFFSET 0x%x\n",
591 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
592 PM8001_INIT_DBG(pm8001_ha,
593 pm8001_printk("IVT OFFSET 0x%x\n",
594 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
595 PM8001_INIT_DBG(pm8001_ha,
596 pm8001_printk("PSPA OFFSET 0x%x\n",
597 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
598 PM8001_INIT_DBG(pm8001_ha,
599 pm8001_printk("addr - main cfg %p general status %p\n",
600 pm8001_ha->main_cfg_tbl_addr,
601 pm8001_ha->general_stat_tbl_addr));
602 PM8001_INIT_DBG(pm8001_ha,
603 pm8001_printk("addr - inbnd %p obnd %p\n",
604 pm8001_ha->inbnd_q_tbl_addr,
605 pm8001_ha->outbnd_q_tbl_addr));
606 PM8001_INIT_DBG(pm8001_ha,
607 pm8001_printk("addr - pspa %p ivt %p\n",
608 pm8001_ha->pspa_q_tbl_addr,
609 pm8001_ha->ivt_tbl_addr));
610 }
611
612 /**
613 * pm80xx_set_thermal_config - support the thermal configuration
614 * @pm8001_ha: our hba card information.
615 */
616 int
617 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
618 {
619 struct set_ctrl_cfg_req payload;
620 struct inbound_queue_table *circularQ;
621 int rc;
622 u32 tag;
623 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
624
625 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
626 rc = pm8001_tag_alloc(pm8001_ha, &tag);
627 if (rc)
628 return -1;
629
630 circularQ = &pm8001_ha->inbnd_q_tbl[0];
631 payload.tag = cpu_to_le32(tag);
632 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
633 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
634 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
635
636 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
637 return rc;
638
639 }
640
641 /**
642 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
643 * Timer configuration page
644 * @pm8001_ha: our hba card information.
645 */
646 static int
647 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
648 {
649 struct set_ctrl_cfg_req payload;
650 struct inbound_queue_table *circularQ;
651 SASProtocolTimerConfig_t SASConfigPage;
652 int rc;
653 u32 tag;
654 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
655
656 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
657 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
658
659 rc = pm8001_tag_alloc(pm8001_ha, &tag);
660
661 if (rc)
662 return -1;
663
664 circularQ = &pm8001_ha->inbnd_q_tbl[0];
665 payload.tag = cpu_to_le32(tag);
666
667 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
668 SASConfigPage.MST_MSI = 3 << 15;
669 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
670 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
671 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
672 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
673
674 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
675 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
676
677
678 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
679 SAS_OPNRJT_RTRY_INTVL;
680 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
681 | SAS_COPNRJT_RTRY_TMO;
682 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
683 | SAS_COPNRJT_RTRY_THR;
684 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
685
686 PM8001_INIT_DBG(pm8001_ha,
687 pm8001_printk("SASConfigPage.pageCode "
688 "0x%08x\n", SASConfigPage.pageCode));
689 PM8001_INIT_DBG(pm8001_ha,
690 pm8001_printk("SASConfigPage.MST_MSI "
691 " 0x%08x\n", SASConfigPage.MST_MSI));
692 PM8001_INIT_DBG(pm8001_ha,
693 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
694 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
695 PM8001_INIT_DBG(pm8001_ha,
696 pm8001_printk("SASConfigPage.STP_FRM_TMO "
697 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
698 PM8001_INIT_DBG(pm8001_ha,
699 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
700 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
701 PM8001_INIT_DBG(pm8001_ha,
702 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
703 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
704 PM8001_INIT_DBG(pm8001_ha,
705 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
706 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
707 PM8001_INIT_DBG(pm8001_ha,
708 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
709 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
710 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
711 " 0x%08x\n", SASConfigPage.MAX_AIP));
712
713 memcpy(&payload.cfg_pg, &SASConfigPage,
714 sizeof(SASProtocolTimerConfig_t));
715
716 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
717
718 return rc;
719 }
720
721 /**
722 * pm80xx_get_encrypt_info - Check for encryption
723 * @pm8001_ha: our hba card information.
724 */
725 static int
726 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
727 {
728 u32 scratch3_value;
729 int ret;
730
731 /* Read encryption status from SCRATCH PAD 3 */
732 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
733
734 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
735 SCRATCH_PAD3_ENC_READY) {
736 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
737 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
738 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
739 SCRATCH_PAD3_SMF_ENABLED)
740 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
741 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
742 SCRATCH_PAD3_SMA_ENABLED)
743 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
744 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
745 SCRATCH_PAD3_SMB_ENABLED)
746 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
747 pm8001_ha->encrypt_info.status = 0;
748 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
749 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
750 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
751 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
752 pm8001_ha->encrypt_info.sec_mode,
753 pm8001_ha->encrypt_info.status));
754 ret = 0;
755 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
756 SCRATCH_PAD3_ENC_DISABLED) {
757 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
758 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
759 scratch3_value));
760 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
761 pm8001_ha->encrypt_info.cipher_mode = 0;
762 pm8001_ha->encrypt_info.sec_mode = 0;
763 return 0;
764 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
765 SCRATCH_PAD3_ENC_DIS_ERR) {
766 pm8001_ha->encrypt_info.status =
767 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
768 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
769 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
770 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
771 SCRATCH_PAD3_SMF_ENABLED)
772 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
773 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
774 SCRATCH_PAD3_SMA_ENABLED)
775 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
776 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
777 SCRATCH_PAD3_SMB_ENABLED)
778 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
779 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
780 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
781 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
782 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
783 pm8001_ha->encrypt_info.sec_mode,
784 pm8001_ha->encrypt_info.status));
785 ret = -1;
786 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
787 SCRATCH_PAD3_ENC_ENA_ERR) {
788
789 pm8001_ha->encrypt_info.status =
790 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
791 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
792 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
793 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
794 SCRATCH_PAD3_SMF_ENABLED)
795 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
796 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
797 SCRATCH_PAD3_SMA_ENABLED)
798 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
799 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
800 SCRATCH_PAD3_SMB_ENABLED)
801 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
802
803 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
804 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
805 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
806 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
807 pm8001_ha->encrypt_info.sec_mode,
808 pm8001_ha->encrypt_info.status));
809 ret = -1;
810 }
811 return ret;
812 }
813
814 /**
815 * pm80xx_encrypt_update - update flash with encryption informtion
816 * @pm8001_ha: our hba card information.
817 */
818 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
819 {
820 struct kek_mgmt_req payload;
821 struct inbound_queue_table *circularQ;
822 int rc;
823 u32 tag;
824 u32 opc = OPC_INB_KEK_MANAGEMENT;
825
826 memset(&payload, 0, sizeof(struct kek_mgmt_req));
827 rc = pm8001_tag_alloc(pm8001_ha, &tag);
828 if (rc)
829 return -1;
830
831 circularQ = &pm8001_ha->inbnd_q_tbl[0];
832 payload.tag = cpu_to_le32(tag);
833 /* Currently only one key is used. New KEK index is 1.
834 * Current KEK index is 1. Store KEK to NVRAM is 1.
835 */
836 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
837 KEK_MGMT_SUBOP_KEYCARDUPDATE);
838
839 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
840
841 return rc;
842 }
843
844 /**
845 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
846 * @pm8001_ha: our hba card information
847 */
848 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
849 {
850 int ret;
851 u8 i = 0;
852
853 /* check the firmware status */
854 if (-1 == check_fw_ready(pm8001_ha)) {
855 PM8001_FAIL_DBG(pm8001_ha,
856 pm8001_printk("Firmware is not ready!\n"));
857 return -EBUSY;
858 }
859
860 /* Initialize pci space address eg: mpi offset */
861 init_pci_device_addresses(pm8001_ha);
862 init_default_table_values(pm8001_ha);
863 read_main_config_table(pm8001_ha);
864 read_general_status_table(pm8001_ha);
865 read_inbnd_queue_table(pm8001_ha);
866 read_outbnd_queue_table(pm8001_ha);
867 read_phy_attr_table(pm8001_ha);
868
869 /* update main config table ,inbound table and outbound table */
870 update_main_config_table(pm8001_ha);
871 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
872 update_inbnd_queue_table(pm8001_ha, i);
873 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
874 update_outbnd_queue_table(pm8001_ha, i);
875
876 /* notify firmware update finished and check initialization status */
877 if (0 == mpi_init_check(pm8001_ha)) {
878 PM8001_INIT_DBG(pm8001_ha,
879 pm8001_printk("MPI initialize successful!\n"));
880 } else
881 return -EBUSY;
882
883 /* send SAS protocol timer configuration page to FW */
884 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
885
886 /* Check for encryption */
887 if (pm8001_ha->chip->encrypt) {
888 PM8001_INIT_DBG(pm8001_ha,
889 pm8001_printk("Checking for encryption\n"));
890 ret = pm80xx_get_encrypt_info(pm8001_ha);
891 if (ret == -1) {
892 PM8001_INIT_DBG(pm8001_ha,
893 pm8001_printk("Encryption error !!\n"));
894 if (pm8001_ha->encrypt_info.status == 0x81) {
895 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
896 "Encryption enabled with error."
897 "Saving encryption key to flash\n"));
898 pm80xx_encrypt_update(pm8001_ha);
899 }
900 }
901 }
902 return 0;
903 }
904
905 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
906 {
907 u32 max_wait_count;
908 u32 value;
909 u32 gst_len_mpistate;
910 init_pci_device_addresses(pm8001_ha);
911 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
912 table is stop */
913 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
914
915 /* wait until Inbound DoorBell Clear Register toggled */
916 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
917 do {
918 udelay(1);
919 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
920 value &= SPCv_MSGU_CFG_TABLE_RESET;
921 } while ((value != 0) && (--max_wait_count));
922
923 if (!max_wait_count) {
924 PM8001_FAIL_DBG(pm8001_ha,
925 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
926 return -1;
927 }
928
929 /* check the MPI-State for termination in progress */
930 /* wait until Inbound DoorBell Clear Register toggled */
931 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
932 do {
933 udelay(1);
934 gst_len_mpistate =
935 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
936 GST_GSTLEN_MPIS_OFFSET);
937 if (GST_MPI_STATE_UNINIT ==
938 (gst_len_mpistate & GST_MPI_STATE_MASK))
939 break;
940 } while (--max_wait_count);
941 if (!max_wait_count) {
942 PM8001_FAIL_DBG(pm8001_ha,
943 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
944 gst_len_mpistate & GST_MPI_STATE_MASK));
945 return -1;
946 }
947
948 return 0;
949 }
950
951 /**
952 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
953 * the FW register status to the originated status.
954 * @pm8001_ha: our hba card information
955 */
956
957 static int
958 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
959 {
960 u32 regval;
961 u32 bootloader_state;
962
963 /* Check if MPI is in ready state to reset */
964 if (mpi_uninit_check(pm8001_ha) != 0) {
965 PM8001_FAIL_DBG(pm8001_ha,
966 pm8001_printk("MPI state is not ready\n"));
967 return -1;
968 }
969
970 /* checked for reset register normal state; 0x0 */
971 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
972 PM8001_INIT_DBG(pm8001_ha,
973 pm8001_printk("reset register before write : 0x%x\n", regval));
974
975 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
976 mdelay(500);
977
978 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
979 PM8001_INIT_DBG(pm8001_ha,
980 pm8001_printk("reset register after write 0x%x\n", regval));
981
982 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
983 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
984 PM8001_MSG_DBG(pm8001_ha,
985 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
986 regval));
987 } else {
988 PM8001_MSG_DBG(pm8001_ha,
989 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
990 regval));
991
992 /* check bootloader is successfully executed or in HDA mode */
993 bootloader_state =
994 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
995 SCRATCH_PAD1_BOOTSTATE_MASK;
996
997 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
998 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
999 "Bootloader state - HDA mode SEEPROM\n"));
1000 } else if (bootloader_state ==
1001 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1002 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1003 "Bootloader state - HDA mode Bootstrap Pin\n"));
1004 } else if (bootloader_state ==
1005 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1006 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1007 "Bootloader state - HDA mode soft reset\n"));
1008 } else if (bootloader_state ==
1009 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1010 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1011 "Bootloader state-HDA mode critical error\n"));
1012 }
1013 return -EBUSY;
1014 }
1015
1016 /* check the firmware status after reset */
1017 if (-1 == check_fw_ready(pm8001_ha)) {
1018 PM8001_FAIL_DBG(pm8001_ha,
1019 pm8001_printk("Firmware is not ready!\n"));
1020 return -EBUSY;
1021 }
1022 PM8001_INIT_DBG(pm8001_ha,
1023 pm8001_printk("SPCv soft reset Complete\n"));
1024 return 0;
1025 }
1026
1027 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1028 {
1029 u32 i;
1030
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("chip reset start\n"));
1033
1034 /* do SPCv chip reset. */
1035 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1036 PM8001_INIT_DBG(pm8001_ha,
1037 pm8001_printk("SPC soft reset Complete\n"));
1038
1039 /* Check this ..whether delay is required or no */
1040 /* delay 10 usec */
1041 udelay(10);
1042
1043 /* wait for 20 msec until the firmware gets reloaded */
1044 i = 20;
1045 do {
1046 mdelay(1);
1047 } while ((--i) != 0);
1048
1049 PM8001_INIT_DBG(pm8001_ha,
1050 pm8001_printk("chip reset finished\n"));
1051 }
1052
1053 /**
1054 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1055 * @pm8001_ha: our hba card information
1056 */
1057 static void
1058 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1059 {
1060 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1061 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1062 }
1063
1064 /**
1065 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1066 * @pm8001_ha: our hba card information
1067 */
1068 static void
1069 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1070 {
1071 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1072 }
1073
1074 /**
1075 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1076 * @pm8001_ha: our hba card information
1077 */
1078 static void
1079 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1080 {
1081 #ifdef PM8001_USE_MSIX
1082 u32 mask;
1083 mask = (u32)(1 << vec);
1084
1085 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1086 return;
1087 #endif
1088 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1089
1090 }
1091
1092 /**
1093 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1094 * @pm8001_ha: our hba card information
1095 */
1096 static void
1097 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1098 {
1099 #ifdef PM8001_USE_MSIX
1100 u32 mask;
1101 if (vec == 0xFF)
1102 mask = 0xFFFFFFFF;
1103 else
1104 mask = (u32)(1 << vec);
1105 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1106 return;
1107 #endif
1108 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1109 }
1110
1111 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1112 struct pm8001_device *pm8001_ha_dev)
1113 {
1114 int res;
1115 u32 ccb_tag;
1116 struct pm8001_ccb_info *ccb;
1117 struct sas_task *task = NULL;
1118 struct task_abort_req task_abort;
1119 struct inbound_queue_table *circularQ;
1120 u32 opc = OPC_INB_SATA_ABORT;
1121 int ret;
1122
1123 if (!pm8001_ha_dev) {
1124 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1125 return;
1126 }
1127
1128 task = sas_alloc_slow_task(GFP_ATOMIC);
1129
1130 if (!task) {
1131 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1132 "allocate task\n"));
1133 return;
1134 }
1135
1136 task->task_done = pm8001_task_done;
1137
1138 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1139 if (res)
1140 return;
1141
1142 ccb = &pm8001_ha->ccb_info[ccb_tag];
1143 ccb->device = pm8001_ha_dev;
1144 ccb->ccb_tag = ccb_tag;
1145 ccb->task = task;
1146
1147 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1148
1149 memset(&task_abort, 0, sizeof(task_abort));
1150 task_abort.abort_all = cpu_to_le32(1);
1151 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1152 task_abort.tag = cpu_to_le32(ccb_tag);
1153
1154 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1155
1156 }
1157
1158 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1159 struct pm8001_device *pm8001_ha_dev)
1160 {
1161 struct sata_start_req sata_cmd;
1162 int res;
1163 u32 ccb_tag;
1164 struct pm8001_ccb_info *ccb;
1165 struct sas_task *task = NULL;
1166 struct host_to_dev_fis fis;
1167 struct domain_device *dev;
1168 struct inbound_queue_table *circularQ;
1169 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1170
1171 task = sas_alloc_slow_task(GFP_ATOMIC);
1172
1173 if (!task) {
1174 PM8001_FAIL_DBG(pm8001_ha,
1175 pm8001_printk("cannot allocate task !!!\n"));
1176 return;
1177 }
1178 task->task_done = pm8001_task_done;
1179
1180 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1181 if (res) {
1182 PM8001_FAIL_DBG(pm8001_ha,
1183 pm8001_printk("cannot allocate tag !!!\n"));
1184 return;
1185 }
1186
1187 /* allocate domain device by ourselves as libsas
1188 * is not going to provide any
1189 */
1190 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1191 if (!dev) {
1192 PM8001_FAIL_DBG(pm8001_ha,
1193 pm8001_printk("Domain device cannot be allocated\n"));
1194 sas_free_task(task);
1195 return;
1196 } else {
1197 task->dev = dev;
1198 task->dev->lldd_dev = pm8001_ha_dev;
1199 }
1200
1201 ccb = &pm8001_ha->ccb_info[ccb_tag];
1202 ccb->device = pm8001_ha_dev;
1203 ccb->ccb_tag = ccb_tag;
1204 ccb->task = task;
1205 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1206 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1207
1208 memset(&sata_cmd, 0, sizeof(sata_cmd));
1209 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1210
1211 /* construct read log FIS */
1212 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1213 fis.fis_type = 0x27;
1214 fis.flags = 0x80;
1215 fis.command = ATA_CMD_READ_LOG_EXT;
1216 fis.lbal = 0x10;
1217 fis.sector_count = 0x1;
1218
1219 sata_cmd.tag = cpu_to_le32(ccb_tag);
1220 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1221 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1222 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1223
1224 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1225
1226 }
1227
1228 /**
1229 * mpi_ssp_completion- process the event that FW response to the SSP request.
1230 * @pm8001_ha: our hba card information
1231 * @piomb: the message contents of this outbound message.
1232 *
1233 * When FW has completed a ssp request for example a IO request, after it has
1234 * filled the SG data with the data, it will trigger this event represent
1235 * that he has finished the job,please check the coresponding buffer.
1236 * So we will tell the caller who maybe waiting the result to tell upper layer
1237 * that the task has been finished.
1238 */
1239 static void
1240 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1241 {
1242 struct sas_task *t;
1243 struct pm8001_ccb_info *ccb;
1244 unsigned long flags;
1245 u32 status;
1246 u32 param;
1247 u32 tag;
1248 struct ssp_completion_resp *psspPayload;
1249 struct task_status_struct *ts;
1250 struct ssp_response_iu *iu;
1251 struct pm8001_device *pm8001_dev;
1252 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1253 status = le32_to_cpu(psspPayload->status);
1254 tag = le32_to_cpu(psspPayload->tag);
1255 ccb = &pm8001_ha->ccb_info[tag];
1256 if ((status == IO_ABORTED) && ccb->open_retry) {
1257 /* Being completed by another */
1258 ccb->open_retry = 0;
1259 return;
1260 }
1261 pm8001_dev = ccb->device;
1262 param = le32_to_cpu(psspPayload->param);
1263 t = ccb->task;
1264
1265 if (status && status != IO_UNDERFLOW)
1266 PM8001_FAIL_DBG(pm8001_ha,
1267 pm8001_printk("sas IO status 0x%x\n", status));
1268 if (unlikely(!t || !t->lldd_task || !t->dev))
1269 return;
1270 ts = &t->task_status;
1271 switch (status) {
1272 case IO_SUCCESS:
1273 PM8001_IO_DBG(pm8001_ha,
1274 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1275 param));
1276 if (param == 0) {
1277 ts->resp = SAS_TASK_COMPLETE;
1278 ts->stat = SAM_STAT_GOOD;
1279 } else {
1280 ts->resp = SAS_TASK_COMPLETE;
1281 ts->stat = SAS_PROTO_RESPONSE;
1282 ts->residual = param;
1283 iu = &psspPayload->ssp_resp_iu;
1284 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1285 }
1286 if (pm8001_dev)
1287 pm8001_dev->running_req--;
1288 break;
1289 case IO_ABORTED:
1290 PM8001_IO_DBG(pm8001_ha,
1291 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1292 ts->resp = SAS_TASK_COMPLETE;
1293 ts->stat = SAS_ABORTED_TASK;
1294 break;
1295 case IO_UNDERFLOW:
1296 /* SSP Completion with error */
1297 PM8001_IO_DBG(pm8001_ha,
1298 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1299 param));
1300 ts->resp = SAS_TASK_COMPLETE;
1301 ts->stat = SAS_DATA_UNDERRUN;
1302 ts->residual = param;
1303 if (pm8001_dev)
1304 pm8001_dev->running_req--;
1305 break;
1306 case IO_NO_DEVICE:
1307 PM8001_IO_DBG(pm8001_ha,
1308 pm8001_printk("IO_NO_DEVICE\n"));
1309 ts->resp = SAS_TASK_UNDELIVERED;
1310 ts->stat = SAS_PHY_DOWN;
1311 break;
1312 case IO_XFER_ERROR_BREAK:
1313 PM8001_IO_DBG(pm8001_ha,
1314 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1315 ts->resp = SAS_TASK_COMPLETE;
1316 ts->stat = SAS_OPEN_REJECT;
1317 /* Force the midlayer to retry */
1318 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1319 break;
1320 case IO_XFER_ERROR_PHY_NOT_READY:
1321 PM8001_IO_DBG(pm8001_ha,
1322 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1323 ts->resp = SAS_TASK_COMPLETE;
1324 ts->stat = SAS_OPEN_REJECT;
1325 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1326 break;
1327 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1328 PM8001_IO_DBG(pm8001_ha,
1329 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1330 ts->resp = SAS_TASK_COMPLETE;
1331 ts->stat = SAS_OPEN_REJECT;
1332 ts->open_rej_reason = SAS_OREJ_EPROTO;
1333 break;
1334 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1335 PM8001_IO_DBG(pm8001_ha,
1336 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1337 ts->resp = SAS_TASK_COMPLETE;
1338 ts->stat = SAS_OPEN_REJECT;
1339 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1340 break;
1341 case IO_OPEN_CNX_ERROR_BREAK:
1342 PM8001_IO_DBG(pm8001_ha,
1343 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1344 ts->resp = SAS_TASK_COMPLETE;
1345 ts->stat = SAS_OPEN_REJECT;
1346 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1347 break;
1348 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1349 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1350 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1351 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1352 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1353 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1354 PM8001_IO_DBG(pm8001_ha,
1355 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1356 ts->resp = SAS_TASK_COMPLETE;
1357 ts->stat = SAS_OPEN_REJECT;
1358 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1359 if (!t->uldd_task)
1360 pm8001_handle_event(pm8001_ha,
1361 pm8001_dev,
1362 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1363 break;
1364 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1365 PM8001_IO_DBG(pm8001_ha,
1366 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1367 ts->resp = SAS_TASK_COMPLETE;
1368 ts->stat = SAS_OPEN_REJECT;
1369 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1370 break;
1371 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1372 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1373 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1374 ts->resp = SAS_TASK_COMPLETE;
1375 ts->stat = SAS_OPEN_REJECT;
1376 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1377 break;
1378 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1379 PM8001_IO_DBG(pm8001_ha,
1380 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1381 ts->resp = SAS_TASK_UNDELIVERED;
1382 ts->stat = SAS_OPEN_REJECT;
1383 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1384 break;
1385 case IO_XFER_ERROR_NAK_RECEIVED:
1386 PM8001_IO_DBG(pm8001_ha,
1387 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1388 ts->resp = SAS_TASK_COMPLETE;
1389 ts->stat = SAS_OPEN_REJECT;
1390 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1391 break;
1392 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1393 PM8001_IO_DBG(pm8001_ha,
1394 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1395 ts->resp = SAS_TASK_COMPLETE;
1396 ts->stat = SAS_NAK_R_ERR;
1397 break;
1398 case IO_XFER_ERROR_DMA:
1399 PM8001_IO_DBG(pm8001_ha,
1400 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1401 ts->resp = SAS_TASK_COMPLETE;
1402 ts->stat = SAS_OPEN_REJECT;
1403 break;
1404 case IO_XFER_OPEN_RETRY_TIMEOUT:
1405 PM8001_IO_DBG(pm8001_ha,
1406 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1407 ts->resp = SAS_TASK_COMPLETE;
1408 ts->stat = SAS_OPEN_REJECT;
1409 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1410 break;
1411 case IO_XFER_ERROR_OFFSET_MISMATCH:
1412 PM8001_IO_DBG(pm8001_ha,
1413 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1414 ts->resp = SAS_TASK_COMPLETE;
1415 ts->stat = SAS_OPEN_REJECT;
1416 break;
1417 case IO_PORT_IN_RESET:
1418 PM8001_IO_DBG(pm8001_ha,
1419 pm8001_printk("IO_PORT_IN_RESET\n"));
1420 ts->resp = SAS_TASK_COMPLETE;
1421 ts->stat = SAS_OPEN_REJECT;
1422 break;
1423 case IO_DS_NON_OPERATIONAL:
1424 PM8001_IO_DBG(pm8001_ha,
1425 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1426 ts->resp = SAS_TASK_COMPLETE;
1427 ts->stat = SAS_OPEN_REJECT;
1428 if (!t->uldd_task)
1429 pm8001_handle_event(pm8001_ha,
1430 pm8001_dev,
1431 IO_DS_NON_OPERATIONAL);
1432 break;
1433 case IO_DS_IN_RECOVERY:
1434 PM8001_IO_DBG(pm8001_ha,
1435 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1436 ts->resp = SAS_TASK_COMPLETE;
1437 ts->stat = SAS_OPEN_REJECT;
1438 break;
1439 case IO_TM_TAG_NOT_FOUND:
1440 PM8001_IO_DBG(pm8001_ha,
1441 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1442 ts->resp = SAS_TASK_COMPLETE;
1443 ts->stat = SAS_OPEN_REJECT;
1444 break;
1445 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1446 PM8001_IO_DBG(pm8001_ha,
1447 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1448 ts->resp = SAS_TASK_COMPLETE;
1449 ts->stat = SAS_OPEN_REJECT;
1450 break;
1451 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1452 PM8001_IO_DBG(pm8001_ha,
1453 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1454 ts->resp = SAS_TASK_COMPLETE;
1455 ts->stat = SAS_OPEN_REJECT;
1456 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1457 break;
1458 default:
1459 PM8001_IO_DBG(pm8001_ha,
1460 pm8001_printk("Unknown status 0x%x\n", status));
1461 /* not allowed case. Therefore, return failed status */
1462 ts->resp = SAS_TASK_COMPLETE;
1463 ts->stat = SAS_OPEN_REJECT;
1464 break;
1465 }
1466 PM8001_IO_DBG(pm8001_ha,
1467 pm8001_printk("scsi_status = 0x%x\n ",
1468 psspPayload->ssp_resp_iu.status));
1469 spin_lock_irqsave(&t->task_state_lock, flags);
1470 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1471 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1472 t->task_state_flags |= SAS_TASK_STATE_DONE;
1473 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1474 spin_unlock_irqrestore(&t->task_state_lock, flags);
1475 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1476 "task 0x%p done with io_status 0x%x resp 0x%x "
1477 "stat 0x%x but aborted by upper layer!\n",
1478 t, status, ts->resp, ts->stat));
1479 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1480 } else {
1481 spin_unlock_irqrestore(&t->task_state_lock, flags);
1482 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1483 mb();/* in order to force CPU ordering */
1484 t->task_done(t);
1485 }
1486 }
1487
1488 /*See the comments for mpi_ssp_completion */
1489 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1490 {
1491 struct sas_task *t;
1492 unsigned long flags;
1493 struct task_status_struct *ts;
1494 struct pm8001_ccb_info *ccb;
1495 struct pm8001_device *pm8001_dev;
1496 struct ssp_event_resp *psspPayload =
1497 (struct ssp_event_resp *)(piomb + 4);
1498 u32 event = le32_to_cpu(psspPayload->event);
1499 u32 tag = le32_to_cpu(psspPayload->tag);
1500 u32 port_id = le32_to_cpu(psspPayload->port_id);
1501
1502 ccb = &pm8001_ha->ccb_info[tag];
1503 t = ccb->task;
1504 pm8001_dev = ccb->device;
1505 if (event)
1506 PM8001_FAIL_DBG(pm8001_ha,
1507 pm8001_printk("sas IO status 0x%x\n", event));
1508 if (unlikely(!t || !t->lldd_task || !t->dev))
1509 return;
1510 ts = &t->task_status;
1511 PM8001_IO_DBG(pm8001_ha,
1512 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1513 port_id, tag, event));
1514 switch (event) {
1515 case IO_OVERFLOW:
1516 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1517 ts->resp = SAS_TASK_COMPLETE;
1518 ts->stat = SAS_DATA_OVERRUN;
1519 ts->residual = 0;
1520 if (pm8001_dev)
1521 pm8001_dev->running_req--;
1522 break;
1523 case IO_XFER_ERROR_BREAK:
1524 PM8001_IO_DBG(pm8001_ha,
1525 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1526 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1527 return;
1528 case IO_XFER_ERROR_PHY_NOT_READY:
1529 PM8001_IO_DBG(pm8001_ha,
1530 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1531 ts->resp = SAS_TASK_COMPLETE;
1532 ts->stat = SAS_OPEN_REJECT;
1533 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1534 break;
1535 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1536 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1537 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1538 ts->resp = SAS_TASK_COMPLETE;
1539 ts->stat = SAS_OPEN_REJECT;
1540 ts->open_rej_reason = SAS_OREJ_EPROTO;
1541 break;
1542 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1543 PM8001_IO_DBG(pm8001_ha,
1544 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1545 ts->resp = SAS_TASK_COMPLETE;
1546 ts->stat = SAS_OPEN_REJECT;
1547 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1548 break;
1549 case IO_OPEN_CNX_ERROR_BREAK:
1550 PM8001_IO_DBG(pm8001_ha,
1551 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1552 ts->resp = SAS_TASK_COMPLETE;
1553 ts->stat = SAS_OPEN_REJECT;
1554 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1555 break;
1556 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1557 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1558 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1559 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1560 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1561 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1562 PM8001_IO_DBG(pm8001_ha,
1563 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1564 ts->resp = SAS_TASK_COMPLETE;
1565 ts->stat = SAS_OPEN_REJECT;
1566 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1567 if (!t->uldd_task)
1568 pm8001_handle_event(pm8001_ha,
1569 pm8001_dev,
1570 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1571 break;
1572 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1573 PM8001_IO_DBG(pm8001_ha,
1574 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1575 ts->resp = SAS_TASK_COMPLETE;
1576 ts->stat = SAS_OPEN_REJECT;
1577 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1578 break;
1579 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1580 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1581 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1582 ts->resp = SAS_TASK_COMPLETE;
1583 ts->stat = SAS_OPEN_REJECT;
1584 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1585 break;
1586 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1587 PM8001_IO_DBG(pm8001_ha,
1588 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1589 ts->resp = SAS_TASK_COMPLETE;
1590 ts->stat = SAS_OPEN_REJECT;
1591 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1592 break;
1593 case IO_XFER_ERROR_NAK_RECEIVED:
1594 PM8001_IO_DBG(pm8001_ha,
1595 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1596 ts->resp = SAS_TASK_COMPLETE;
1597 ts->stat = SAS_OPEN_REJECT;
1598 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1599 break;
1600 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1601 PM8001_IO_DBG(pm8001_ha,
1602 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1603 ts->resp = SAS_TASK_COMPLETE;
1604 ts->stat = SAS_NAK_R_ERR;
1605 break;
1606 case IO_XFER_OPEN_RETRY_TIMEOUT:
1607 PM8001_IO_DBG(pm8001_ha,
1608 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1609 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1610 return;
1611 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1612 PM8001_IO_DBG(pm8001_ha,
1613 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1614 ts->resp = SAS_TASK_COMPLETE;
1615 ts->stat = SAS_DATA_OVERRUN;
1616 break;
1617 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1618 PM8001_IO_DBG(pm8001_ha,
1619 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1620 ts->resp = SAS_TASK_COMPLETE;
1621 ts->stat = SAS_DATA_OVERRUN;
1622 break;
1623 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1624 PM8001_IO_DBG(pm8001_ha,
1625 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1626 ts->resp = SAS_TASK_COMPLETE;
1627 ts->stat = SAS_DATA_OVERRUN;
1628 break;
1629 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1630 PM8001_IO_DBG(pm8001_ha,
1631 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1632 ts->resp = SAS_TASK_COMPLETE;
1633 ts->stat = SAS_DATA_OVERRUN;
1634 break;
1635 case IO_XFER_ERROR_OFFSET_MISMATCH:
1636 PM8001_IO_DBG(pm8001_ha,
1637 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1638 ts->resp = SAS_TASK_COMPLETE;
1639 ts->stat = SAS_DATA_OVERRUN;
1640 break;
1641 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1642 PM8001_IO_DBG(pm8001_ha,
1643 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1644 ts->resp = SAS_TASK_COMPLETE;
1645 ts->stat = SAS_DATA_OVERRUN;
1646 break;
1647 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1648 PM8001_IO_DBG(pm8001_ha,
1649 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1650 /* TBC: used default set values */
1651 ts->resp = SAS_TASK_COMPLETE;
1652 ts->stat = SAS_DATA_OVERRUN;
1653 break;
1654 case IO_XFER_CMD_FRAME_ISSUED:
1655 PM8001_IO_DBG(pm8001_ha,
1656 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1657 return;
1658 default:
1659 PM8001_IO_DBG(pm8001_ha,
1660 pm8001_printk("Unknown status 0x%x\n", event));
1661 /* not allowed case. Therefore, return failed status */
1662 ts->resp = SAS_TASK_COMPLETE;
1663 ts->stat = SAS_DATA_OVERRUN;
1664 break;
1665 }
1666 spin_lock_irqsave(&t->task_state_lock, flags);
1667 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1668 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1669 t->task_state_flags |= SAS_TASK_STATE_DONE;
1670 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1671 spin_unlock_irqrestore(&t->task_state_lock, flags);
1672 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1673 "task 0x%p done with event 0x%x resp 0x%x "
1674 "stat 0x%x but aborted by upper layer!\n",
1675 t, event, ts->resp, ts->stat));
1676 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1677 } else {
1678 spin_unlock_irqrestore(&t->task_state_lock, flags);
1679 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1680 mb();/* in order to force CPU ordering */
1681 t->task_done(t);
1682 }
1683 }
1684
1685 /*See the comments for mpi_ssp_completion */
1686 static void
1687 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1688 {
1689 struct sas_task *t;
1690 struct pm8001_ccb_info *ccb;
1691 u32 param;
1692 u32 status;
1693 u32 tag;
1694 struct sata_completion_resp *psataPayload;
1695 struct task_status_struct *ts;
1696 struct ata_task_resp *resp ;
1697 u32 *sata_resp;
1698 struct pm8001_device *pm8001_dev;
1699 unsigned long flags;
1700
1701 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1702 status = le32_to_cpu(psataPayload->status);
1703 tag = le32_to_cpu(psataPayload->tag);
1704
1705 if (!tag) {
1706 PM8001_FAIL_DBG(pm8001_ha,
1707 pm8001_printk("tag null\n"));
1708 return;
1709 }
1710 ccb = &pm8001_ha->ccb_info[tag];
1711 param = le32_to_cpu(psataPayload->param);
1712 if (ccb) {
1713 t = ccb->task;
1714 pm8001_dev = ccb->device;
1715 } else {
1716 PM8001_FAIL_DBG(pm8001_ha,
1717 pm8001_printk("ccb null\n"));
1718 return;
1719 }
1720
1721 if (t) {
1722 if (t->dev && (t->dev->lldd_dev))
1723 pm8001_dev = t->dev->lldd_dev;
1724 } else {
1725 PM8001_FAIL_DBG(pm8001_ha,
1726 pm8001_printk("task null\n"));
1727 return;
1728 }
1729
1730 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1731 && unlikely(!t || !t->lldd_task || !t->dev)) {
1732 PM8001_FAIL_DBG(pm8001_ha,
1733 pm8001_printk("task or dev null\n"));
1734 return;
1735 }
1736
1737 ts = &t->task_status;
1738 if (!ts) {
1739 PM8001_FAIL_DBG(pm8001_ha,
1740 pm8001_printk("ts null\n"));
1741 return;
1742 }
1743
1744 switch (status) {
1745 case IO_SUCCESS:
1746 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1747 if (param == 0) {
1748 ts->resp = SAS_TASK_COMPLETE;
1749 ts->stat = SAM_STAT_GOOD;
1750 /* check if response is for SEND READ LOG */
1751 if (pm8001_dev &&
1752 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
1753 /* set new bit for abort_all */
1754 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
1755 /* clear bit for read log */
1756 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
1757 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
1758 /* Free the tag */
1759 pm8001_tag_free(pm8001_ha, tag);
1760 sas_free_task(t);
1761 return;
1762 }
1763 } else {
1764 u8 len;
1765 ts->resp = SAS_TASK_COMPLETE;
1766 ts->stat = SAS_PROTO_RESPONSE;
1767 ts->residual = param;
1768 PM8001_IO_DBG(pm8001_ha,
1769 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1770 param));
1771 sata_resp = &psataPayload->sata_resp[0];
1772 resp = (struct ata_task_resp *)ts->buf;
1773 if (t->ata_task.dma_xfer == 0 &&
1774 t->data_dir == PCI_DMA_FROMDEVICE) {
1775 len = sizeof(struct pio_setup_fis);
1776 PM8001_IO_DBG(pm8001_ha,
1777 pm8001_printk("PIO read len = %d\n", len));
1778 } else if (t->ata_task.use_ncq) {
1779 len = sizeof(struct set_dev_bits_fis);
1780 PM8001_IO_DBG(pm8001_ha,
1781 pm8001_printk("FPDMA len = %d\n", len));
1782 } else {
1783 len = sizeof(struct dev_to_host_fis);
1784 PM8001_IO_DBG(pm8001_ha,
1785 pm8001_printk("other len = %d\n", len));
1786 }
1787 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1788 resp->frame_len = len;
1789 memcpy(&resp->ending_fis[0], sata_resp, len);
1790 ts->buf_valid_size = sizeof(*resp);
1791 } else
1792 PM8001_IO_DBG(pm8001_ha,
1793 pm8001_printk("response to large\n"));
1794 }
1795 if (pm8001_dev)
1796 pm8001_dev->running_req--;
1797 break;
1798 case IO_ABORTED:
1799 PM8001_IO_DBG(pm8001_ha,
1800 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1801 ts->resp = SAS_TASK_COMPLETE;
1802 ts->stat = SAS_ABORTED_TASK;
1803 if (pm8001_dev)
1804 pm8001_dev->running_req--;
1805 break;
1806 /* following cases are to do cases */
1807 case IO_UNDERFLOW:
1808 /* SATA Completion with error */
1809 PM8001_IO_DBG(pm8001_ha,
1810 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1811 ts->resp = SAS_TASK_COMPLETE;
1812 ts->stat = SAS_DATA_UNDERRUN;
1813 ts->residual = param;
1814 if (pm8001_dev)
1815 pm8001_dev->running_req--;
1816 break;
1817 case IO_NO_DEVICE:
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("IO_NO_DEVICE\n"));
1820 ts->resp = SAS_TASK_UNDELIVERED;
1821 ts->stat = SAS_PHY_DOWN;
1822 break;
1823 case IO_XFER_ERROR_BREAK:
1824 PM8001_IO_DBG(pm8001_ha,
1825 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1826 ts->resp = SAS_TASK_COMPLETE;
1827 ts->stat = SAS_INTERRUPTED;
1828 break;
1829 case IO_XFER_ERROR_PHY_NOT_READY:
1830 PM8001_IO_DBG(pm8001_ha,
1831 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1832 ts->resp = SAS_TASK_COMPLETE;
1833 ts->stat = SAS_OPEN_REJECT;
1834 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1835 break;
1836 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1837 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1838 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1839 ts->resp = SAS_TASK_COMPLETE;
1840 ts->stat = SAS_OPEN_REJECT;
1841 ts->open_rej_reason = SAS_OREJ_EPROTO;
1842 break;
1843 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1844 PM8001_IO_DBG(pm8001_ha,
1845 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1846 ts->resp = SAS_TASK_COMPLETE;
1847 ts->stat = SAS_OPEN_REJECT;
1848 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1849 break;
1850 case IO_OPEN_CNX_ERROR_BREAK:
1851 PM8001_IO_DBG(pm8001_ha,
1852 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1853 ts->resp = SAS_TASK_COMPLETE;
1854 ts->stat = SAS_OPEN_REJECT;
1855 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1856 break;
1857 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1858 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1859 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1860 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1861 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1862 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1863 PM8001_IO_DBG(pm8001_ha,
1864 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1865 ts->resp = SAS_TASK_COMPLETE;
1866 ts->stat = SAS_DEV_NO_RESPONSE;
1867 if (!t->uldd_task) {
1868 pm8001_handle_event(pm8001_ha,
1869 pm8001_dev,
1870 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1871 ts->resp = SAS_TASK_UNDELIVERED;
1872 ts->stat = SAS_QUEUE_FULL;
1873 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1874 mb();/*in order to force CPU ordering*/
1875 spin_unlock_irq(&pm8001_ha->lock);
1876 t->task_done(t);
1877 spin_lock_irq(&pm8001_ha->lock);
1878 return;
1879 }
1880 break;
1881 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1882 PM8001_IO_DBG(pm8001_ha,
1883 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1884 ts->resp = SAS_TASK_UNDELIVERED;
1885 ts->stat = SAS_OPEN_REJECT;
1886 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1887 if (!t->uldd_task) {
1888 pm8001_handle_event(pm8001_ha,
1889 pm8001_dev,
1890 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1891 ts->resp = SAS_TASK_UNDELIVERED;
1892 ts->stat = SAS_QUEUE_FULL;
1893 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1894 mb();/*ditto*/
1895 spin_unlock_irq(&pm8001_ha->lock);
1896 t->task_done(t);
1897 spin_lock_irq(&pm8001_ha->lock);
1898 return;
1899 }
1900 break;
1901 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1902 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1903 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1904 ts->resp = SAS_TASK_COMPLETE;
1905 ts->stat = SAS_OPEN_REJECT;
1906 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1907 break;
1908 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1909 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1910 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1911 ts->resp = SAS_TASK_COMPLETE;
1912 ts->stat = SAS_DEV_NO_RESPONSE;
1913 if (!t->uldd_task) {
1914 pm8001_handle_event(pm8001_ha,
1915 pm8001_dev,
1916 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1917 ts->resp = SAS_TASK_UNDELIVERED;
1918 ts->stat = SAS_QUEUE_FULL;
1919 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1920 mb();/* ditto*/
1921 spin_unlock_irq(&pm8001_ha->lock);
1922 t->task_done(t);
1923 spin_lock_irq(&pm8001_ha->lock);
1924 return;
1925 }
1926 break;
1927 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1928 PM8001_IO_DBG(pm8001_ha,
1929 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1930 ts->resp = SAS_TASK_COMPLETE;
1931 ts->stat = SAS_OPEN_REJECT;
1932 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1933 break;
1934 case IO_XFER_ERROR_NAK_RECEIVED:
1935 PM8001_IO_DBG(pm8001_ha,
1936 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1937 ts->resp = SAS_TASK_COMPLETE;
1938 ts->stat = SAS_NAK_R_ERR;
1939 break;
1940 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1941 PM8001_IO_DBG(pm8001_ha,
1942 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1943 ts->resp = SAS_TASK_COMPLETE;
1944 ts->stat = SAS_NAK_R_ERR;
1945 break;
1946 case IO_XFER_ERROR_DMA:
1947 PM8001_IO_DBG(pm8001_ha,
1948 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1949 ts->resp = SAS_TASK_COMPLETE;
1950 ts->stat = SAS_ABORTED_TASK;
1951 break;
1952 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
1953 PM8001_IO_DBG(pm8001_ha,
1954 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
1955 ts->resp = SAS_TASK_UNDELIVERED;
1956 ts->stat = SAS_DEV_NO_RESPONSE;
1957 break;
1958 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
1959 PM8001_IO_DBG(pm8001_ha,
1960 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_DATA_UNDERRUN;
1963 break;
1964 case IO_XFER_OPEN_RETRY_TIMEOUT:
1965 PM8001_IO_DBG(pm8001_ha,
1966 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1967 ts->resp = SAS_TASK_COMPLETE;
1968 ts->stat = SAS_OPEN_TO;
1969 break;
1970 case IO_PORT_IN_RESET:
1971 PM8001_IO_DBG(pm8001_ha,
1972 pm8001_printk("IO_PORT_IN_RESET\n"));
1973 ts->resp = SAS_TASK_COMPLETE;
1974 ts->stat = SAS_DEV_NO_RESPONSE;
1975 break;
1976 case IO_DS_NON_OPERATIONAL:
1977 PM8001_IO_DBG(pm8001_ha,
1978 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1979 ts->resp = SAS_TASK_COMPLETE;
1980 ts->stat = SAS_DEV_NO_RESPONSE;
1981 if (!t->uldd_task) {
1982 pm8001_handle_event(pm8001_ha, pm8001_dev,
1983 IO_DS_NON_OPERATIONAL);
1984 ts->resp = SAS_TASK_UNDELIVERED;
1985 ts->stat = SAS_QUEUE_FULL;
1986 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1987 mb();/*ditto*/
1988 spin_unlock_irq(&pm8001_ha->lock);
1989 t->task_done(t);
1990 spin_lock_irq(&pm8001_ha->lock);
1991 return;
1992 }
1993 break;
1994 case IO_DS_IN_RECOVERY:
1995 PM8001_IO_DBG(pm8001_ha,
1996 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1997 ts->resp = SAS_TASK_COMPLETE;
1998 ts->stat = SAS_DEV_NO_RESPONSE;
1999 break;
2000 case IO_DS_IN_ERROR:
2001 PM8001_IO_DBG(pm8001_ha,
2002 pm8001_printk("IO_DS_IN_ERROR\n"));
2003 ts->resp = SAS_TASK_COMPLETE;
2004 ts->stat = SAS_DEV_NO_RESPONSE;
2005 if (!t->uldd_task) {
2006 pm8001_handle_event(pm8001_ha, pm8001_dev,
2007 IO_DS_IN_ERROR);
2008 ts->resp = SAS_TASK_UNDELIVERED;
2009 ts->stat = SAS_QUEUE_FULL;
2010 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2011 mb();/*ditto*/
2012 spin_unlock_irq(&pm8001_ha->lock);
2013 t->task_done(t);
2014 spin_lock_irq(&pm8001_ha->lock);
2015 return;
2016 }
2017 break;
2018 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2019 PM8001_IO_DBG(pm8001_ha,
2020 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2021 ts->resp = SAS_TASK_COMPLETE;
2022 ts->stat = SAS_OPEN_REJECT;
2023 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2024 default:
2025 PM8001_IO_DBG(pm8001_ha,
2026 pm8001_printk("Unknown status 0x%x\n", status));
2027 /* not allowed case. Therefore, return failed status */
2028 ts->resp = SAS_TASK_COMPLETE;
2029 ts->stat = SAS_DEV_NO_RESPONSE;
2030 break;
2031 }
2032 spin_lock_irqsave(&t->task_state_lock, flags);
2033 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2034 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2035 t->task_state_flags |= SAS_TASK_STATE_DONE;
2036 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2037 spin_unlock_irqrestore(&t->task_state_lock, flags);
2038 PM8001_FAIL_DBG(pm8001_ha,
2039 pm8001_printk("task 0x%p done with io_status 0x%x"
2040 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2041 t, status, ts->resp, ts->stat));
2042 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2043 } else if (t->uldd_task) {
2044 spin_unlock_irqrestore(&t->task_state_lock, flags);
2045 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2046 mb();/* ditto */
2047 spin_unlock_irq(&pm8001_ha->lock);
2048 t->task_done(t);
2049 spin_lock_irq(&pm8001_ha->lock);
2050 } else if (!t->uldd_task) {
2051 spin_unlock_irqrestore(&t->task_state_lock, flags);
2052 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2053 mb();/*ditto*/
2054 spin_unlock_irq(&pm8001_ha->lock);
2055 t->task_done(t);
2056 spin_lock_irq(&pm8001_ha->lock);
2057 }
2058 }
2059
2060 /*See the comments for mpi_ssp_completion */
2061 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2062 {
2063 struct sas_task *t;
2064 struct task_status_struct *ts;
2065 struct pm8001_ccb_info *ccb;
2066 struct pm8001_device *pm8001_dev;
2067 struct sata_event_resp *psataPayload =
2068 (struct sata_event_resp *)(piomb + 4);
2069 u32 event = le32_to_cpu(psataPayload->event);
2070 u32 tag = le32_to_cpu(psataPayload->tag);
2071 u32 port_id = le32_to_cpu(psataPayload->port_id);
2072 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2073 unsigned long flags;
2074
2075 ccb = &pm8001_ha->ccb_info[tag];
2076
2077 if (ccb) {
2078 t = ccb->task;
2079 pm8001_dev = ccb->device;
2080 } else {
2081 PM8001_FAIL_DBG(pm8001_ha,
2082 pm8001_printk("No CCB !!!. returning\n"));
2083 return;
2084 }
2085 if (event)
2086 PM8001_FAIL_DBG(pm8001_ha,
2087 pm8001_printk("SATA EVENT 0x%x\n", event));
2088
2089 /* Check if this is NCQ error */
2090 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2091 /* find device using device id */
2092 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2093 /* send read log extension */
2094 if (pm8001_dev)
2095 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2096 return;
2097 }
2098
2099 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2100 PM8001_FAIL_DBG(pm8001_ha,
2101 pm8001_printk("task or dev null\n"));
2102 return;
2103 }
2104
2105 ts = &t->task_status;
2106 PM8001_IO_DBG(pm8001_ha,
2107 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2108 port_id, tag, event));
2109 switch (event) {
2110 case IO_OVERFLOW:
2111 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2112 ts->resp = SAS_TASK_COMPLETE;
2113 ts->stat = SAS_DATA_OVERRUN;
2114 ts->residual = 0;
2115 if (pm8001_dev)
2116 pm8001_dev->running_req--;
2117 break;
2118 case IO_XFER_ERROR_BREAK:
2119 PM8001_IO_DBG(pm8001_ha,
2120 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2121 ts->resp = SAS_TASK_COMPLETE;
2122 ts->stat = SAS_INTERRUPTED;
2123 break;
2124 case IO_XFER_ERROR_PHY_NOT_READY:
2125 PM8001_IO_DBG(pm8001_ha,
2126 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2127 ts->resp = SAS_TASK_COMPLETE;
2128 ts->stat = SAS_OPEN_REJECT;
2129 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2130 break;
2131 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2132 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2133 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2134 ts->resp = SAS_TASK_COMPLETE;
2135 ts->stat = SAS_OPEN_REJECT;
2136 ts->open_rej_reason = SAS_OREJ_EPROTO;
2137 break;
2138 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2139 PM8001_IO_DBG(pm8001_ha,
2140 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2141 ts->resp = SAS_TASK_COMPLETE;
2142 ts->stat = SAS_OPEN_REJECT;
2143 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2144 break;
2145 case IO_OPEN_CNX_ERROR_BREAK:
2146 PM8001_IO_DBG(pm8001_ha,
2147 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2148 ts->resp = SAS_TASK_COMPLETE;
2149 ts->stat = SAS_OPEN_REJECT;
2150 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2151 break;
2152 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2153 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2154 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2155 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2156 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2157 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2158 PM8001_FAIL_DBG(pm8001_ha,
2159 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2160 ts->resp = SAS_TASK_UNDELIVERED;
2161 ts->stat = SAS_DEV_NO_RESPONSE;
2162 if (!t->uldd_task) {
2163 pm8001_handle_event(pm8001_ha,
2164 pm8001_dev,
2165 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2166 ts->resp = SAS_TASK_COMPLETE;
2167 ts->stat = SAS_QUEUE_FULL;
2168 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2169 mb();/*ditto*/
2170 spin_unlock_irq(&pm8001_ha->lock);
2171 t->task_done(t);
2172 spin_lock_irq(&pm8001_ha->lock);
2173 return;
2174 }
2175 break;
2176 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2177 PM8001_IO_DBG(pm8001_ha,
2178 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2179 ts->resp = SAS_TASK_UNDELIVERED;
2180 ts->stat = SAS_OPEN_REJECT;
2181 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2182 break;
2183 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2184 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2185 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2186 ts->resp = SAS_TASK_COMPLETE;
2187 ts->stat = SAS_OPEN_REJECT;
2188 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2189 break;
2190 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2191 PM8001_IO_DBG(pm8001_ha,
2192 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2193 ts->resp = SAS_TASK_COMPLETE;
2194 ts->stat = SAS_OPEN_REJECT;
2195 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2196 break;
2197 case IO_XFER_ERROR_NAK_RECEIVED:
2198 PM8001_IO_DBG(pm8001_ha,
2199 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2200 ts->resp = SAS_TASK_COMPLETE;
2201 ts->stat = SAS_NAK_R_ERR;
2202 break;
2203 case IO_XFER_ERROR_PEER_ABORTED:
2204 PM8001_IO_DBG(pm8001_ha,
2205 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2206 ts->resp = SAS_TASK_COMPLETE;
2207 ts->stat = SAS_NAK_R_ERR;
2208 break;
2209 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2210 PM8001_IO_DBG(pm8001_ha,
2211 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_DATA_UNDERRUN;
2214 break;
2215 case IO_XFER_OPEN_RETRY_TIMEOUT:
2216 PM8001_IO_DBG(pm8001_ha,
2217 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2218 ts->resp = SAS_TASK_COMPLETE;
2219 ts->stat = SAS_OPEN_TO;
2220 break;
2221 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2222 PM8001_IO_DBG(pm8001_ha,
2223 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2224 ts->resp = SAS_TASK_COMPLETE;
2225 ts->stat = SAS_OPEN_TO;
2226 break;
2227 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2228 PM8001_IO_DBG(pm8001_ha,
2229 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2230 ts->resp = SAS_TASK_COMPLETE;
2231 ts->stat = SAS_OPEN_TO;
2232 break;
2233 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2234 PM8001_IO_DBG(pm8001_ha,
2235 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2236 ts->resp = SAS_TASK_COMPLETE;
2237 ts->stat = SAS_OPEN_TO;
2238 break;
2239 case IO_XFER_ERROR_OFFSET_MISMATCH:
2240 PM8001_IO_DBG(pm8001_ha,
2241 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2242 ts->resp = SAS_TASK_COMPLETE;
2243 ts->stat = SAS_OPEN_TO;
2244 break;
2245 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2246 PM8001_IO_DBG(pm8001_ha,
2247 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2248 ts->resp = SAS_TASK_COMPLETE;
2249 ts->stat = SAS_OPEN_TO;
2250 break;
2251 case IO_XFER_CMD_FRAME_ISSUED:
2252 PM8001_IO_DBG(pm8001_ha,
2253 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2254 break;
2255 case IO_XFER_PIO_SETUP_ERROR:
2256 PM8001_IO_DBG(pm8001_ha,
2257 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2258 ts->resp = SAS_TASK_COMPLETE;
2259 ts->stat = SAS_OPEN_TO;
2260 break;
2261 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2262 PM8001_FAIL_DBG(pm8001_ha,
2263 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2264 /* TBC: used default set values */
2265 ts->resp = SAS_TASK_COMPLETE;
2266 ts->stat = SAS_OPEN_TO;
2267 break;
2268 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2269 PM8001_FAIL_DBG(pm8001_ha,
2270 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2271 /* TBC: used default set values */
2272 ts->resp = SAS_TASK_COMPLETE;
2273 ts->stat = SAS_OPEN_TO;
2274 break;
2275 default:
2276 PM8001_IO_DBG(pm8001_ha,
2277 pm8001_printk("Unknown status 0x%x\n", event));
2278 /* not allowed case. Therefore, return failed status */
2279 ts->resp = SAS_TASK_COMPLETE;
2280 ts->stat = SAS_OPEN_TO;
2281 break;
2282 }
2283 spin_lock_irqsave(&t->task_state_lock, flags);
2284 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2285 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2286 t->task_state_flags |= SAS_TASK_STATE_DONE;
2287 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2288 spin_unlock_irqrestore(&t->task_state_lock, flags);
2289 PM8001_FAIL_DBG(pm8001_ha,
2290 pm8001_printk("task 0x%p done with io_status 0x%x"
2291 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2292 t, event, ts->resp, ts->stat));
2293 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2294 } else if (t->uldd_task) {
2295 spin_unlock_irqrestore(&t->task_state_lock, flags);
2296 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2297 mb();/* ditto */
2298 spin_unlock_irq(&pm8001_ha->lock);
2299 t->task_done(t);
2300 spin_lock_irq(&pm8001_ha->lock);
2301 } else if (!t->uldd_task) {
2302 spin_unlock_irqrestore(&t->task_state_lock, flags);
2303 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2304 mb();/*ditto*/
2305 spin_unlock_irq(&pm8001_ha->lock);
2306 t->task_done(t);
2307 spin_lock_irq(&pm8001_ha->lock);
2308 }
2309 }
2310
2311 /*See the comments for mpi_ssp_completion */
2312 static void
2313 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2314 {
2315 u32 param, i;
2316 struct sas_task *t;
2317 struct pm8001_ccb_info *ccb;
2318 unsigned long flags;
2319 u32 status;
2320 u32 tag;
2321 struct smp_completion_resp *psmpPayload;
2322 struct task_status_struct *ts;
2323 struct pm8001_device *pm8001_dev;
2324 char *pdma_respaddr = NULL;
2325
2326 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2327 status = le32_to_cpu(psmpPayload->status);
2328 tag = le32_to_cpu(psmpPayload->tag);
2329
2330 ccb = &pm8001_ha->ccb_info[tag];
2331 param = le32_to_cpu(psmpPayload->param);
2332 t = ccb->task;
2333 ts = &t->task_status;
2334 pm8001_dev = ccb->device;
2335 if (status)
2336 PM8001_FAIL_DBG(pm8001_ha,
2337 pm8001_printk("smp IO status 0x%x\n", status));
2338 if (unlikely(!t || !t->lldd_task || !t->dev))
2339 return;
2340
2341 switch (status) {
2342
2343 case IO_SUCCESS:
2344 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2345 ts->resp = SAS_TASK_COMPLETE;
2346 ts->stat = SAM_STAT_GOOD;
2347 if (pm8001_dev)
2348 pm8001_dev->running_req--;
2349 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2350 PM8001_IO_DBG(pm8001_ha,
2351 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2352 param));
2353 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2354 ((u64)sg_dma_address
2355 (&t->smp_task.smp_resp))));
2356 for (i = 0; i < param; i++) {
2357 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2358 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2359 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2360 i, *(pdma_respaddr+i),
2361 psmpPayload->_r_a[i]));
2362 }
2363 }
2364 break;
2365 case IO_ABORTED:
2366 PM8001_IO_DBG(pm8001_ha,
2367 pm8001_printk("IO_ABORTED IOMB\n"));
2368 ts->resp = SAS_TASK_COMPLETE;
2369 ts->stat = SAS_ABORTED_TASK;
2370 if (pm8001_dev)
2371 pm8001_dev->running_req--;
2372 break;
2373 case IO_OVERFLOW:
2374 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2375 ts->resp = SAS_TASK_COMPLETE;
2376 ts->stat = SAS_DATA_OVERRUN;
2377 ts->residual = 0;
2378 if (pm8001_dev)
2379 pm8001_dev->running_req--;
2380 break;
2381 case IO_NO_DEVICE:
2382 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2383 ts->resp = SAS_TASK_COMPLETE;
2384 ts->stat = SAS_PHY_DOWN;
2385 break;
2386 case IO_ERROR_HW_TIMEOUT:
2387 PM8001_IO_DBG(pm8001_ha,
2388 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2389 ts->resp = SAS_TASK_COMPLETE;
2390 ts->stat = SAM_STAT_BUSY;
2391 break;
2392 case IO_XFER_ERROR_BREAK:
2393 PM8001_IO_DBG(pm8001_ha,
2394 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2395 ts->resp = SAS_TASK_COMPLETE;
2396 ts->stat = SAM_STAT_BUSY;
2397 break;
2398 case IO_XFER_ERROR_PHY_NOT_READY:
2399 PM8001_IO_DBG(pm8001_ha,
2400 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2401 ts->resp = SAS_TASK_COMPLETE;
2402 ts->stat = SAM_STAT_BUSY;
2403 break;
2404 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2405 PM8001_IO_DBG(pm8001_ha,
2406 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2407 ts->resp = SAS_TASK_COMPLETE;
2408 ts->stat = SAS_OPEN_REJECT;
2409 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2410 break;
2411 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2412 PM8001_IO_DBG(pm8001_ha,
2413 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2414 ts->resp = SAS_TASK_COMPLETE;
2415 ts->stat = SAS_OPEN_REJECT;
2416 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2417 break;
2418 case IO_OPEN_CNX_ERROR_BREAK:
2419 PM8001_IO_DBG(pm8001_ha,
2420 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2421 ts->resp = SAS_TASK_COMPLETE;
2422 ts->stat = SAS_OPEN_REJECT;
2423 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2424 break;
2425 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2426 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2427 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2428 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2429 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2430 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2431 PM8001_IO_DBG(pm8001_ha,
2432 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2433 ts->resp = SAS_TASK_COMPLETE;
2434 ts->stat = SAS_OPEN_REJECT;
2435 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2436 pm8001_handle_event(pm8001_ha,
2437 pm8001_dev,
2438 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2439 break;
2440 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2441 PM8001_IO_DBG(pm8001_ha,
2442 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2443 ts->resp = SAS_TASK_COMPLETE;
2444 ts->stat = SAS_OPEN_REJECT;
2445 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2446 break;
2447 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2448 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2449 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2450 ts->resp = SAS_TASK_COMPLETE;
2451 ts->stat = SAS_OPEN_REJECT;
2452 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2453 break;
2454 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2455 PM8001_IO_DBG(pm8001_ha,
2456 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2457 ts->resp = SAS_TASK_COMPLETE;
2458 ts->stat = SAS_OPEN_REJECT;
2459 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2460 break;
2461 case IO_XFER_ERROR_RX_FRAME:
2462 PM8001_IO_DBG(pm8001_ha,
2463 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2464 ts->resp = SAS_TASK_COMPLETE;
2465 ts->stat = SAS_DEV_NO_RESPONSE;
2466 break;
2467 case IO_XFER_OPEN_RETRY_TIMEOUT:
2468 PM8001_IO_DBG(pm8001_ha,
2469 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2470 ts->resp = SAS_TASK_COMPLETE;
2471 ts->stat = SAS_OPEN_REJECT;
2472 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2473 break;
2474 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2475 PM8001_IO_DBG(pm8001_ha,
2476 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2477 ts->resp = SAS_TASK_COMPLETE;
2478 ts->stat = SAS_QUEUE_FULL;
2479 break;
2480 case IO_PORT_IN_RESET:
2481 PM8001_IO_DBG(pm8001_ha,
2482 pm8001_printk("IO_PORT_IN_RESET\n"));
2483 ts->resp = SAS_TASK_COMPLETE;
2484 ts->stat = SAS_OPEN_REJECT;
2485 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2486 break;
2487 case IO_DS_NON_OPERATIONAL:
2488 PM8001_IO_DBG(pm8001_ha,
2489 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2490 ts->resp = SAS_TASK_COMPLETE;
2491 ts->stat = SAS_DEV_NO_RESPONSE;
2492 break;
2493 case IO_DS_IN_RECOVERY:
2494 PM8001_IO_DBG(pm8001_ha,
2495 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2496 ts->resp = SAS_TASK_COMPLETE;
2497 ts->stat = SAS_OPEN_REJECT;
2498 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2499 break;
2500 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2501 PM8001_IO_DBG(pm8001_ha,
2502 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2503 ts->resp = SAS_TASK_COMPLETE;
2504 ts->stat = SAS_OPEN_REJECT;
2505 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2506 break;
2507 default:
2508 PM8001_IO_DBG(pm8001_ha,
2509 pm8001_printk("Unknown status 0x%x\n", status));
2510 ts->resp = SAS_TASK_COMPLETE;
2511 ts->stat = SAS_DEV_NO_RESPONSE;
2512 /* not allowed case. Therefore, return failed status */
2513 break;
2514 }
2515 spin_lock_irqsave(&t->task_state_lock, flags);
2516 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2517 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2518 t->task_state_flags |= SAS_TASK_STATE_DONE;
2519 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2520 spin_unlock_irqrestore(&t->task_state_lock, flags);
2521 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2522 "task 0x%p done with io_status 0x%x resp 0x%x"
2523 "stat 0x%x but aborted by upper layer!\n",
2524 t, status, ts->resp, ts->stat));
2525 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2526 } else {
2527 spin_unlock_irqrestore(&t->task_state_lock, flags);
2528 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2529 mb();/* in order to force CPU ordering */
2530 t->task_done(t);
2531 }
2532 }
2533
2534 /**
2535 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2536 * @pm8001_ha: our hba card information
2537 * @Qnum: the outbound queue message number.
2538 * @SEA: source of event to ack
2539 * @port_id: port id.
2540 * @phyId: phy id.
2541 * @param0: parameter 0.
2542 * @param1: parameter 1.
2543 */
2544 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2545 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2546 {
2547 struct hw_event_ack_req payload;
2548 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2549
2550 struct inbound_queue_table *circularQ;
2551
2552 memset((u8 *)&payload, 0, sizeof(payload));
2553 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2554 payload.tag = cpu_to_le32(1);
2555 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2556 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2557 payload.param0 = cpu_to_le32(param0);
2558 payload.param1 = cpu_to_le32(param1);
2559 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2560 }
2561
2562 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2563 u32 phyId, u32 phy_op);
2564
2565 /**
2566 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2567 * @pm8001_ha: our hba card information
2568 * @piomb: IO message buffer
2569 */
2570 static void
2571 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2572 {
2573 struct hw_event_resp *pPayload =
2574 (struct hw_event_resp *)(piomb + 4);
2575 u32 lr_status_evt_portid =
2576 le32_to_cpu(pPayload->lr_status_evt_portid);
2577 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2578
2579 u8 link_rate =
2580 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2581 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2582 u8 phy_id =
2583 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2584 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2585
2586 struct pm8001_port *port = &pm8001_ha->port[port_id];
2587 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2588 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2589 unsigned long flags;
2590 u8 deviceType = pPayload->sas_identify.dev_type;
2591 port->port_state = portstate;
2592 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2593 "portid:%d; phyid:%d; linkrate:%d; "
2594 "portstate:%x; devicetype:%x\n",
2595 port_id, phy_id, link_rate, portstate, deviceType));
2596
2597 switch (deviceType) {
2598 case SAS_PHY_UNUSED:
2599 PM8001_MSG_DBG(pm8001_ha,
2600 pm8001_printk("device type no device.\n"));
2601 break;
2602 case SAS_END_DEVICE:
2603 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2604 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2605 PHY_NOTIFY_ENABLE_SPINUP);
2606 port->port_attached = 1;
2607 pm8001_get_lrate_mode(phy, link_rate);
2608 break;
2609 case SAS_EDGE_EXPANDER_DEVICE:
2610 PM8001_MSG_DBG(pm8001_ha,
2611 pm8001_printk("expander device.\n"));
2612 port->port_attached = 1;
2613 pm8001_get_lrate_mode(phy, link_rate);
2614 break;
2615 case SAS_FANOUT_EXPANDER_DEVICE:
2616 PM8001_MSG_DBG(pm8001_ha,
2617 pm8001_printk("fanout expander device.\n"));
2618 port->port_attached = 1;
2619 pm8001_get_lrate_mode(phy, link_rate);
2620 break;
2621 default:
2622 PM8001_MSG_DBG(pm8001_ha,
2623 pm8001_printk("unknown device type(%x)\n", deviceType));
2624 break;
2625 }
2626 phy->phy_type |= PORT_TYPE_SAS;
2627 phy->identify.device_type = deviceType;
2628 phy->phy_attached = 1;
2629 if (phy->identify.device_type == SAS_END_DEVICE)
2630 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2631 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2632 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2633 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2634 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2635 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2636 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2637 sizeof(struct sas_identify_frame)-4);
2638 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2639 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2640 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2641 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2642 mdelay(200);/*delay a moment to wait disk to spinup*/
2643 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2644 }
2645
2646 /**
2647 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2648 * @pm8001_ha: our hba card information
2649 * @piomb: IO message buffer
2650 */
2651 static void
2652 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2653 {
2654 struct hw_event_resp *pPayload =
2655 (struct hw_event_resp *)(piomb + 4);
2656 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2657 u32 lr_status_evt_portid =
2658 le32_to_cpu(pPayload->lr_status_evt_portid);
2659 u8 link_rate =
2660 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2661 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2662 u8 phy_id =
2663 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2664
2665 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2666
2667 struct pm8001_port *port = &pm8001_ha->port[port_id];
2668 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2669 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2670 unsigned long flags;
2671 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2672 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2673 port_id, phy_id, link_rate, portstate));
2674
2675 port->port_state = portstate;
2676 port->port_attached = 1;
2677 pm8001_get_lrate_mode(phy, link_rate);
2678 phy->phy_type |= PORT_TYPE_SATA;
2679 phy->phy_attached = 1;
2680 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2681 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2682 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2683 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2684 sizeof(struct dev_to_host_fis));
2685 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2686 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2687 phy->identify.device_type = SAS_SATA_DEV;
2688 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2689 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2690 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2691 }
2692
2693 /**
2694 * hw_event_phy_down -we should notify the libsas the phy is down.
2695 * @pm8001_ha: our hba card information
2696 * @piomb: IO message buffer
2697 */
2698 static void
2699 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2700 {
2701 struct hw_event_resp *pPayload =
2702 (struct hw_event_resp *)(piomb + 4);
2703
2704 u32 lr_status_evt_portid =
2705 le32_to_cpu(pPayload->lr_status_evt_portid);
2706 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2707 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2708 u8 phy_id =
2709 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2710 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2711
2712 struct pm8001_port *port = &pm8001_ha->port[port_id];
2713 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2714 port->port_state = portstate;
2715 phy->phy_type = 0;
2716 phy->identify.device_type = 0;
2717 phy->phy_attached = 0;
2718 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2719 switch (portstate) {
2720 case PORT_VALID:
2721 break;
2722 case PORT_INVALID:
2723 PM8001_MSG_DBG(pm8001_ha,
2724 pm8001_printk(" PortInvalid portID %d\n", port_id));
2725 PM8001_MSG_DBG(pm8001_ha,
2726 pm8001_printk(" Last phy Down and port invalid\n"));
2727 port->port_attached = 0;
2728 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2729 port_id, phy_id, 0, 0);
2730 break;
2731 case PORT_IN_RESET:
2732 PM8001_MSG_DBG(pm8001_ha,
2733 pm8001_printk(" Port In Reset portID %d\n", port_id));
2734 break;
2735 case PORT_NOT_ESTABLISHED:
2736 PM8001_MSG_DBG(pm8001_ha,
2737 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2738 port->port_attached = 0;
2739 break;
2740 case PORT_LOSTCOMM:
2741 PM8001_MSG_DBG(pm8001_ha,
2742 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2743 PM8001_MSG_DBG(pm8001_ha,
2744 pm8001_printk(" Last phy Down and port invalid\n"));
2745 port->port_attached = 0;
2746 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2747 port_id, phy_id, 0, 0);
2748 break;
2749 default:
2750 port->port_attached = 0;
2751 PM8001_MSG_DBG(pm8001_ha,
2752 pm8001_printk(" phy Down and(default) = 0x%x\n",
2753 portstate));
2754 break;
2755
2756 }
2757 }
2758
2759 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2760 {
2761 struct phy_start_resp *pPayload =
2762 (struct phy_start_resp *)(piomb + 4);
2763 u32 status =
2764 le32_to_cpu(pPayload->status);
2765 u32 phy_id =
2766 le32_to_cpu(pPayload->phyid);
2767 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2768
2769 PM8001_INIT_DBG(pm8001_ha,
2770 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2771 status, phy_id));
2772 if (status == 0) {
2773 phy->phy_state = 1;
2774 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2775 complete(phy->enable_completion);
2776 }
2777 return 0;
2778
2779 }
2780
2781 /**
2782 * mpi_thermal_hw_event -The hw event has come.
2783 * @pm8001_ha: our hba card information
2784 * @piomb: IO message buffer
2785 */
2786 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2787 {
2788 struct thermal_hw_event *pPayload =
2789 (struct thermal_hw_event *)(piomb + 4);
2790
2791 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2792 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2793
2794 if (thermal_event & 0x40) {
2795 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2796 "Thermal Event: Local high temperature violated!\n"));
2797 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2798 "Thermal Event: Measured local high temperature %d\n",
2799 ((rht_lht & 0xFF00) >> 8)));
2800 }
2801 if (thermal_event & 0x10) {
2802 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2803 "Thermal Event: Remote high temperature violated!\n"));
2804 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2805 "Thermal Event: Measured remote high temperature %d\n",
2806 ((rht_lht & 0xFF000000) >> 24)));
2807 }
2808 return 0;
2809 }
2810
2811 /**
2812 * mpi_hw_event -The hw event has come.
2813 * @pm8001_ha: our hba card information
2814 * @piomb: IO message buffer
2815 */
2816 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2817 {
2818 unsigned long flags;
2819 struct hw_event_resp *pPayload =
2820 (struct hw_event_resp *)(piomb + 4);
2821 u32 lr_status_evt_portid =
2822 le32_to_cpu(pPayload->lr_status_evt_portid);
2823 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2824 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2825 u8 phy_id =
2826 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2827 u16 eventType =
2828 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2829 u8 status =
2830 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2831
2832 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2833 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2834 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2835 PM8001_MSG_DBG(pm8001_ha,
2836 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2837 port_id, phy_id, eventType, status));
2838
2839 switch (eventType) {
2840
2841 case HW_EVENT_SAS_PHY_UP:
2842 PM8001_MSG_DBG(pm8001_ha,
2843 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2844 hw_event_sas_phy_up(pm8001_ha, piomb);
2845 break;
2846 case HW_EVENT_SATA_PHY_UP:
2847 PM8001_MSG_DBG(pm8001_ha,
2848 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2849 hw_event_sata_phy_up(pm8001_ha, piomb);
2850 break;
2851 case HW_EVENT_SATA_SPINUP_HOLD:
2852 PM8001_MSG_DBG(pm8001_ha,
2853 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2854 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2855 break;
2856 case HW_EVENT_PHY_DOWN:
2857 PM8001_MSG_DBG(pm8001_ha,
2858 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2859 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2860 phy->phy_attached = 0;
2861 phy->phy_state = 0;
2862 hw_event_phy_down(pm8001_ha, piomb);
2863 break;
2864 case HW_EVENT_PORT_INVALID:
2865 PM8001_MSG_DBG(pm8001_ha,
2866 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2867 sas_phy_disconnected(sas_phy);
2868 phy->phy_attached = 0;
2869 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2870 break;
2871 /* the broadcast change primitive received, tell the LIBSAS this event
2872 to revalidate the sas domain*/
2873 case HW_EVENT_BROADCAST_CHANGE:
2874 PM8001_MSG_DBG(pm8001_ha,
2875 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2876 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2877 port_id, phy_id, 1, 0);
2878 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2879 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2880 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2881 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2882 break;
2883 case HW_EVENT_PHY_ERROR:
2884 PM8001_MSG_DBG(pm8001_ha,
2885 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2886 sas_phy_disconnected(&phy->sas_phy);
2887 phy->phy_attached = 0;
2888 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2889 break;
2890 case HW_EVENT_BROADCAST_EXP:
2891 PM8001_MSG_DBG(pm8001_ha,
2892 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2893 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2894 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2895 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2896 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2897 break;
2898 case HW_EVENT_LINK_ERR_INVALID_DWORD:
2899 PM8001_MSG_DBG(pm8001_ha,
2900 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2901 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2902 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2903 sas_phy_disconnected(sas_phy);
2904 phy->phy_attached = 0;
2905 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2906 break;
2907 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2908 PM8001_MSG_DBG(pm8001_ha,
2909 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2910 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2911 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2912 port_id, phy_id, 0, 0);
2913 sas_phy_disconnected(sas_phy);
2914 phy->phy_attached = 0;
2915 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2916 break;
2917 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2918 PM8001_MSG_DBG(pm8001_ha,
2919 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
2920 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2921 HW_EVENT_LINK_ERR_CODE_VIOLATION,
2922 port_id, phy_id, 0, 0);
2923 sas_phy_disconnected(sas_phy);
2924 phy->phy_attached = 0;
2925 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2926 break;
2927 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
2928 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2929 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
2930 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2931 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
2932 port_id, phy_id, 0, 0);
2933 sas_phy_disconnected(sas_phy);
2934 phy->phy_attached = 0;
2935 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2936 break;
2937 case HW_EVENT_MALFUNCTION:
2938 PM8001_MSG_DBG(pm8001_ha,
2939 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
2940 break;
2941 case HW_EVENT_BROADCAST_SES:
2942 PM8001_MSG_DBG(pm8001_ha,
2943 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
2944 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2945 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
2946 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2947 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2948 break;
2949 case HW_EVENT_INBOUND_CRC_ERROR:
2950 PM8001_MSG_DBG(pm8001_ha,
2951 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
2952 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2953 HW_EVENT_INBOUND_CRC_ERROR,
2954 port_id, phy_id, 0, 0);
2955 break;
2956 case HW_EVENT_HARD_RESET_RECEIVED:
2957 PM8001_MSG_DBG(pm8001_ha,
2958 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
2959 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
2960 break;
2961 case HW_EVENT_ID_FRAME_TIMEOUT:
2962 PM8001_MSG_DBG(pm8001_ha,
2963 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
2964 sas_phy_disconnected(sas_phy);
2965 phy->phy_attached = 0;
2966 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2967 break;
2968 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
2969 PM8001_MSG_DBG(pm8001_ha,
2970 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
2971 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2972 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
2973 port_id, phy_id, 0, 0);
2974 sas_phy_disconnected(sas_phy);
2975 phy->phy_attached = 0;
2976 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2977 break;
2978 case HW_EVENT_PORT_RESET_TIMER_TMO:
2979 PM8001_MSG_DBG(pm8001_ha,
2980 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
2981 sas_phy_disconnected(sas_phy);
2982 phy->phy_attached = 0;
2983 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2984 break;
2985 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
2986 PM8001_MSG_DBG(pm8001_ha,
2987 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
2988 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2989 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
2990 port_id, phy_id, 0, 0);
2991 sas_phy_disconnected(sas_phy);
2992 phy->phy_attached = 0;
2993 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2994 break;
2995 case HW_EVENT_PORT_RECOVER:
2996 PM8001_MSG_DBG(pm8001_ha,
2997 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
2998 break;
2999 case HW_EVENT_PORT_RESET_COMPLETE:
3000 PM8001_MSG_DBG(pm8001_ha,
3001 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3002 break;
3003 case EVENT_BROADCAST_ASYNCH_EVENT:
3004 PM8001_MSG_DBG(pm8001_ha,
3005 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3006 break;
3007 default:
3008 PM8001_MSG_DBG(pm8001_ha,
3009 pm8001_printk("Unknown event type 0x%x\n", eventType));
3010 break;
3011 }
3012 return 0;
3013 }
3014
3015 /**
3016 * mpi_phy_stop_resp - SPCv specific
3017 * @pm8001_ha: our hba card information
3018 * @piomb: IO message buffer
3019 */
3020 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3021 {
3022 struct phy_stop_resp *pPayload =
3023 (struct phy_stop_resp *)(piomb + 4);
3024 u32 status =
3025 le32_to_cpu(pPayload->status);
3026 u32 phyid =
3027 le32_to_cpu(pPayload->phyid);
3028 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3029 PM8001_MSG_DBG(pm8001_ha,
3030 pm8001_printk("phy:0x%x status:0x%x\n",
3031 phyid, status));
3032 if (status == 0)
3033 phy->phy_state = 0;
3034 return 0;
3035 }
3036
3037 /**
3038 * mpi_set_controller_config_resp - SPCv specific
3039 * @pm8001_ha: our hba card information
3040 * @piomb: IO message buffer
3041 */
3042 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3043 void *piomb)
3044 {
3045 struct set_ctrl_cfg_resp *pPayload =
3046 (struct set_ctrl_cfg_resp *)(piomb + 4);
3047 u32 status = le32_to_cpu(pPayload->status);
3048 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3049
3050 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3051 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3052 status, err_qlfr_pgcd));
3053
3054 return 0;
3055 }
3056
3057 /**
3058 * mpi_get_controller_config_resp - SPCv specific
3059 * @pm8001_ha: our hba card information
3060 * @piomb: IO message buffer
3061 */
3062 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3063 void *piomb)
3064 {
3065 PM8001_MSG_DBG(pm8001_ha,
3066 pm8001_printk(" pm80xx_addition_functionality\n"));
3067
3068 return 0;
3069 }
3070
3071 /**
3072 * mpi_get_phy_profile_resp - SPCv specific
3073 * @pm8001_ha: our hba card information
3074 * @piomb: IO message buffer
3075 */
3076 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3077 void *piomb)
3078 {
3079 PM8001_MSG_DBG(pm8001_ha,
3080 pm8001_printk(" pm80xx_addition_functionality\n"));
3081
3082 return 0;
3083 }
3084
3085 /**
3086 * mpi_flash_op_ext_resp - SPCv specific
3087 * @pm8001_ha: our hba card information
3088 * @piomb: IO message buffer
3089 */
3090 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3091 {
3092 PM8001_MSG_DBG(pm8001_ha,
3093 pm8001_printk(" pm80xx_addition_functionality\n"));
3094
3095 return 0;
3096 }
3097
3098 /**
3099 * mpi_set_phy_profile_resp - SPCv specific
3100 * @pm8001_ha: our hba card information
3101 * @piomb: IO message buffer
3102 */
3103 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3104 void *piomb)
3105 {
3106 PM8001_MSG_DBG(pm8001_ha,
3107 pm8001_printk(" pm80xx_addition_functionality\n"));
3108
3109 return 0;
3110 }
3111
3112 /**
3113 * mpi_kek_management_resp - SPCv specific
3114 * @pm8001_ha: our hba card information
3115 * @piomb: IO message buffer
3116 */
3117 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3118 void *piomb)
3119 {
3120 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3121
3122 u32 status = le32_to_cpu(pPayload->status);
3123 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3124 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3125
3126 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3127 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3128 status, kidx_new_curr_ksop, err_qlfr));
3129
3130 return 0;
3131 }
3132
3133 /**
3134 * mpi_dek_management_resp - SPCv specific
3135 * @pm8001_ha: our hba card information
3136 * @piomb: IO message buffer
3137 */
3138 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3139 void *piomb)
3140 {
3141 PM8001_MSG_DBG(pm8001_ha,
3142 pm8001_printk(" pm80xx_addition_functionality\n"));
3143
3144 return 0;
3145 }
3146
3147 /**
3148 * ssp_coalesced_comp_resp - SPCv specific
3149 * @pm8001_ha: our hba card information
3150 * @piomb: IO message buffer
3151 */
3152 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3153 void *piomb)
3154 {
3155 PM8001_MSG_DBG(pm8001_ha,
3156 pm8001_printk(" pm80xx_addition_functionality\n"));
3157
3158 return 0;
3159 }
3160
3161 /**
3162 * process_one_iomb - process one outbound Queue memory block
3163 * @pm8001_ha: our hba card information
3164 * @piomb: IO message buffer
3165 */
3166 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3167 {
3168 __le32 pHeader = *(__le32 *)piomb;
3169 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3170
3171 switch (opc) {
3172 case OPC_OUB_ECHO:
3173 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3174 break;
3175 case OPC_OUB_HW_EVENT:
3176 PM8001_MSG_DBG(pm8001_ha,
3177 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3178 mpi_hw_event(pm8001_ha, piomb);
3179 break;
3180 case OPC_OUB_THERM_HW_EVENT:
3181 PM8001_MSG_DBG(pm8001_ha,
3182 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3183 mpi_thermal_hw_event(pm8001_ha, piomb);
3184 break;
3185 case OPC_OUB_SSP_COMP:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3188 mpi_ssp_completion(pm8001_ha, piomb);
3189 break;
3190 case OPC_OUB_SMP_COMP:
3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3193 mpi_smp_completion(pm8001_ha, piomb);
3194 break;
3195 case OPC_OUB_LOCAL_PHY_CNTRL:
3196 PM8001_MSG_DBG(pm8001_ha,
3197 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3198 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3199 break;
3200 case OPC_OUB_DEV_REGIST:
3201 PM8001_MSG_DBG(pm8001_ha,
3202 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3203 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3204 break;
3205 case OPC_OUB_DEREG_DEV:
3206 PM8001_MSG_DBG(pm8001_ha,
3207 pm8001_printk("unregister the device\n"));
3208 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3209 break;
3210 case OPC_OUB_GET_DEV_HANDLE:
3211 PM8001_MSG_DBG(pm8001_ha,
3212 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3213 break;
3214 case OPC_OUB_SATA_COMP:
3215 PM8001_MSG_DBG(pm8001_ha,
3216 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3217 mpi_sata_completion(pm8001_ha, piomb);
3218 break;
3219 case OPC_OUB_SATA_EVENT:
3220 PM8001_MSG_DBG(pm8001_ha,
3221 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3222 mpi_sata_event(pm8001_ha, piomb);
3223 break;
3224 case OPC_OUB_SSP_EVENT:
3225 PM8001_MSG_DBG(pm8001_ha,
3226 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3227 mpi_ssp_event(pm8001_ha, piomb);
3228 break;
3229 case OPC_OUB_DEV_HANDLE_ARRIV:
3230 PM8001_MSG_DBG(pm8001_ha,
3231 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3232 /*This is for target*/
3233 break;
3234 case OPC_OUB_SSP_RECV_EVENT:
3235 PM8001_MSG_DBG(pm8001_ha,
3236 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3237 /*This is for target*/
3238 break;
3239 case OPC_OUB_FW_FLASH_UPDATE:
3240 PM8001_MSG_DBG(pm8001_ha,
3241 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3242 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3243 break;
3244 case OPC_OUB_GPIO_RESPONSE:
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3247 break;
3248 case OPC_OUB_GPIO_EVENT:
3249 PM8001_MSG_DBG(pm8001_ha,
3250 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3251 break;
3252 case OPC_OUB_GENERAL_EVENT:
3253 PM8001_MSG_DBG(pm8001_ha,
3254 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3255 pm8001_mpi_general_event(pm8001_ha, piomb);
3256 break;
3257 case OPC_OUB_SSP_ABORT_RSP:
3258 PM8001_MSG_DBG(pm8001_ha,
3259 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3260 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3261 break;
3262 case OPC_OUB_SATA_ABORT_RSP:
3263 PM8001_MSG_DBG(pm8001_ha,
3264 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3265 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3266 break;
3267 case OPC_OUB_SAS_DIAG_MODE_START_END:
3268 PM8001_MSG_DBG(pm8001_ha,
3269 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3270 break;
3271 case OPC_OUB_SAS_DIAG_EXECUTE:
3272 PM8001_MSG_DBG(pm8001_ha,
3273 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3274 break;
3275 case OPC_OUB_GET_TIME_STAMP:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3278 break;
3279 case OPC_OUB_SAS_HW_EVENT_ACK:
3280 PM8001_MSG_DBG(pm8001_ha,
3281 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3282 break;
3283 case OPC_OUB_PORT_CONTROL:
3284 PM8001_MSG_DBG(pm8001_ha,
3285 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3286 break;
3287 case OPC_OUB_SMP_ABORT_RSP:
3288 PM8001_MSG_DBG(pm8001_ha,
3289 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3290 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3291 break;
3292 case OPC_OUB_GET_NVMD_DATA:
3293 PM8001_MSG_DBG(pm8001_ha,
3294 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3295 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3296 break;
3297 case OPC_OUB_SET_NVMD_DATA:
3298 PM8001_MSG_DBG(pm8001_ha,
3299 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3300 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3301 break;
3302 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3303 PM8001_MSG_DBG(pm8001_ha,
3304 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3305 break;
3306 case OPC_OUB_SET_DEVICE_STATE:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3309 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3310 break;
3311 case OPC_OUB_GET_DEVICE_STATE:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3314 break;
3315 case OPC_OUB_SET_DEV_INFO:
3316 PM8001_MSG_DBG(pm8001_ha,
3317 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3318 break;
3319 /* spcv specifc commands */
3320 case OPC_OUB_PHY_START_RESP:
3321 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3322 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3323 mpi_phy_start_resp(pm8001_ha, piomb);
3324 break;
3325 case OPC_OUB_PHY_STOP_RESP:
3326 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3327 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3328 mpi_phy_stop_resp(pm8001_ha, piomb);
3329 break;
3330 case OPC_OUB_SET_CONTROLLER_CONFIG:
3331 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3332 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3333 mpi_set_controller_config_resp(pm8001_ha, piomb);
3334 break;
3335 case OPC_OUB_GET_CONTROLLER_CONFIG:
3336 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3337 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3338 mpi_get_controller_config_resp(pm8001_ha, piomb);
3339 break;
3340 case OPC_OUB_GET_PHY_PROFILE:
3341 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3342 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3343 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3344 break;
3345 case OPC_OUB_FLASH_OP_EXT:
3346 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3347 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3348 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3349 break;
3350 case OPC_OUB_SET_PHY_PROFILE:
3351 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3352 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3353 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3354 break;
3355 case OPC_OUB_KEK_MANAGEMENT_RESP:
3356 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3357 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3358 mpi_kek_management_resp(pm8001_ha, piomb);
3359 break;
3360 case OPC_OUB_DEK_MANAGEMENT_RESP:
3361 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3362 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3363 mpi_dek_management_resp(pm8001_ha, piomb);
3364 break;
3365 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3366 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3367 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3368 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3369 break;
3370 default:
3371 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3372 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3373 break;
3374 }
3375 }
3376
3377 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3378 {
3379 struct outbound_queue_table *circularQ;
3380 void *pMsg1 = NULL;
3381 u8 uninitialized_var(bc);
3382 u32 ret = MPI_IO_STATUS_FAIL;
3383 unsigned long flags;
3384
3385 spin_lock_irqsave(&pm8001_ha->lock, flags);
3386 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3387 do {
3388 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3389 if (MPI_IO_STATUS_SUCCESS == ret) {
3390 /* process the outbound message */
3391 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3392 /* free the message from the outbound circular buffer */
3393 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3394 circularQ, bc);
3395 }
3396 if (MPI_IO_STATUS_BUSY == ret) {
3397 /* Update the producer index from SPC */
3398 circularQ->producer_index =
3399 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3400 if (le32_to_cpu(circularQ->producer_index) ==
3401 circularQ->consumer_idx)
3402 /* OQ is empty */
3403 break;
3404 }
3405 } while (1);
3406 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3407 return ret;
3408 }
3409
3410 /* PCI_DMA_... to our direction translation. */
3411 static const u8 data_dir_flags[] = {
3412 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3413 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3414 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3415 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3416 };
3417
3418 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3419 struct smp_req *psmp_cmd, int mode, int length)
3420 {
3421 psmp_cmd->tag = hTag;
3422 psmp_cmd->device_id = cpu_to_le32(deviceID);
3423 if (mode == SMP_DIRECT) {
3424 length = length - 4; /* subtract crc */
3425 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3426 } else {
3427 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3428 }
3429 }
3430
3431 /**
3432 * pm8001_chip_smp_req - send a SMP task to FW
3433 * @pm8001_ha: our hba card information.
3434 * @ccb: the ccb information this request used.
3435 */
3436 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3437 struct pm8001_ccb_info *ccb)
3438 {
3439 int elem, rc;
3440 struct sas_task *task = ccb->task;
3441 struct domain_device *dev = task->dev;
3442 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3443 struct scatterlist *sg_req, *sg_resp;
3444 u32 req_len, resp_len;
3445 struct smp_req smp_cmd;
3446 u32 opc;
3447 struct inbound_queue_table *circularQ;
3448 char *preq_dma_addr = NULL;
3449 __le64 tmp_addr;
3450 u32 i, length;
3451
3452 memset(&smp_cmd, 0, sizeof(smp_cmd));
3453 /*
3454 * DMA-map SMP request, response buffers
3455 */
3456 sg_req = &task->smp_task.smp_req;
3457 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3458 if (!elem)
3459 return -ENOMEM;
3460 req_len = sg_dma_len(sg_req);
3461
3462 sg_resp = &task->smp_task.smp_resp;
3463 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3464 if (!elem) {
3465 rc = -ENOMEM;
3466 goto err_out;
3467 }
3468 resp_len = sg_dma_len(sg_resp);
3469 /* must be in dwords */
3470 if ((req_len & 0x3) || (resp_len & 0x3)) {
3471 rc = -EINVAL;
3472 goto err_out_2;
3473 }
3474
3475 opc = OPC_INB_SMP_REQUEST;
3476 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3477 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3478
3479 length = sg_req->length;
3480 PM8001_IO_DBG(pm8001_ha,
3481 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3482 if (!(length - 8))
3483 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3484 else
3485 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3486
3487 /* DIRECT MODE support only in spcv/ve */
3488 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3489
3490 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3491 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3492
3493 /* INDIRECT MODE command settings. Use DMA */
3494 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3495 PM8001_IO_DBG(pm8001_ha,
3496 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3497 /* for SPCv indirect mode. Place the top 4 bytes of
3498 * SMP Request header here. */
3499 for (i = 0; i < 4; i++)
3500 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3501 /* exclude top 4 bytes for SMP req header */
3502 smp_cmd.long_smp_req.long_req_addr =
3503 cpu_to_le64((u64)sg_dma_address
3504 (&task->smp_task.smp_req) - 4);
3505 /* exclude 4 bytes for SMP req header and CRC */
3506 smp_cmd.long_smp_req.long_req_size =
3507 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3508 smp_cmd.long_smp_req.long_resp_addr =
3509 cpu_to_le64((u64)sg_dma_address
3510 (&task->smp_task.smp_resp));
3511 smp_cmd.long_smp_req.long_resp_size =
3512 cpu_to_le32((u32)sg_dma_len
3513 (&task->smp_task.smp_resp)-4);
3514 } else { /* DIRECT MODE */
3515 smp_cmd.long_smp_req.long_req_addr =
3516 cpu_to_le64((u64)sg_dma_address
3517 (&task->smp_task.smp_req));
3518 smp_cmd.long_smp_req.long_req_size =
3519 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3520 smp_cmd.long_smp_req.long_resp_addr =
3521 cpu_to_le64((u64)sg_dma_address
3522 (&task->smp_task.smp_resp));
3523 smp_cmd.long_smp_req.long_resp_size =
3524 cpu_to_le32
3525 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3526 }
3527 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3528 PM8001_IO_DBG(pm8001_ha,
3529 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3530 for (i = 0; i < length; i++)
3531 if (i < 16) {
3532 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3533 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3534 "Byte[%d]:%x (DMA data:%x)\n",
3535 i, smp_cmd.smp_req16[i],
3536 *(preq_dma_addr)));
3537 } else {
3538 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3539 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3540 "Byte[%d]:%x (DMA data:%x)\n",
3541 i, smp_cmd.smp_req[i],
3542 *(preq_dma_addr)));
3543 }
3544 }
3545
3546 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3547 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3548 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3549 return 0;
3550
3551 err_out_2:
3552 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3553 PCI_DMA_FROMDEVICE);
3554 err_out:
3555 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3556 PCI_DMA_TODEVICE);
3557 return rc;
3558 }
3559
3560 static int check_enc_sas_cmd(struct sas_task *task)
3561 {
3562 u8 cmd = task->ssp_task.cmd->cmnd[0];
3563
3564 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3565 return 1;
3566 else
3567 return 0;
3568 }
3569
3570 static int check_enc_sat_cmd(struct sas_task *task)
3571 {
3572 int ret = 0;
3573 switch (task->ata_task.fis.command) {
3574 case ATA_CMD_FPDMA_READ:
3575 case ATA_CMD_READ_EXT:
3576 case ATA_CMD_READ:
3577 case ATA_CMD_FPDMA_WRITE:
3578 case ATA_CMD_WRITE_EXT:
3579 case ATA_CMD_WRITE:
3580 case ATA_CMD_PIO_READ:
3581 case ATA_CMD_PIO_READ_EXT:
3582 case ATA_CMD_PIO_WRITE:
3583 case ATA_CMD_PIO_WRITE_EXT:
3584 ret = 1;
3585 break;
3586 default:
3587 ret = 0;
3588 break;
3589 }
3590 return ret;
3591 }
3592
3593 /**
3594 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3595 * @pm8001_ha: our hba card information.
3596 * @ccb: the ccb information this request used.
3597 */
3598 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3599 struct pm8001_ccb_info *ccb)
3600 {
3601 struct sas_task *task = ccb->task;
3602 struct domain_device *dev = task->dev;
3603 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3604 struct ssp_ini_io_start_req ssp_cmd;
3605 u32 tag = ccb->ccb_tag;
3606 int ret;
3607 u64 phys_addr;
3608 struct inbound_queue_table *circularQ;
3609 static u32 inb;
3610 static u32 outb;
3611 u32 opc = OPC_INB_SSPINIIOSTART;
3612 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3613 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3614 /* data address domain added for spcv; set to 0 by host,
3615 * used internally by controller
3616 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3617 */
3618 ssp_cmd.dad_dir_m_tlr =
3619 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3620 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3621 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3622 ssp_cmd.tag = cpu_to_le32(tag);
3623 if (task->ssp_task.enable_first_burst)
3624 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3625 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3626 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3627 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3628 task->ssp_task.cmd->cmd_len);
3629 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3630
3631 /* Check if encryption is set */
3632 if (pm8001_ha->chip->encrypt &&
3633 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3634 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3635 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3636 task->ssp_task.cmd->cmnd[0]));
3637 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3638 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3639 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3640 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3641
3642 /* fill in PRD (scatter/gather) table, if any */
3643 if (task->num_scatter > 1) {
3644 pm8001_chip_make_sg(task->scatter,
3645 ccb->n_elem, ccb->buf_prd);
3646 phys_addr = ccb->ccb_dma_handle +
3647 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3648 ssp_cmd.enc_addr_low =
3649 cpu_to_le32(lower_32_bits(phys_addr));
3650 ssp_cmd.enc_addr_high =
3651 cpu_to_le32(upper_32_bits(phys_addr));
3652 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3653 } else if (task->num_scatter == 1) {
3654 u64 dma_addr = sg_dma_address(task->scatter);
3655 ssp_cmd.enc_addr_low =
3656 cpu_to_le32(lower_32_bits(dma_addr));
3657 ssp_cmd.enc_addr_high =
3658 cpu_to_le32(upper_32_bits(dma_addr));
3659 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3660 ssp_cmd.enc_esgl = 0;
3661 } else if (task->num_scatter == 0) {
3662 ssp_cmd.enc_addr_low = 0;
3663 ssp_cmd.enc_addr_high = 0;
3664 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3665 ssp_cmd.enc_esgl = 0;
3666 }
3667 /* XTS mode. All other fields are 0 */
3668 ssp_cmd.key_cmode = 0x6 << 4;
3669 /* set tweak values. Should be the start lba */
3670 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3671 (task->ssp_task.cmd->cmnd[3] << 16) |
3672 (task->ssp_task.cmd->cmnd[4] << 8) |
3673 (task->ssp_task.cmd->cmnd[5]));
3674 } else {
3675 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3676 "Sending Normal SAS command 0x%x inb q %x\n",
3677 task->ssp_task.cmd->cmnd[0], inb));
3678 /* fill in PRD (scatter/gather) table, if any */
3679 if (task->num_scatter > 1) {
3680 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3681 ccb->buf_prd);
3682 phys_addr = ccb->ccb_dma_handle +
3683 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3684 ssp_cmd.addr_low =
3685 cpu_to_le32(lower_32_bits(phys_addr));
3686 ssp_cmd.addr_high =
3687 cpu_to_le32(upper_32_bits(phys_addr));
3688 ssp_cmd.esgl = cpu_to_le32(1<<31);
3689 } else if (task->num_scatter == 1) {
3690 u64 dma_addr = sg_dma_address(task->scatter);
3691 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3692 ssp_cmd.addr_high =
3693 cpu_to_le32(upper_32_bits(dma_addr));
3694 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3695 ssp_cmd.esgl = 0;
3696 } else if (task->num_scatter == 0) {
3697 ssp_cmd.addr_low = 0;
3698 ssp_cmd.addr_high = 0;
3699 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3700 ssp_cmd.esgl = 0;
3701 }
3702 }
3703 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, outb++);
3704
3705 /* rotate the outb queue */
3706 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3707
3708 return ret;
3709 }
3710
3711 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3712 struct pm8001_ccb_info *ccb)
3713 {
3714 struct sas_task *task = ccb->task;
3715 struct domain_device *dev = task->dev;
3716 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3717 u32 tag = ccb->ccb_tag;
3718 int ret;
3719 static u32 inb;
3720 static u32 outb;
3721 struct sata_start_req sata_cmd;
3722 u32 hdr_tag, ncg_tag = 0;
3723 u64 phys_addr;
3724 u32 ATAP = 0x0;
3725 u32 dir;
3726 struct inbound_queue_table *circularQ;
3727 unsigned long flags;
3728 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3729 memset(&sata_cmd, 0, sizeof(sata_cmd));
3730 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3731
3732 if (task->data_dir == PCI_DMA_NONE) {
3733 ATAP = 0x04; /* no data*/
3734 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3735 } else if (likely(!task->ata_task.device_control_reg_update)) {
3736 if (task->ata_task.dma_xfer) {
3737 ATAP = 0x06; /* DMA */
3738 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3739 } else {
3740 ATAP = 0x05; /* PIO*/
3741 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3742 }
3743 if (task->ata_task.use_ncq &&
3744 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3745 ATAP = 0x07; /* FPDMA */
3746 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3747 }
3748 }
3749 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
3750 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
3751 ncg_tag = hdr_tag;
3752 }
3753 dir = data_dir_flags[task->data_dir] << 8;
3754 sata_cmd.tag = cpu_to_le32(tag);
3755 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3756 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3757
3758 sata_cmd.sata_fis = task->ata_task.fis;
3759 if (likely(!task->ata_task.device_control_reg_update))
3760 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3761 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3762
3763 /* Check if encryption is set */
3764 if (pm8001_ha->chip->encrypt &&
3765 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3766 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3767 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3768 sata_cmd.sata_fis.command));
3769 opc = OPC_INB_SATA_DIF_ENC_IO;
3770
3771 /* set encryption bit */
3772 sata_cmd.ncqtag_atap_dir_m_dad =
3773 cpu_to_le32(((ncg_tag & 0xff)<<16)|
3774 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3775 /* dad (bit 0-1) is 0 */
3776 /* fill in PRD (scatter/gather) table, if any */
3777 if (task->num_scatter > 1) {
3778 pm8001_chip_make_sg(task->scatter,
3779 ccb->n_elem, ccb->buf_prd);
3780 phys_addr = ccb->ccb_dma_handle +
3781 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3782 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3783 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3784 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3785 } else if (task->num_scatter == 1) {
3786 u64 dma_addr = sg_dma_address(task->scatter);
3787 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3788 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3789 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3790 sata_cmd.enc_esgl = 0;
3791 } else if (task->num_scatter == 0) {
3792 sata_cmd.enc_addr_low = 0;
3793 sata_cmd.enc_addr_high = 0;
3794 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3795 sata_cmd.enc_esgl = 0;
3796 }
3797 /* XTS mode. All other fields are 0 */
3798 sata_cmd.key_index_mode = 0x6 << 4;
3799 /* set tweak values. Should be the start lba */
3800 sata_cmd.twk_val0 =
3801 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3802 (sata_cmd.sata_fis.lbah << 16) |
3803 (sata_cmd.sata_fis.lbam << 8) |
3804 (sata_cmd.sata_fis.lbal));
3805 sata_cmd.twk_val1 =
3806 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3807 (sata_cmd.sata_fis.lbam_exp));
3808 } else {
3809 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3810 "Sending Normal SATA command 0x%x inb %x\n",
3811 sata_cmd.sata_fis.command, inb));
3812 /* dad (bit 0-1) is 0 */
3813 sata_cmd.ncqtag_atap_dir_m_dad =
3814 cpu_to_le32(((ncg_tag & 0xff)<<16) |
3815 ((ATAP & 0x3f) << 10) | dir);
3816
3817 /* fill in PRD (scatter/gather) table, if any */
3818 if (task->num_scatter > 1) {
3819 pm8001_chip_make_sg(task->scatter,
3820 ccb->n_elem, ccb->buf_prd);
3821 phys_addr = ccb->ccb_dma_handle +
3822 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3823 sata_cmd.addr_low = lower_32_bits(phys_addr);
3824 sata_cmd.addr_high = upper_32_bits(phys_addr);
3825 sata_cmd.esgl = cpu_to_le32(1 << 31);
3826 } else if (task->num_scatter == 1) {
3827 u64 dma_addr = sg_dma_address(task->scatter);
3828 sata_cmd.addr_low = lower_32_bits(dma_addr);
3829 sata_cmd.addr_high = upper_32_bits(dma_addr);
3830 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3831 sata_cmd.esgl = 0;
3832 } else if (task->num_scatter == 0) {
3833 sata_cmd.addr_low = 0;
3834 sata_cmd.addr_high = 0;
3835 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3836 sata_cmd.esgl = 0;
3837 }
3838 /* scsi cdb */
3839 sata_cmd.atapi_scsi_cdb[0] =
3840 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
3841 (task->ata_task.atapi_packet[1] << 8) |
3842 (task->ata_task.atapi_packet[2] << 16) |
3843 (task->ata_task.atapi_packet[3] << 24)));
3844 sata_cmd.atapi_scsi_cdb[1] =
3845 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
3846 (task->ata_task.atapi_packet[5] << 8) |
3847 (task->ata_task.atapi_packet[6] << 16) |
3848 (task->ata_task.atapi_packet[7] << 24)));
3849 sata_cmd.atapi_scsi_cdb[2] =
3850 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
3851 (task->ata_task.atapi_packet[9] << 8) |
3852 (task->ata_task.atapi_packet[10] << 16) |
3853 (task->ata_task.atapi_packet[11] << 24)));
3854 sata_cmd.atapi_scsi_cdb[3] =
3855 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
3856 (task->ata_task.atapi_packet[13] << 8) |
3857 (task->ata_task.atapi_packet[14] << 16) |
3858 (task->ata_task.atapi_packet[15] << 24)));
3859 }
3860
3861 /* Check for read log for failed drive and return */
3862 if (sata_cmd.sata_fis.command == 0x2f) {
3863 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
3864 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
3865 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
3866 struct task_status_struct *ts;
3867
3868 pm8001_ha_dev->id &= 0xDFFFFFFF;
3869 ts = &task->task_status;
3870
3871 spin_lock_irqsave(&task->task_state_lock, flags);
3872 ts->resp = SAS_TASK_COMPLETE;
3873 ts->stat = SAM_STAT_GOOD;
3874 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3875 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3876 task->task_state_flags |= SAS_TASK_STATE_DONE;
3877 if (unlikely((task->task_state_flags &
3878 SAS_TASK_STATE_ABORTED))) {
3879 spin_unlock_irqrestore(&task->task_state_lock,
3880 flags);
3881 PM8001_FAIL_DBG(pm8001_ha,
3882 pm8001_printk("task 0x%p resp 0x%x "
3883 " stat 0x%x but aborted by upper layer "
3884 "\n", task, ts->resp, ts->stat));
3885 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3886 return 0;
3887 } else if (task->uldd_task) {
3888 spin_unlock_irqrestore(&task->task_state_lock,
3889 flags);
3890 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3891 mb();/* ditto */
3892 spin_unlock_irq(&pm8001_ha->lock);
3893 task->task_done(task);
3894 spin_lock_irq(&pm8001_ha->lock);
3895 return 0;
3896 } else if (!task->uldd_task) {
3897 spin_unlock_irqrestore(&task->task_state_lock,
3898 flags);
3899 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3900 mb();/*ditto*/
3901 spin_unlock_irq(&pm8001_ha->lock);
3902 task->task_done(task);
3903 spin_lock_irq(&pm8001_ha->lock);
3904 return 0;
3905 }
3906 }
3907 }
3908
3909 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3910 &sata_cmd, outb++);
3911
3912 /* rotate the outb queue */
3913 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3914 return ret;
3915 }
3916
3917 /**
3918 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
3919 * @pm8001_ha: our hba card information.
3920 * @num: the inbound queue number
3921 * @phy_id: the phy id which we wanted to start up.
3922 */
3923 static int
3924 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3925 {
3926 struct phy_start_req payload;
3927 struct inbound_queue_table *circularQ;
3928 int ret;
3929 u32 tag = 0x01;
3930 u32 opcode = OPC_INB_PHYSTART;
3931 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3932 memset(&payload, 0, sizeof(payload));
3933 payload.tag = cpu_to_le32(tag);
3934
3935 PM8001_INIT_DBG(pm8001_ha,
3936 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
3937 /*
3938 ** [0:7] PHY Identifier
3939 ** [8:11] link rate 1.5G, 3G, 6G
3940 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
3941 ** [14] 0b disable spin up hold; 1b enable spin up hold
3942 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
3943 */
3944 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3945 LINKMODE_AUTO | LINKRATE_15 |
3946 LINKRATE_30 | LINKRATE_60 | phy_id);
3947 /* SSC Disable and SAS Analog ST configuration */
3948 /**
3949 payload.ase_sh_lm_slr_phyid =
3950 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
3951 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
3952 phy_id);
3953 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
3954 **/
3955
3956 payload.sas_identify.dev_type = SAS_END_DEVICE;
3957 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3958 memcpy(payload.sas_identify.sas_addr,
3959 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3960 payload.sas_identify.phy_id = phy_id;
3961 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3962 return ret;
3963 }
3964
3965 /**
3966 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3967 * @pm8001_ha: our hba card information.
3968 * @num: the inbound queue number
3969 * @phy_id: the phy id which we wanted to start up.
3970 */
3971 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3972 u8 phy_id)
3973 {
3974 struct phy_stop_req payload;
3975 struct inbound_queue_table *circularQ;
3976 int ret;
3977 u32 tag = 0x01;
3978 u32 opcode = OPC_INB_PHYSTOP;
3979 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3980 memset(&payload, 0, sizeof(payload));
3981 payload.tag = cpu_to_le32(tag);
3982 payload.phy_id = cpu_to_le32(phy_id);
3983 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3984 return ret;
3985 }
3986
3987 /**
3988 * see comments on pm8001_mpi_reg_resp.
3989 */
3990 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3991 struct pm8001_device *pm8001_dev, u32 flag)
3992 {
3993 struct reg_dev_req payload;
3994 u32 opc;
3995 u32 stp_sspsmp_sata = 0x4;
3996 struct inbound_queue_table *circularQ;
3997 u32 linkrate, phy_id;
3998 int rc, tag = 0xdeadbeef;
3999 struct pm8001_ccb_info *ccb;
4000 u8 retryFlag = 0x1;
4001 u16 firstBurstSize = 0;
4002 u16 ITNT = 2000;
4003 struct domain_device *dev = pm8001_dev->sas_device;
4004 struct domain_device *parent_dev = dev->parent;
4005 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4006
4007 memset(&payload, 0, sizeof(payload));
4008 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4009 if (rc)
4010 return rc;
4011 ccb = &pm8001_ha->ccb_info[tag];
4012 ccb->device = pm8001_dev;
4013 ccb->ccb_tag = tag;
4014 payload.tag = cpu_to_le32(tag);
4015
4016 if (flag == 1) {
4017 stp_sspsmp_sata = 0x02; /*direct attached sata */
4018 } else {
4019 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4020 stp_sspsmp_sata = 0x00; /* stp*/
4021 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4022 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4023 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4024 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4025 }
4026 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4027 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4028 else
4029 phy_id = pm8001_dev->attached_phy;
4030
4031 opc = OPC_INB_REG_DEV;
4032
4033 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4034 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4035
4036 payload.phyid_portid =
4037 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4038 ((phy_id & 0xFF) << 8));
4039
4040 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4041 ((linkrate & 0x0F) << 24) |
4042 ((stp_sspsmp_sata & 0x03) << 28));
4043 payload.firstburstsize_ITNexustimeout =
4044 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4045
4046 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4047 SAS_ADDR_SIZE);
4048
4049 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4050
4051 return rc;
4052 }
4053
4054 /**
4055 * pm80xx_chip_phy_ctl_req - support the local phy operation
4056 * @pm8001_ha: our hba card information.
4057 * @num: the inbound queue number
4058 * @phy_id: the phy id which we wanted to operate
4059 * @phy_op:
4060 */
4061 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4062 u32 phyId, u32 phy_op)
4063 {
4064 struct local_phy_ctl_req payload;
4065 struct inbound_queue_table *circularQ;
4066 int ret;
4067 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4068 memset(&payload, 0, sizeof(payload));
4069 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4070 payload.tag = cpu_to_le32(1);
4071 payload.phyop_phyid =
4072 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4073 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4074 return ret;
4075 }
4076
4077 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4078 {
4079 u32 value;
4080 #ifdef PM8001_USE_MSIX
4081 return 1;
4082 #endif
4083 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4084 if (value)
4085 return 1;
4086 return 0;
4087
4088 }
4089
4090 /**
4091 * pm8001_chip_isr - PM8001 isr handler.
4092 * @pm8001_ha: our hba card information.
4093 * @irq: irq number.
4094 * @stat: stat.
4095 */
4096 static irqreturn_t
4097 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4098 {
4099 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4100 process_oq(pm8001_ha, vec);
4101 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4102 return IRQ_HANDLED;
4103 }
4104
4105 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4106 .name = "pmc80xx",
4107 .chip_init = pm80xx_chip_init,
4108 .chip_soft_rst = pm80xx_chip_soft_rst,
4109 .chip_rst = pm80xx_hw_chip_rst,
4110 .chip_iounmap = pm8001_chip_iounmap,
4111 .isr = pm80xx_chip_isr,
4112 .is_our_interupt = pm80xx_chip_is_our_interupt,
4113 .isr_process_oq = process_oq,
4114 .interrupt_enable = pm80xx_chip_interrupt_enable,
4115 .interrupt_disable = pm80xx_chip_interrupt_disable,
4116 .make_prd = pm8001_chip_make_sg,
4117 .smp_req = pm80xx_chip_smp_req,
4118 .ssp_io_req = pm80xx_chip_ssp_io_req,
4119 .sata_req = pm80xx_chip_sata_req,
4120 .phy_start_req = pm80xx_chip_phy_start_req,
4121 .phy_stop_req = pm80xx_chip_phy_stop_req,
4122 .reg_dev_req = pm80xx_chip_reg_dev_req,
4123 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4124 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4125 .task_abort = pm8001_chip_abort_task,
4126 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4127 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4128 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4129 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4130 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4131 };
Linux with added FPC-III support