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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / spi / spi-dw.c
blob79c958e49f6110a33385d99b3116245028c6c264
1 /*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/highmem.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27
28 #include "spi-dw.h"
29
30 #ifdef CONFIG_DEBUG_FS
31 #include <linux/debugfs.h>
32 #endif
33
34 #define START_STATE ((void *)0)
35 #define RUNNING_STATE ((void *)1)
36 #define DONE_STATE ((void *)2)
37 #define ERROR_STATE ((void *)-1)
38
39 #define QUEUE_RUNNING 0
40 #define QUEUE_STOPPED 1
41
42 #define MRST_SPI_DEASSERT 0
43 #define MRST_SPI_ASSERT 1
44
45 /* Slave spi_dev related */
46 struct chip_data {
47 u16 cr0;
48 u8 cs; /* chip select pin */
49 u8 n_bytes; /* current is a 1/2/4 byte op */
50 u8 tmode; /* TR/TO/RO/EEPROM */
51 u8 type; /* SPI/SSP/MicroWire */
52
53 u8 poll_mode; /* 1 means use poll mode */
54
55 u32 dma_width;
56 u32 rx_threshold;
57 u32 tx_threshold;
58 u8 enable_dma;
59 u8 bits_per_word;
60 u16 clk_div; /* baud rate divider */
61 u32 speed_hz; /* baud rate */
62 void (*cs_control)(u32 command);
63 };
64
65 #ifdef CONFIG_DEBUG_FS
66 #define SPI_REGS_BUFSIZE 1024
67 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69 {
70 struct dw_spi *dws;
71 char *buf;
72 u32 len = 0;
73 ssize_t ret;
74
75 dws = file->private_data;
76
77 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
78 if (!buf)
79 return 0;
80
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "MRST SPI0 registers:\n");
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "=================================\n");
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "=================================\n");
117
118 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
119 kfree(buf);
120 return ret;
121 }
122
123 static const struct file_operations mrst_spi_regs_ops = {
124 .owner = THIS_MODULE,
125 .open = simple_open,
126 .read = spi_show_regs,
127 .llseek = default_llseek,
128 };
129
130 static int mrst_spi_debugfs_init(struct dw_spi *dws)
131 {
132 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
133 if (!dws->debugfs)
134 return -ENOMEM;
135
136 debugfs_create_file("registers", S_IFREG | S_IRUGO,
137 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
138 return 0;
139 }
140
141 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
142 {
143 if (dws->debugfs)
144 debugfs_remove_recursive(dws->debugfs);
145 }
146
147 #else
148 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
149 {
150 return 0;
151 }
152
153 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
154 {
155 }
156 #endif /* CONFIG_DEBUG_FS */
157
158 /* Return the max entries we can fill into tx fifo */
159 static inline u32 tx_max(struct dw_spi *dws)
160 {
161 u32 tx_left, tx_room, rxtx_gap;
162
163 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
164 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
165
166 /*
167 * Another concern is about the tx/rx mismatch, we
168 * though to use (dws->fifo_len - rxflr - txflr) as
169 * one maximum value for tx, but it doesn't cover the
170 * data which is out of tx/rx fifo and inside the
171 * shift registers. So a control from sw point of
172 * view is taken.
173 */
174 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
175 / dws->n_bytes;
176
177 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
178 }
179
180 /* Return the max entries we should read out of rx fifo */
181 static inline u32 rx_max(struct dw_spi *dws)
182 {
183 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
184
185 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
186 }
187
188 static void dw_writer(struct dw_spi *dws)
189 {
190 u32 max = tx_max(dws);
191 u16 txw = 0;
192
193 while (max--) {
194 /* Set the tx word if the transfer's original "tx" is not null */
195 if (dws->tx_end - dws->len) {
196 if (dws->n_bytes == 1)
197 txw = *(u8 *)(dws->tx);
198 else
199 txw = *(u16 *)(dws->tx);
200 }
201 dw_writew(dws, DW_SPI_DR, txw);
202 dws->tx += dws->n_bytes;
203 }
204 }
205
206 static void dw_reader(struct dw_spi *dws)
207 {
208 u32 max = rx_max(dws);
209 u16 rxw;
210
211 while (max--) {
212 rxw = dw_readw(dws, DW_SPI_DR);
213 /* Care rx only if the transfer's original "rx" is not null */
214 if (dws->rx_end - dws->len) {
215 if (dws->n_bytes == 1)
216 *(u8 *)(dws->rx) = rxw;
217 else
218 *(u16 *)(dws->rx) = rxw;
219 }
220 dws->rx += dws->n_bytes;
221 }
222 }
223
224 static void *next_transfer(struct dw_spi *dws)
225 {
226 struct spi_message *msg = dws->cur_msg;
227 struct spi_transfer *trans = dws->cur_transfer;
228
229 /* Move to next transfer */
230 if (trans->transfer_list.next != &msg->transfers) {
231 dws->cur_transfer =
232 list_entry(trans->transfer_list.next,
233 struct spi_transfer,
234 transfer_list);
235 return RUNNING_STATE;
236 } else
237 return DONE_STATE;
238 }
239
240 /*
241 * Note: first step is the protocol driver prepares
242 * a dma-capable memory, and this func just need translate
243 * the virt addr to physical
244 */
245 static int map_dma_buffers(struct dw_spi *dws)
246 {
247 if (!dws->cur_msg->is_dma_mapped
248 || !dws->dma_inited
249 || !dws->cur_chip->enable_dma
250 || !dws->dma_ops)
251 return 0;
252
253 if (dws->cur_transfer->tx_dma)
254 dws->tx_dma = dws->cur_transfer->tx_dma;
255
256 if (dws->cur_transfer->rx_dma)
257 dws->rx_dma = dws->cur_transfer->rx_dma;
258
259 return 1;
260 }
261
262 /* Caller already set message->status; dma and pio irqs are blocked */
263 static void giveback(struct dw_spi *dws)
264 {
265 struct spi_transfer *last_transfer;
266 unsigned long flags;
267 struct spi_message *msg;
268
269 spin_lock_irqsave(&dws->lock, flags);
270 msg = dws->cur_msg;
271 dws->cur_msg = NULL;
272 dws->cur_transfer = NULL;
273 dws->prev_chip = dws->cur_chip;
274 dws->cur_chip = NULL;
275 dws->dma_mapped = 0;
276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags);
278
279 last_transfer = list_entry(msg->transfers.prev,
280 struct spi_transfer,
281 transfer_list);
282
283 if (!last_transfer->cs_change && dws->cs_control)
284 dws->cs_control(MRST_SPI_DEASSERT);
285
286 msg->state = NULL;
287 if (msg->complete)
288 msg->complete(msg->context);
289 }
290
291 static void int_error_stop(struct dw_spi *dws, const char *msg)
292 {
293 /* Stop the hw */
294 spi_enable_chip(dws, 0);
295
296 dev_err(&dws->master->dev, "%s\n", msg);
297 dws->cur_msg->state = ERROR_STATE;
298 tasklet_schedule(&dws->pump_transfers);
299 }
300
301 void dw_spi_xfer_done(struct dw_spi *dws)
302 {
303 /* Update total byte transferred return count actual bytes read */
304 dws->cur_msg->actual_length += dws->len;
305
306 /* Move to next transfer */
307 dws->cur_msg->state = next_transfer(dws);
308
309 /* Handle end of message */
310 if (dws->cur_msg->state == DONE_STATE) {
311 dws->cur_msg->status = 0;
312 giveback(dws);
313 } else
314 tasklet_schedule(&dws->pump_transfers);
315 }
316 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
317
318 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
319 {
320 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
321
322 /* Error handling */
323 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
324 dw_readw(dws, DW_SPI_TXOICR);
325 dw_readw(dws, DW_SPI_RXOICR);
326 dw_readw(dws, DW_SPI_RXUICR);
327 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
328 return IRQ_HANDLED;
329 }
330
331 dw_reader(dws);
332 if (dws->rx_end == dws->rx) {
333 spi_mask_intr(dws, SPI_INT_TXEI);
334 dw_spi_xfer_done(dws);
335 return IRQ_HANDLED;
336 }
337 if (irq_status & SPI_INT_TXEI) {
338 spi_mask_intr(dws, SPI_INT_TXEI);
339 dw_writer(dws);
340 /* Enable TX irq always, it will be disabled when RX finished */
341 spi_umask_intr(dws, SPI_INT_TXEI);
342 }
343
344 return IRQ_HANDLED;
345 }
346
347 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
348 {
349 struct dw_spi *dws = dev_id;
350 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
351
352 if (!irq_status)
353 return IRQ_NONE;
354
355 if (!dws->cur_msg) {
356 spi_mask_intr(dws, SPI_INT_TXEI);
357 return IRQ_HANDLED;
358 }
359
360 return dws->transfer_handler(dws);
361 }
362
363 /* Must be called inside pump_transfers() */
364 static void poll_transfer(struct dw_spi *dws)
365 {
366 do {
367 dw_writer(dws);
368 dw_reader(dws);
369 cpu_relax();
370 } while (dws->rx_end > dws->rx);
371
372 dw_spi_xfer_done(dws);
373 }
374
375 static void pump_transfers(unsigned long data)
376 {
377 struct dw_spi *dws = (struct dw_spi *)data;
378 struct spi_message *message = NULL;
379 struct spi_transfer *transfer = NULL;
380 struct spi_transfer *previous = NULL;
381 struct spi_device *spi = NULL;
382 struct chip_data *chip = NULL;
383 u8 bits = 0;
384 u8 imask = 0;
385 u8 cs_change = 0;
386 u16 txint_level = 0;
387 u16 clk_div = 0;
388 u32 speed = 0;
389 u32 cr0 = 0;
390
391 /* Get current state information */
392 message = dws->cur_msg;
393 transfer = dws->cur_transfer;
394 chip = dws->cur_chip;
395 spi = message->spi;
396
397 if (unlikely(!chip->clk_div))
398 chip->clk_div = dws->max_freq / chip->speed_hz;
399
400 if (message->state == ERROR_STATE) {
401 message->status = -EIO;
402 goto early_exit;
403 }
404
405 /* Handle end of message */
406 if (message->state == DONE_STATE) {
407 message->status = 0;
408 goto early_exit;
409 }
410
411 /* Delay if requested at end of transfer*/
412 if (message->state == RUNNING_STATE) {
413 previous = list_entry(transfer->transfer_list.prev,
414 struct spi_transfer,
415 transfer_list);
416 if (previous->delay_usecs)
417 udelay(previous->delay_usecs);
418 }
419
420 dws->n_bytes = chip->n_bytes;
421 dws->dma_width = chip->dma_width;
422 dws->cs_control = chip->cs_control;
423
424 dws->rx_dma = transfer->rx_dma;
425 dws->tx_dma = transfer->tx_dma;
426 dws->tx = (void *)transfer->tx_buf;
427 dws->tx_end = dws->tx + transfer->len;
428 dws->rx = transfer->rx_buf;
429 dws->rx_end = dws->rx + transfer->len;
430 dws->cs_change = transfer->cs_change;
431 dws->len = dws->cur_transfer->len;
432 if (chip != dws->prev_chip)
433 cs_change = 1;
434
435 cr0 = chip->cr0;
436
437 /* Handle per transfer options for bpw and speed */
438 if (transfer->speed_hz) {
439 speed = chip->speed_hz;
440
441 if (transfer->speed_hz != speed) {
442 speed = transfer->speed_hz;
443 if (speed > dws->max_freq) {
444 printk(KERN_ERR "MRST SPI0: unsupported"
445 "freq: %dHz\n", speed);
446 message->status = -EIO;
447 goto early_exit;
448 }
449
450 /* clk_div doesn't support odd number */
451 clk_div = dws->max_freq / speed;
452 clk_div = (clk_div + 1) & 0xfffe;
453
454 chip->speed_hz = speed;
455 chip->clk_div = clk_div;
456 }
457 }
458 if (transfer->bits_per_word) {
459 bits = transfer->bits_per_word;
460 dws->n_bytes = dws->dma_width = bits >> 3;
461 cr0 = (bits - 1)
462 | (chip->type << SPI_FRF_OFFSET)
463 | (spi->mode << SPI_MODE_OFFSET)
464 | (chip->tmode << SPI_TMOD_OFFSET);
465 }
466 message->state = RUNNING_STATE;
467
468 /*
469 * Adjust transfer mode if necessary. Requires platform dependent
470 * chipselect mechanism.
471 */
472 if (dws->cs_control) {
473 if (dws->rx && dws->tx)
474 chip->tmode = SPI_TMOD_TR;
475 else if (dws->rx)
476 chip->tmode = SPI_TMOD_RO;
477 else
478 chip->tmode = SPI_TMOD_TO;
479
480 cr0 &= ~SPI_TMOD_MASK;
481 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
482 }
483
484 /* Check if current transfer is a DMA transaction */
485 dws->dma_mapped = map_dma_buffers(dws);
486
487 /*
488 * Interrupt mode
489 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
490 */
491 if (!dws->dma_mapped && !chip->poll_mode) {
492 int templen = dws->len / dws->n_bytes;
493 txint_level = dws->fifo_len / 2;
494 txint_level = (templen > txint_level) ? txint_level : templen;
495
496 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
497 dws->transfer_handler = interrupt_transfer;
498 }
499
500 /*
501 * Reprogram registers only if
502 * 1. chip select changes
503 * 2. clk_div is changed
504 * 3. control value changes
505 */
506 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
507 spi_enable_chip(dws, 0);
508
509 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
510 dw_writew(dws, DW_SPI_CTRL0, cr0);
511
512 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
513 spi_chip_sel(dws, spi->chip_select);
514
515 /* Set the interrupt mask, for poll mode just disable all int */
516 spi_mask_intr(dws, 0xff);
517 if (imask)
518 spi_umask_intr(dws, imask);
519 if (txint_level)
520 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
521
522 spi_enable_chip(dws, 1);
523 if (cs_change)
524 dws->prev_chip = chip;
525 }
526
527 if (dws->dma_mapped)
528 dws->dma_ops->dma_transfer(dws, cs_change);
529
530 if (chip->poll_mode)
531 poll_transfer(dws);
532
533 return;
534
535 early_exit:
536 giveback(dws);
537 return;
538 }
539
540 static void pump_messages(struct work_struct *work)
541 {
542 struct dw_spi *dws =
543 container_of(work, struct dw_spi, pump_messages);
544 unsigned long flags;
545
546 /* Lock queue and check for queue work */
547 spin_lock_irqsave(&dws->lock, flags);
548 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
549 dws->busy = 0;
550 spin_unlock_irqrestore(&dws->lock, flags);
551 return;
552 }
553
554 /* Make sure we are not already running a message */
555 if (dws->cur_msg) {
556 spin_unlock_irqrestore(&dws->lock, flags);
557 return;
558 }
559
560 /* Extract head of queue */
561 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
562 list_del_init(&dws->cur_msg->queue);
563
564 /* Initial message state*/
565 dws->cur_msg->state = START_STATE;
566 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
567 struct spi_transfer,
568 transfer_list);
569 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
570
571 /* Mark as busy and launch transfers */
572 tasklet_schedule(&dws->pump_transfers);
573
574 dws->busy = 1;
575 spin_unlock_irqrestore(&dws->lock, flags);
576 }
577
578 /* spi_device use this to queue in their spi_msg */
579 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
580 {
581 struct dw_spi *dws = spi_master_get_devdata(spi->master);
582 unsigned long flags;
583
584 spin_lock_irqsave(&dws->lock, flags);
585
586 if (dws->run == QUEUE_STOPPED) {
587 spin_unlock_irqrestore(&dws->lock, flags);
588 return -ESHUTDOWN;
589 }
590
591 msg->actual_length = 0;
592 msg->status = -EINPROGRESS;
593 msg->state = START_STATE;
594
595 list_add_tail(&msg->queue, &dws->queue);
596
597 if (dws->run == QUEUE_RUNNING && !dws->busy) {
598
599 if (dws->cur_transfer || dws->cur_msg)
600 queue_work(dws->workqueue,
601 &dws->pump_messages);
602 else {
603 /* If no other data transaction in air, just go */
604 spin_unlock_irqrestore(&dws->lock, flags);
605 pump_messages(&dws->pump_messages);
606 return 0;
607 }
608 }
609
610 spin_unlock_irqrestore(&dws->lock, flags);
611 return 0;
612 }
613
614 /* This may be called twice for each spi dev */
615 static int dw_spi_setup(struct spi_device *spi)
616 {
617 struct dw_spi_chip *chip_info = NULL;
618 struct chip_data *chip;
619
620 /* Only alloc on first setup */
621 chip = spi_get_ctldata(spi);
622 if (!chip) {
623 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
624 if (!chip)
625 return -ENOMEM;
626 }
627
628 /*
629 * Protocol drivers may change the chip settings, so...
630 * if chip_info exists, use it
631 */
632 chip_info = spi->controller_data;
633
634 /* chip_info doesn't always exist */
635 if (chip_info) {
636 if (chip_info->cs_control)
637 chip->cs_control = chip_info->cs_control;
638
639 chip->poll_mode = chip_info->poll_mode;
640 chip->type = chip_info->type;
641
642 chip->rx_threshold = 0;
643 chip->tx_threshold = 0;
644
645 chip->enable_dma = chip_info->enable_dma;
646 }
647
648 if (spi->bits_per_word == 8) {
649 chip->n_bytes = 1;
650 chip->dma_width = 1;
651 } else if (spi->bits_per_word == 16) {
652 chip->n_bytes = 2;
653 chip->dma_width = 2;
654 }
655 chip->bits_per_word = spi->bits_per_word;
656
657 if (!spi->max_speed_hz) {
658 dev_err(&spi->dev, "No max speed HZ parameter\n");
659 return -EINVAL;
660 }
661 chip->speed_hz = spi->max_speed_hz;
662
663 chip->tmode = 0; /* Tx & Rx */
664 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
665 chip->cr0 = (chip->bits_per_word - 1)
666 | (chip->type << SPI_FRF_OFFSET)
667 | (spi->mode << SPI_MODE_OFFSET)
668 | (chip->tmode << SPI_TMOD_OFFSET);
669
670 spi_set_ctldata(spi, chip);
671 return 0;
672 }
673
674 static void dw_spi_cleanup(struct spi_device *spi)
675 {
676 struct chip_data *chip = spi_get_ctldata(spi);
677 kfree(chip);
678 }
679
680 static int init_queue(struct dw_spi *dws)
681 {
682 INIT_LIST_HEAD(&dws->queue);
683 spin_lock_init(&dws->lock);
684
685 dws->run = QUEUE_STOPPED;
686 dws->busy = 0;
687
688 tasklet_init(&dws->pump_transfers,
689 pump_transfers, (unsigned long)dws);
690
691 INIT_WORK(&dws->pump_messages, pump_messages);
692 dws->workqueue = create_singlethread_workqueue(
693 dev_name(dws->master->dev.parent));
694 if (dws->workqueue == NULL)
695 return -EBUSY;
696
697 return 0;
698 }
699
700 static int start_queue(struct dw_spi *dws)
701 {
702 unsigned long flags;
703
704 spin_lock_irqsave(&dws->lock, flags);
705
706 if (dws->run == QUEUE_RUNNING || dws->busy) {
707 spin_unlock_irqrestore(&dws->lock, flags);
708 return -EBUSY;
709 }
710
711 dws->run = QUEUE_RUNNING;
712 dws->cur_msg = NULL;
713 dws->cur_transfer = NULL;
714 dws->cur_chip = NULL;
715 dws->prev_chip = NULL;
716 spin_unlock_irqrestore(&dws->lock, flags);
717
718 queue_work(dws->workqueue, &dws->pump_messages);
719
720 return 0;
721 }
722
723 static int stop_queue(struct dw_spi *dws)
724 {
725 unsigned long flags;
726 unsigned limit = 50;
727 int status = 0;
728
729 spin_lock_irqsave(&dws->lock, flags);
730 dws->run = QUEUE_STOPPED;
731 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
732 spin_unlock_irqrestore(&dws->lock, flags);
733 msleep(10);
734 spin_lock_irqsave(&dws->lock, flags);
735 }
736
737 if (!list_empty(&dws->queue) || dws->busy)
738 status = -EBUSY;
739 spin_unlock_irqrestore(&dws->lock, flags);
740
741 return status;
742 }
743
744 static int destroy_queue(struct dw_spi *dws)
745 {
746 int status;
747
748 status = stop_queue(dws);
749 if (status != 0)
750 return status;
751 destroy_workqueue(dws->workqueue);
752 return 0;
753 }
754
755 /* Restart the controller, disable all interrupts, clean rx fifo */
756 static void spi_hw_init(struct dw_spi *dws)
757 {
758 spi_enable_chip(dws, 0);
759 spi_mask_intr(dws, 0xff);
760 spi_enable_chip(dws, 1);
761
762 /*
763 * Try to detect the FIFO depth if not set by interface driver,
764 * the depth could be from 2 to 256 from HW spec
765 */
766 if (!dws->fifo_len) {
767 u32 fifo;
768 for (fifo = 2; fifo <= 257; fifo++) {
769 dw_writew(dws, DW_SPI_TXFLTR, fifo);
770 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
771 break;
772 }
773
774 dws->fifo_len = (fifo == 257) ? 0 : fifo;
775 dw_writew(dws, DW_SPI_TXFLTR, 0);
776 }
777 }
778
779 int dw_spi_add_host(struct dw_spi *dws)
780 {
781 struct spi_master *master;
782 int ret;
783
784 BUG_ON(dws == NULL);
785
786 master = spi_alloc_master(dws->parent_dev, 0);
787 if (!master) {
788 ret = -ENOMEM;
789 goto exit;
790 }
791
792 dws->master = master;
793 dws->type = SSI_MOTO_SPI;
794 dws->prev_chip = NULL;
795 dws->dma_inited = 0;
796 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
797 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
798 dws->bus_num);
799
800 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
801 dws->name, dws);
802 if (ret < 0) {
803 dev_err(&master->dev, "can not get IRQ\n");
804 goto err_free_master;
805 }
806
807 master->mode_bits = SPI_CPOL | SPI_CPHA;
808 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
809 master->bus_num = dws->bus_num;
810 master->num_chipselect = dws->num_cs;
811 master->cleanup = dw_spi_cleanup;
812 master->setup = dw_spi_setup;
813 master->transfer = dw_spi_transfer;
814
815 /* Basic HW init */
816 spi_hw_init(dws);
817
818 if (dws->dma_ops && dws->dma_ops->dma_init) {
819 ret = dws->dma_ops->dma_init(dws);
820 if (ret) {
821 dev_warn(&master->dev, "DMA init failed\n");
822 dws->dma_inited = 0;
823 }
824 }
825
826 /* Initial and start queue */
827 ret = init_queue(dws);
828 if (ret) {
829 dev_err(&master->dev, "problem initializing queue\n");
830 goto err_diable_hw;
831 }
832 ret = start_queue(dws);
833 if (ret) {
834 dev_err(&master->dev, "problem starting queue\n");
835 goto err_diable_hw;
836 }
837
838 spi_master_set_devdata(master, dws);
839 ret = spi_register_master(master);
840 if (ret) {
841 dev_err(&master->dev, "problem registering spi master\n");
842 goto err_queue_alloc;
843 }
844
845 mrst_spi_debugfs_init(dws);
846 return 0;
847
848 err_queue_alloc:
849 destroy_queue(dws);
850 if (dws->dma_ops && dws->dma_ops->dma_exit)
851 dws->dma_ops->dma_exit(dws);
852 err_diable_hw:
853 spi_enable_chip(dws, 0);
854 free_irq(dws->irq, dws);
855 err_free_master:
856 spi_master_put(master);
857 exit:
858 return ret;
859 }
860 EXPORT_SYMBOL_GPL(dw_spi_add_host);
861
862 void dw_spi_remove_host(struct dw_spi *dws)
863 {
864 int status = 0;
865
866 if (!dws)
867 return;
868 mrst_spi_debugfs_remove(dws);
869
870 /* Remove the queue */
871 status = destroy_queue(dws);
872 if (status != 0)
873 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
874 "complete, message memory not freed\n");
875
876 if (dws->dma_ops && dws->dma_ops->dma_exit)
877 dws->dma_ops->dma_exit(dws);
878 spi_enable_chip(dws, 0);
879 /* Disable clk */
880 spi_set_clk(dws, 0);
881 free_irq(dws->irq, dws);
882
883 /* Disconnect from the SPI framework */
884 spi_unregister_master(dws->master);
885 }
886 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
887
888 int dw_spi_suspend_host(struct dw_spi *dws)
889 {
890 int ret = 0;
891
892 ret = stop_queue(dws);
893 if (ret)
894 return ret;
895 spi_enable_chip(dws, 0);
896 spi_set_clk(dws, 0);
897 return ret;
898 }
899 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
900
901 int dw_spi_resume_host(struct dw_spi *dws)
902 {
903 int ret;
904
905 spi_hw_init(dws);
906 ret = start_queue(dws);
907 if (ret)
908 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
909 return ret;
910 }
911 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
912
913 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
914 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
915 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support