2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011, 2012 Cavium, Inc.
9 #include <linux/platform_device.h>
10 #include <linux/interrupt.h>
11 #include <linux/spi/spi.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
18 #include <asm/octeon/octeon.h>
19 #include <asm/octeon/cvmx-mpi-defs.h>
21 #define OCTEON_SPI_CFG 0
22 #define OCTEON_SPI_STS 0x08
23 #define OCTEON_SPI_TX 0x10
24 #define OCTEON_SPI_DAT0 0x80
26 #define OCTEON_SPI_MAX_BYTES 9
28 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
36 struct octeon_spi_setup
{
43 static void octeon_spi_wait_ready(struct octeon_spi
*p
)
45 union cvmx_mpi_sts mpi_sts
;
46 unsigned int loops
= 0;
51 mpi_sts
.u64
= cvmx_read_csr(p
->register_base
+ OCTEON_SPI_STS
);
52 } while (mpi_sts
.s
.busy
);
55 static int octeon_spi_do_transfer(struct octeon_spi
*p
,
56 struct spi_message
*msg
,
57 struct spi_transfer
*xfer
,
60 union cvmx_mpi_cfg mpi_cfg
;
61 union cvmx_mpi_tx mpi_tx
;
63 unsigned int speed_hz
;
71 struct octeon_spi_setup
*msg_setup
= spi_get_ctldata(msg
->spi
);
73 speed_hz
= msg_setup
->max_speed_hz
;
74 mode
= msg_setup
->mode
;
75 cpha
= mode
& SPI_CPHA
;
76 cpol
= mode
& SPI_CPOL
;
79 speed_hz
= xfer
->speed_hz
;
81 if (speed_hz
> OCTEON_SPI_MAX_CLOCK_HZ
)
82 speed_hz
= OCTEON_SPI_MAX_CLOCK_HZ
;
84 clkdiv
= octeon_get_io_clock_rate() / (2 * speed_hz
);
88 mpi_cfg
.s
.clkdiv
= clkdiv
;
89 mpi_cfg
.s
.cshi
= (mode
& SPI_CS_HIGH
) ? 1 : 0;
90 mpi_cfg
.s
.lsbfirst
= (mode
& SPI_LSB_FIRST
) ? 1 : 0;
91 mpi_cfg
.s
.wireor
= (mode
& SPI_3WIRE
) ? 1 : 0;
92 mpi_cfg
.s
.idlelo
= cpha
!= cpol
;
93 mpi_cfg
.s
.cslate
= cpha
? 1 : 0;
96 if (msg_setup
->chip_select
< 4)
97 p
->cs_enax
|= 1ull << (12 + msg_setup
->chip_select
);
98 mpi_cfg
.u64
|= p
->cs_enax
;
100 if (mpi_cfg
.u64
!= p
->last_cfg
) {
101 p
->last_cfg
= mpi_cfg
.u64
;
102 cvmx_write_csr(p
->register_base
+ OCTEON_SPI_CFG
, mpi_cfg
.u64
);
104 tx_buf
= xfer
->tx_buf
;
105 rx_buf
= xfer
->rx_buf
;
107 while (len
> OCTEON_SPI_MAX_BYTES
) {
108 for (i
= 0; i
< OCTEON_SPI_MAX_BYTES
; i
++) {
114 cvmx_write_csr(p
->register_base
+ OCTEON_SPI_DAT0
+ (8 * i
), d
);
117 mpi_tx
.s
.csid
= msg_setup
->chip_select
;
118 mpi_tx
.s
.leavecs
= 1;
119 mpi_tx
.s
.txnum
= tx_buf
? OCTEON_SPI_MAX_BYTES
: 0;
120 mpi_tx
.s
.totnum
= OCTEON_SPI_MAX_BYTES
;
121 cvmx_write_csr(p
->register_base
+ OCTEON_SPI_TX
, mpi_tx
.u64
);
123 octeon_spi_wait_ready(p
);
125 for (i
= 0; i
< OCTEON_SPI_MAX_BYTES
; i
++) {
126 u64 v
= cvmx_read_csr(p
->register_base
+ OCTEON_SPI_DAT0
+ (8 * i
));
129 len
-= OCTEON_SPI_MAX_BYTES
;
132 for (i
= 0; i
< len
; i
++) {
138 cvmx_write_csr(p
->register_base
+ OCTEON_SPI_DAT0
+ (8 * i
), d
);
142 mpi_tx
.s
.csid
= msg_setup
->chip_select
;
144 mpi_tx
.s
.leavecs
= xfer
->cs_change
;
146 mpi_tx
.s
.leavecs
= !xfer
->cs_change
;
147 mpi_tx
.s
.txnum
= tx_buf
? len
: 0;
148 mpi_tx
.s
.totnum
= len
;
149 cvmx_write_csr(p
->register_base
+ OCTEON_SPI_TX
, mpi_tx
.u64
);
151 octeon_spi_wait_ready(p
);
153 for (i
= 0; i
< len
; i
++) {
154 u64 v
= cvmx_read_csr(p
->register_base
+ OCTEON_SPI_DAT0
+ (8 * i
));
158 if (xfer
->delay_usecs
)
159 udelay(xfer
->delay_usecs
);
164 static int octeon_spi_transfer_one_message(struct spi_master
*master
,
165 struct spi_message
*msg
)
167 struct octeon_spi
*p
= spi_master_get_devdata(master
);
168 unsigned int total_len
= 0;
170 struct spi_transfer
*xfer
;
173 * We better have set the configuration via a call to .setup
174 * before we get here.
176 if (spi_get_ctldata(msg
->spi
) == NULL
) {
181 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
182 bool last_xfer
= &xfer
->transfer_list
== msg
->transfers
.prev
;
183 int r
= octeon_spi_do_transfer(p
, msg
, xfer
, last_xfer
);
191 msg
->status
= status
;
192 msg
->actual_length
= total_len
;
193 spi_finalize_current_message(master
);
197 static struct octeon_spi_setup
*octeon_spi_new_setup(struct spi_device
*spi
)
199 struct octeon_spi_setup
*setup
= kzalloc(sizeof(*setup
), GFP_KERNEL
);
203 setup
->max_speed_hz
= spi
->max_speed_hz
;
204 setup
->chip_select
= spi
->chip_select
;
205 setup
->mode
= spi
->mode
;
206 setup
->bits_per_word
= spi
->bits_per_word
;
210 static int octeon_spi_setup(struct spi_device
*spi
)
212 struct octeon_spi_setup
*new_setup
;
213 struct octeon_spi_setup
*old_setup
= spi_get_ctldata(spi
);
215 new_setup
= octeon_spi_new_setup(spi
);
219 spi_set_ctldata(spi
, new_setup
);
225 static void octeon_spi_cleanup(struct spi_device
*spi
)
227 struct octeon_spi_setup
*old_setup
= spi_get_ctldata(spi
);
228 spi_set_ctldata(spi
, NULL
);
232 static int octeon_spi_probe(struct platform_device
*pdev
)
234 struct resource
*res_mem
;
235 struct spi_master
*master
;
236 struct octeon_spi
*p
;
239 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct octeon_spi
));
242 p
= spi_master_get_devdata(master
);
243 platform_set_drvdata(pdev
, master
);
245 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
247 if (res_mem
== NULL
) {
248 dev_err(&pdev
->dev
, "found no memory resource\n");
252 if (!devm_request_mem_region(&pdev
->dev
, res_mem
->start
,
253 resource_size(res_mem
), res_mem
->name
)) {
254 dev_err(&pdev
->dev
, "request_mem_region failed\n");
257 p
->register_base
= (u64
)devm_ioremap(&pdev
->dev
, res_mem
->start
,
258 resource_size(res_mem
));
260 /* Dynamic bus numbering */
261 master
->bus_num
= -1;
262 master
->num_chipselect
= 4;
263 master
->mode_bits
= SPI_CPHA
|
269 master
->setup
= octeon_spi_setup
;
270 master
->cleanup
= octeon_spi_cleanup
;
271 master
->transfer_one_message
= octeon_spi_transfer_one_message
;
272 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
274 master
->dev
.of_node
= pdev
->dev
.of_node
;
275 err
= spi_register_master(master
);
277 dev_err(&pdev
->dev
, "register master failed: %d\n", err
);
281 dev_info(&pdev
->dev
, "OCTEON SPI bus driver\n");
285 spi_master_put(master
);
289 static int octeon_spi_remove(struct platform_device
*pdev
)
291 struct spi_master
*master
= platform_get_drvdata(pdev
);
292 struct octeon_spi
*p
= spi_master_get_devdata(master
);
293 u64 register_base
= p
->register_base
;
295 spi_unregister_master(master
);
297 /* Clear the CSENA* and put everything in a known state. */
298 cvmx_write_csr(register_base
+ OCTEON_SPI_CFG
, 0);
303 static struct of_device_id octeon_spi_match
[] = {
304 { .compatible
= "cavium,octeon-3010-spi", },
307 MODULE_DEVICE_TABLE(of
, octeon_spi_match
);
309 static struct platform_driver octeon_spi_driver
= {
311 .name
= "spi-octeon",
312 .owner
= THIS_MODULE
,
313 .of_match_table
= octeon_spi_match
,
315 .probe
= octeon_spi_probe
,
316 .remove
= octeon_spi_remove
,
319 module_platform_driver(octeon_spi_driver
);
321 MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
322 MODULE_AUTHOR("David Daney");
323 MODULE_LICENSE("GPL");