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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / spi / spi-topcliff-pch.c
blobeaeeed51bbbfa1f6a315fd87a2cef72b5dd2c5d1
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33
34 /* Register offsets */
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
41 #define PCH_SRST 0x1C /* SPI reset register */
42 #define PCH_ADDRESS_SIZE 0x20
43
44 #define PCH_SPSR_TFD 0x000007C0
45 #define PCH_SPSR_RFD 0x0000F800
46
47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
49
50 #define PCH_RX_THOLD 7
51 #define PCH_RX_THOLD_MAX 15
52
53 #define PCH_TX_THOLD 2
54
55 #define PCH_MAX_BAUDRATE 5000000
56 #define PCH_MAX_FIFO_DEPTH 16
57
58 #define STATUS_RUNNING 1
59 #define STATUS_EXITING 2
60 #define PCH_SLEEP_TIME 10
61
62 #define SSN_LOW 0x02U
63 #define SSN_HIGH 0x03U
64 #define SSN_NO_CONTROL 0x00U
65 #define PCH_MAX_CS 0xFF
66 #define PCI_DEVICE_ID_GE_SPI 0x8816
67
68 #define SPCR_SPE_BIT (1 << 0)
69 #define SPCR_MSTR_BIT (1 << 1)
70 #define SPCR_LSBF_BIT (1 << 4)
71 #define SPCR_CPHA_BIT (1 << 5)
72 #define SPCR_CPOL_BIT (1 << 6)
73 #define SPCR_TFIE_BIT (1 << 8)
74 #define SPCR_RFIE_BIT (1 << 9)
75 #define SPCR_FIE_BIT (1 << 10)
76 #define SPCR_ORIE_BIT (1 << 11)
77 #define SPCR_MDFIE_BIT (1 << 12)
78 #define SPCR_FICLR_BIT (1 << 24)
79 #define SPSR_TFI_BIT (1 << 0)
80 #define SPSR_RFI_BIT (1 << 1)
81 #define SPSR_FI_BIT (1 << 2)
82 #define SPSR_ORF_BIT (1 << 3)
83 #define SPBRR_SIZE_BIT (1 << 10)
84
85 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
86 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
87
88 #define SPCR_RFIC_FIELD 20
89 #define SPCR_TFIC_FIELD 16
90
91 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
92 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
93 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
94
95 #define PCH_CLOCK_HZ 50000000
96 #define PCH_MAX_SPBR 1023
97
98 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
99 #define PCI_VENDOR_ID_ROHM 0x10DB
100 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
101 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
102 #define PCI_DEVICE_ID_ML7831_SPI 0x8816
103
104 /*
105 * Set the number of SPI instance max
106 * Intel EG20T PCH : 1ch
107 * LAPIS Semiconductor ML7213 IOH : 2ch
108 * LAPIS Semiconductor ML7223 IOH : 1ch
109 * LAPIS Semiconductor ML7831 IOH : 1ch
110 */
111 #define PCH_SPI_MAX_DEV 2
112
113 #define PCH_BUF_SIZE 4096
114 #define PCH_DMA_TRANS_SIZE 12
115
116 static int use_dma = 1;
117
118 struct pch_spi_dma_ctrl {
119 struct dma_async_tx_descriptor *desc_tx;
120 struct dma_async_tx_descriptor *desc_rx;
121 struct pch_dma_slave param_tx;
122 struct pch_dma_slave param_rx;
123 struct dma_chan *chan_tx;
124 struct dma_chan *chan_rx;
125 struct scatterlist *sg_tx_p;
126 struct scatterlist *sg_rx_p;
127 struct scatterlist sg_tx;
128 struct scatterlist sg_rx;
129 int nent;
130 void *tx_buf_virt;
131 void *rx_buf_virt;
132 dma_addr_t tx_buf_dma;
133 dma_addr_t rx_buf_dma;
134 };
135 /**
136 * struct pch_spi_data - Holds the SPI channel specific details
137 * @io_remap_addr: The remapped PCI base address
138 * @master: Pointer to the SPI master structure
139 * @work: Reference to work queue handler
140 * @wk: Workqueue for carrying out execution of the
141 * requests
142 * @wait: Wait queue for waking up upon receiving an
143 * interrupt.
144 * @transfer_complete: Status of SPI Transfer
145 * @bcurrent_msg_processing: Status flag for message processing
146 * @lock: Lock for protecting this structure
147 * @queue: SPI Message queue
148 * @status: Status of the SPI driver
149 * @bpw_len: Length of data to be transferred in bits per
150 * word
151 * @transfer_active: Flag showing active transfer
152 * @tx_index: Transmit data count; for bookkeeping during
153 * transfer
154 * @rx_index: Receive data count; for bookkeeping during
155 * transfer
156 * @tx_buff: Buffer for data to be transmitted
157 * @rx_index: Buffer for Received data
158 * @n_curnt_chip: The chip number that this SPI driver currently
159 * operates on
160 * @current_chip: Reference to the current chip that this SPI
161 * driver currently operates on
162 * @current_msg: The current message that this SPI driver is
163 * handling
164 * @cur_trans: The current transfer that this SPI driver is
165 * handling
166 * @board_dat: Reference to the SPI device data structure
167 * @plat_dev: platform_device structure
168 * @ch: SPI channel number
169 * @irq_reg_sts: Status of IRQ registration
170 */
171 struct pch_spi_data {
172 void __iomem *io_remap_addr;
173 unsigned long io_base_addr;
174 struct spi_master *master;
175 struct work_struct work;
176 struct workqueue_struct *wk;
177 wait_queue_head_t wait;
178 u8 transfer_complete;
179 u8 bcurrent_msg_processing;
180 spinlock_t lock;
181 struct list_head queue;
182 u8 status;
183 u32 bpw_len;
184 u8 transfer_active;
185 u32 tx_index;
186 u32 rx_index;
187 u16 *pkt_tx_buff;
188 u16 *pkt_rx_buff;
189 u8 n_curnt_chip;
190 struct spi_device *current_chip;
191 struct spi_message *current_msg;
192 struct spi_transfer *cur_trans;
193 struct pch_spi_board_data *board_dat;
194 struct platform_device *plat_dev;
195 int ch;
196 struct pch_spi_dma_ctrl dma;
197 int use_dma;
198 u8 irq_reg_sts;
199 int save_total_len;
200 };
201
202 /**
203 * struct pch_spi_board_data - Holds the SPI device specific details
204 * @pdev: Pointer to the PCI device
205 * @suspend_sts: Status of suspend
206 * @num: The number of SPI device instance
207 */
208 struct pch_spi_board_data {
209 struct pci_dev *pdev;
210 u8 suspend_sts;
211 int num;
212 };
213
214 struct pch_pd_dev_save {
215 int num;
216 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
217 struct pch_spi_board_data *board_dat;
218 };
219
220 static DEFINE_PCI_DEVICE_TABLE(pch_spi_pcidev_id) = {
221 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
224 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
225 { }
226 };
227
228 /**
229 * pch_spi_writereg() - Performs register writes
230 * @master: Pointer to struct spi_master.
231 * @idx: Register offset.
232 * @val: Value to be written to register.
233 */
234 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
235 {
236 struct pch_spi_data *data = spi_master_get_devdata(master);
237 iowrite32(val, (data->io_remap_addr + idx));
238 }
239
240 /**
241 * pch_spi_readreg() - Performs register reads
242 * @master: Pointer to struct spi_master.
243 * @idx: Register offset.
244 */
245 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
246 {
247 struct pch_spi_data *data = spi_master_get_devdata(master);
248 return ioread32(data->io_remap_addr + idx);
249 }
250
251 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
252 u32 set, u32 clr)
253 {
254 u32 tmp = pch_spi_readreg(master, idx);
255 tmp = (tmp & ~clr) | set;
256 pch_spi_writereg(master, idx, tmp);
257 }
258
259 static void pch_spi_set_master_mode(struct spi_master *master)
260 {
261 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
262 }
263
264 /**
265 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
266 * @master: Pointer to struct spi_master.
267 */
268 static void pch_spi_clear_fifo(struct spi_master *master)
269 {
270 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
271 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
272 }
273
274 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
275 void __iomem *io_remap_addr)
276 {
277 u32 n_read, tx_index, rx_index, bpw_len;
278 u16 *pkt_rx_buffer, *pkt_tx_buff;
279 int read_cnt;
280 u32 reg_spcr_val;
281 void __iomem *spsr;
282 void __iomem *spdrr;
283 void __iomem *spdwr;
284
285 spsr = io_remap_addr + PCH_SPSR;
286 iowrite32(reg_spsr_val, spsr);
287
288 if (data->transfer_active) {
289 rx_index = data->rx_index;
290 tx_index = data->tx_index;
291 bpw_len = data->bpw_len;
292 pkt_rx_buffer = data->pkt_rx_buff;
293 pkt_tx_buff = data->pkt_tx_buff;
294
295 spdrr = io_remap_addr + PCH_SPDRR;
296 spdwr = io_remap_addr + PCH_SPDWR;
297
298 n_read = PCH_READABLE(reg_spsr_val);
299
300 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
301 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
302 if (tx_index < bpw_len)
303 iowrite32(pkt_tx_buff[tx_index++], spdwr);
304 }
305
306 /* disable RFI if not needed */
307 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
308 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
309 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
310
311 /* reset rx threshold */
312 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
313 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
314
315 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
316 }
317
318 /* update counts */
319 data->tx_index = tx_index;
320 data->rx_index = rx_index;
321
322 /* if transfer complete interrupt */
323 if (reg_spsr_val & SPSR_FI_BIT) {
324 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
325 /* disable interrupts */
326 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
327 PCH_ALL);
328
329 /* transfer is completed;
330 inform pch_spi_process_messages */
331 data->transfer_complete = true;
332 data->transfer_active = false;
333 wake_up(&data->wait);
334 } else {
335 dev_err(&data->master->dev,
336 "%s : Transfer is not completed",
337 __func__);
338 }
339 }
340 }
341 }
342
343 /**
344 * pch_spi_handler() - Interrupt handler
345 * @irq: The interrupt number.
346 * @dev_id: Pointer to struct pch_spi_board_data.
347 */
348 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
349 {
350 u32 reg_spsr_val;
351 void __iomem *spsr;
352 void __iomem *io_remap_addr;
353 irqreturn_t ret = IRQ_NONE;
354 struct pch_spi_data *data = dev_id;
355 struct pch_spi_board_data *board_dat = data->board_dat;
356
357 if (board_dat->suspend_sts) {
358 dev_dbg(&board_dat->pdev->dev,
359 "%s returning due to suspend\n", __func__);
360 return IRQ_NONE;
361 }
362
363 io_remap_addr = data->io_remap_addr;
364 spsr = io_remap_addr + PCH_SPSR;
365
366 reg_spsr_val = ioread32(spsr);
367
368 if (reg_spsr_val & SPSR_ORF_BIT) {
369 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
370 if (data->current_msg->complete) {
371 data->transfer_complete = true;
372 data->current_msg->status = -EIO;
373 data->current_msg->complete(data->current_msg->context);
374 data->bcurrent_msg_processing = false;
375 data->current_msg = NULL;
376 data->cur_trans = NULL;
377 }
378 }
379
380 if (data->use_dma)
381 return IRQ_NONE;
382
383 /* Check if the interrupt is for SPI device */
384 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
385 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
386 ret = IRQ_HANDLED;
387 }
388
389 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
390 __func__, ret);
391
392 return ret;
393 }
394
395 /**
396 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
397 * @master: Pointer to struct spi_master.
398 * @speed_hz: Baud rate.
399 */
400 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
401 {
402 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
403
404 /* if baud rate is less than we can support limit it */
405 if (n_spbr > PCH_MAX_SPBR)
406 n_spbr = PCH_MAX_SPBR;
407
408 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
409 }
410
411 /**
412 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
413 * @master: Pointer to struct spi_master.
414 * @bits_per_word: Bits per word for SPI transfer.
415 */
416 static void pch_spi_set_bits_per_word(struct spi_master *master,
417 u8 bits_per_word)
418 {
419 if (bits_per_word == 8)
420 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
421 else
422 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
423 }
424
425 /**
426 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
427 * @spi: Pointer to struct spi_device.
428 */
429 static void pch_spi_setup_transfer(struct spi_device *spi)
430 {
431 u32 flags = 0;
432
433 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
434 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
435 spi->max_speed_hz);
436 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
437
438 /* set bits per word */
439 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
440
441 if (!(spi->mode & SPI_LSB_FIRST))
442 flags |= SPCR_LSBF_BIT;
443 if (spi->mode & SPI_CPOL)
444 flags |= SPCR_CPOL_BIT;
445 if (spi->mode & SPI_CPHA)
446 flags |= SPCR_CPHA_BIT;
447 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
448 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
449
450 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
451 pch_spi_clear_fifo(spi->master);
452 }
453
454 /**
455 * pch_spi_reset() - Clears SPI registers
456 * @master: Pointer to struct spi_master.
457 */
458 static void pch_spi_reset(struct spi_master *master)
459 {
460 /* write 1 to reset SPI */
461 pch_spi_writereg(master, PCH_SRST, 0x1);
462
463 /* clear reset */
464 pch_spi_writereg(master, PCH_SRST, 0x0);
465 }
466
467 static int pch_spi_setup(struct spi_device *pspi)
468 {
469 /* check bits per word */
470 if (pspi->bits_per_word == 0) {
471 pspi->bits_per_word = 8;
472 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
473 }
474
475 /* Check baud rate setting */
476 /* if baud rate of chip is greater than
477 max we can support,return error */
478 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
479 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
480
481 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
482 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
483
484 return 0;
485 }
486
487 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
488 {
489
490 struct spi_transfer *transfer;
491 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
492 int retval;
493 unsigned long flags;
494
495 /* validate spi message and baud rate */
496 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
497 dev_err(&pspi->dev, "%s list empty\n", __func__);
498 retval = -EINVAL;
499 goto err_out;
500 }
501
502 if (unlikely(pspi->max_speed_hz == 0)) {
503 dev_err(&pspi->dev, "%s pch_spi_transfer maxspeed=%d\n",
504 __func__, pspi->max_speed_hz);
505 retval = -EINVAL;
506 goto err_out;
507 }
508
509 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
510 "Transfer Speed is set.\n", __func__);
511
512 spin_lock_irqsave(&data->lock, flags);
513 /* validate Tx/Rx buffers and Transfer length */
514 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
515 if (!transfer->tx_buf && !transfer->rx_buf) {
516 dev_err(&pspi->dev,
517 "%s Tx and Rx buffer NULL\n", __func__);
518 retval = -EINVAL;
519 goto err_return_spinlock;
520 }
521
522 if (!transfer->len) {
523 dev_err(&pspi->dev, "%s Transfer length invalid\n",
524 __func__);
525 retval = -EINVAL;
526 goto err_return_spinlock;
527 }
528
529 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
530 " valid\n", __func__);
531
532 /* if baud rate has been specified validate the same */
533 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
534 transfer->speed_hz = PCH_MAX_BAUDRATE;
535 }
536 spin_unlock_irqrestore(&data->lock, flags);
537
538 /* We won't process any messages if we have been asked to terminate */
539 if (data->status == STATUS_EXITING) {
540 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
541 retval = -ESHUTDOWN;
542 goto err_out;
543 }
544
545 /* If suspended ,return -EINVAL */
546 if (data->board_dat->suspend_sts) {
547 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
548 retval = -EINVAL;
549 goto err_out;
550 }
551
552 /* set status of message */
553 pmsg->actual_length = 0;
554 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
555
556 pmsg->status = -EINPROGRESS;
557 spin_lock_irqsave(&data->lock, flags);
558 /* add message to queue */
559 list_add_tail(&pmsg->queue, &data->queue);
560 spin_unlock_irqrestore(&data->lock, flags);
561
562 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
563
564 /* schedule work queue to run */
565 queue_work(data->wk, &data->work);
566 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
567
568 retval = 0;
569
570 err_out:
571 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
572 return retval;
573 err_return_spinlock:
574 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
575 spin_unlock_irqrestore(&data->lock, flags);
576 return retval;
577 }
578
579 static inline void pch_spi_select_chip(struct pch_spi_data *data,
580 struct spi_device *pspi)
581 {
582 if (data->current_chip != NULL) {
583 if (pspi->chip_select != data->n_curnt_chip) {
584 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
585 data->current_chip = NULL;
586 }
587 }
588
589 data->current_chip = pspi;
590
591 data->n_curnt_chip = data->current_chip->chip_select;
592
593 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
594 pch_spi_setup_transfer(pspi);
595 }
596
597 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
598 {
599 int size;
600 u32 n_writes;
601 int j;
602 struct spi_message *pmsg, *tmp;
603 const u8 *tx_buf;
604 const u16 *tx_sbuf;
605
606 /* set baud rate if needed */
607 if (data->cur_trans->speed_hz) {
608 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
609 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
610 }
611
612 /* set bits per word if needed */
613 if (data->cur_trans->bits_per_word &&
614 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
615 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
616 pch_spi_set_bits_per_word(data->master,
617 data->cur_trans->bits_per_word);
618 *bpw = data->cur_trans->bits_per_word;
619 } else {
620 *bpw = data->current_msg->spi->bits_per_word;
621 }
622
623 /* reset Tx/Rx index */
624 data->tx_index = 0;
625 data->rx_index = 0;
626
627 data->bpw_len = data->cur_trans->len / (*bpw / 8);
628
629 /* find alloc size */
630 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
631
632 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
633 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
634 if (data->pkt_tx_buff != NULL) {
635 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
636 if (!data->pkt_rx_buff)
637 kfree(data->pkt_tx_buff);
638 }
639
640 if (!data->pkt_rx_buff) {
641 /* flush queue and set status of all transfers to -ENOMEM */
642 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
643 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
644 pmsg->status = -ENOMEM;
645
646 if (pmsg->complete)
647 pmsg->complete(pmsg->context);
648
649 /* delete from queue */
650 list_del_init(&pmsg->queue);
651 }
652 return;
653 }
654
655 /* copy Tx Data */
656 if (data->cur_trans->tx_buf != NULL) {
657 if (*bpw == 8) {
658 tx_buf = data->cur_trans->tx_buf;
659 for (j = 0; j < data->bpw_len; j++)
660 data->pkt_tx_buff[j] = *tx_buf++;
661 } else {
662 tx_sbuf = data->cur_trans->tx_buf;
663 for (j = 0; j < data->bpw_len; j++)
664 data->pkt_tx_buff[j] = *tx_sbuf++;
665 }
666 }
667
668 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
669 n_writes = data->bpw_len;
670 if (n_writes > PCH_MAX_FIFO_DEPTH)
671 n_writes = PCH_MAX_FIFO_DEPTH;
672
673 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
674 "0x2 to SSNXCR\n", __func__);
675 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
676
677 for (j = 0; j < n_writes; j++)
678 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
679
680 /* update tx_index */
681 data->tx_index = j;
682
683 /* reset transfer complete flag */
684 data->transfer_complete = false;
685 data->transfer_active = true;
686 }
687
688 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
689 {
690 struct spi_message *pmsg, *tmp;
691 dev_dbg(&data->master->dev, "%s called\n", __func__);
692 /* Invoke complete callback
693 * [To the spi core..indicating end of transfer] */
694 data->current_msg->status = 0;
695
696 if (data->current_msg->complete) {
697 dev_dbg(&data->master->dev,
698 "%s:Invoking callback of SPI core\n", __func__);
699 data->current_msg->complete(data->current_msg->context);
700 }
701
702 /* update status in global variable */
703 data->bcurrent_msg_processing = false;
704
705 dev_dbg(&data->master->dev,
706 "%s:data->bcurrent_msg_processing = false\n", __func__);
707
708 data->current_msg = NULL;
709 data->cur_trans = NULL;
710
711 /* check if we have items in list and not suspending
712 * return 1 if list empty */
713 if ((list_empty(&data->queue) == 0) &&
714 (!data->board_dat->suspend_sts) &&
715 (data->status != STATUS_EXITING)) {
716 /* We have some more work to do (either there is more tranint
717 * bpw;sfer requests in the current message or there are
718 *more messages)
719 */
720 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
721 queue_work(data->wk, &data->work);
722 } else if (data->board_dat->suspend_sts ||
723 data->status == STATUS_EXITING) {
724 dev_dbg(&data->master->dev,
725 "%s suspend/remove initiated, flushing queue\n",
726 __func__);
727 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
728 pmsg->status = -EIO;
729
730 if (pmsg->complete)
731 pmsg->complete(pmsg->context);
732
733 /* delete from queue */
734 list_del_init(&pmsg->queue);
735 }
736 }
737 }
738
739 static void pch_spi_set_ir(struct pch_spi_data *data)
740 {
741 /* enable interrupts, set threshold, enable SPI */
742 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
743 /* set receive threshold to PCH_RX_THOLD */
744 pch_spi_setclr_reg(data->master, PCH_SPCR,
745 PCH_RX_THOLD << SPCR_RFIC_FIELD |
746 SPCR_FIE_BIT | SPCR_RFIE_BIT |
747 SPCR_ORIE_BIT | SPCR_SPE_BIT,
748 MASK_RFIC_SPCR_BITS | PCH_ALL);
749 else
750 /* set receive threshold to maximum */
751 pch_spi_setclr_reg(data->master, PCH_SPCR,
752 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
753 SPCR_FIE_BIT | SPCR_ORIE_BIT |
754 SPCR_SPE_BIT,
755 MASK_RFIC_SPCR_BITS | PCH_ALL);
756
757 /* Wait until the transfer completes; go to sleep after
758 initiating the transfer. */
759 dev_dbg(&data->master->dev,
760 "%s:waiting for transfer to get over\n", __func__);
761
762 wait_event_interruptible(data->wait, data->transfer_complete);
763
764 /* clear all interrupts */
765 pch_spi_writereg(data->master, PCH_SPSR,
766 pch_spi_readreg(data->master, PCH_SPSR));
767 /* Disable interrupts and SPI transfer */
768 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
769 /* clear FIFO */
770 pch_spi_clear_fifo(data->master);
771 }
772
773 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
774 {
775 int j;
776 u8 *rx_buf;
777 u16 *rx_sbuf;
778
779 /* copy Rx Data */
780 if (!data->cur_trans->rx_buf)
781 return;
782
783 if (bpw == 8) {
784 rx_buf = data->cur_trans->rx_buf;
785 for (j = 0; j < data->bpw_len; j++)
786 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
787 } else {
788 rx_sbuf = data->cur_trans->rx_buf;
789 for (j = 0; j < data->bpw_len; j++)
790 *rx_sbuf++ = data->pkt_rx_buff[j];
791 }
792 }
793
794 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
795 {
796 int j;
797 u8 *rx_buf;
798 u16 *rx_sbuf;
799 const u8 *rx_dma_buf;
800 const u16 *rx_dma_sbuf;
801
802 /* copy Rx Data */
803 if (!data->cur_trans->rx_buf)
804 return;
805
806 if (bpw == 8) {
807 rx_buf = data->cur_trans->rx_buf;
808 rx_dma_buf = data->dma.rx_buf_virt;
809 for (j = 0; j < data->bpw_len; j++)
810 *rx_buf++ = *rx_dma_buf++ & 0xFF;
811 data->cur_trans->rx_buf = rx_buf;
812 } else {
813 rx_sbuf = data->cur_trans->rx_buf;
814 rx_dma_sbuf = data->dma.rx_buf_virt;
815 for (j = 0; j < data->bpw_len; j++)
816 *rx_sbuf++ = *rx_dma_sbuf++;
817 data->cur_trans->rx_buf = rx_sbuf;
818 }
819 }
820
821 static int pch_spi_start_transfer(struct pch_spi_data *data)
822 {
823 struct pch_spi_dma_ctrl *dma;
824 unsigned long flags;
825 int rtn;
826
827 dma = &data->dma;
828
829 spin_lock_irqsave(&data->lock, flags);
830
831 /* disable interrupts, SPI set enable */
832 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
833
834 spin_unlock_irqrestore(&data->lock, flags);
835
836 /* Wait until the transfer completes; go to sleep after
837 initiating the transfer. */
838 dev_dbg(&data->master->dev,
839 "%s:waiting for transfer to get over\n", __func__);
840 rtn = wait_event_interruptible_timeout(data->wait,
841 data->transfer_complete,
842 msecs_to_jiffies(2 * HZ));
843 if (!rtn)
844 dev_err(&data->master->dev,
845 "%s wait-event timeout\n", __func__);
846
847 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
848 DMA_FROM_DEVICE);
849
850 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
851 DMA_FROM_DEVICE);
852 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
853
854 async_tx_ack(dma->desc_rx);
855 async_tx_ack(dma->desc_tx);
856 kfree(dma->sg_tx_p);
857 kfree(dma->sg_rx_p);
858
859 spin_lock_irqsave(&data->lock, flags);
860
861 /* clear fifo threshold, disable interrupts, disable SPI transfer */
862 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
863 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
864 SPCR_SPE_BIT);
865 /* clear all interrupts */
866 pch_spi_writereg(data->master, PCH_SPSR,
867 pch_spi_readreg(data->master, PCH_SPSR));
868 /* clear FIFO */
869 pch_spi_clear_fifo(data->master);
870
871 spin_unlock_irqrestore(&data->lock, flags);
872
873 return rtn;
874 }
875
876 static void pch_dma_rx_complete(void *arg)
877 {
878 struct pch_spi_data *data = arg;
879
880 /* transfer is completed;inform pch_spi_process_messages_dma */
881 data->transfer_complete = true;
882 wake_up_interruptible(&data->wait);
883 }
884
885 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
886 {
887 struct pch_dma_slave *param = slave;
888
889 if ((chan->chan_id == param->chan_id) &&
890 (param->dma_dev == chan->device->dev)) {
891 chan->private = param;
892 return true;
893 } else {
894 return false;
895 }
896 }
897
898 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
899 {
900 dma_cap_mask_t mask;
901 struct dma_chan *chan;
902 struct pci_dev *dma_dev;
903 struct pch_dma_slave *param;
904 struct pch_spi_dma_ctrl *dma;
905 unsigned int width;
906
907 if (bpw == 8)
908 width = PCH_DMA_WIDTH_1_BYTE;
909 else
910 width = PCH_DMA_WIDTH_2_BYTES;
911
912 dma = &data->dma;
913 dma_cap_zero(mask);
914 dma_cap_set(DMA_SLAVE, mask);
915
916 /* Get DMA's dev information */
917 dma_dev = pci_get_bus_and_slot(data->board_dat->pdev->bus->number,
918 PCI_DEVFN(12, 0));
919
920 /* Set Tx DMA */
921 param = &dma->param_tx;
922 param->dma_dev = &dma_dev->dev;
923 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
924 param->tx_reg = data->io_base_addr + PCH_SPDWR;
925 param->width = width;
926 chan = dma_request_channel(mask, pch_spi_filter, param);
927 if (!chan) {
928 dev_err(&data->master->dev,
929 "ERROR: dma_request_channel FAILS(Tx)\n");
930 data->use_dma = 0;
931 return;
932 }
933 dma->chan_tx = chan;
934
935 /* Set Rx DMA */
936 param = &dma->param_rx;
937 param->dma_dev = &dma_dev->dev;
938 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
939 param->rx_reg = data->io_base_addr + PCH_SPDRR;
940 param->width = width;
941 chan = dma_request_channel(mask, pch_spi_filter, param);
942 if (!chan) {
943 dev_err(&data->master->dev,
944 "ERROR: dma_request_channel FAILS(Rx)\n");
945 dma_release_channel(dma->chan_tx);
946 dma->chan_tx = NULL;
947 data->use_dma = 0;
948 return;
949 }
950 dma->chan_rx = chan;
951 }
952
953 static void pch_spi_release_dma(struct pch_spi_data *data)
954 {
955 struct pch_spi_dma_ctrl *dma;
956
957 dma = &data->dma;
958 if (dma->chan_tx) {
959 dma_release_channel(dma->chan_tx);
960 dma->chan_tx = NULL;
961 }
962 if (dma->chan_rx) {
963 dma_release_channel(dma->chan_rx);
964 dma->chan_rx = NULL;
965 }
966 return;
967 }
968
969 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
970 {
971 const u8 *tx_buf;
972 const u16 *tx_sbuf;
973 u8 *tx_dma_buf;
974 u16 *tx_dma_sbuf;
975 struct scatterlist *sg;
976 struct dma_async_tx_descriptor *desc_tx;
977 struct dma_async_tx_descriptor *desc_rx;
978 int num;
979 int i;
980 int size;
981 int rem;
982 int head;
983 unsigned long flags;
984 struct pch_spi_dma_ctrl *dma;
985
986 dma = &data->dma;
987
988 /* set baud rate if needed */
989 if (data->cur_trans->speed_hz) {
990 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
991 spin_lock_irqsave(&data->lock, flags);
992 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
993 spin_unlock_irqrestore(&data->lock, flags);
994 }
995
996 /* set bits per word if needed */
997 if (data->cur_trans->bits_per_word &&
998 (data->current_msg->spi->bits_per_word !=
999 data->cur_trans->bits_per_word)) {
1000 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
1001 spin_lock_irqsave(&data->lock, flags);
1002 pch_spi_set_bits_per_word(data->master,
1003 data->cur_trans->bits_per_word);
1004 spin_unlock_irqrestore(&data->lock, flags);
1005 *bpw = data->cur_trans->bits_per_word;
1006 } else {
1007 *bpw = data->current_msg->spi->bits_per_word;
1008 }
1009 data->bpw_len = data->cur_trans->len / (*bpw / 8);
1010
1011 if (data->bpw_len > PCH_BUF_SIZE) {
1012 data->bpw_len = PCH_BUF_SIZE;
1013 data->cur_trans->len -= PCH_BUF_SIZE;
1014 }
1015
1016 /* copy Tx Data */
1017 if (data->cur_trans->tx_buf != NULL) {
1018 if (*bpw == 8) {
1019 tx_buf = data->cur_trans->tx_buf;
1020 tx_dma_buf = dma->tx_buf_virt;
1021 for (i = 0; i < data->bpw_len; i++)
1022 *tx_dma_buf++ = *tx_buf++;
1023 } else {
1024 tx_sbuf = data->cur_trans->tx_buf;
1025 tx_dma_sbuf = dma->tx_buf_virt;
1026 for (i = 0; i < data->bpw_len; i++)
1027 *tx_dma_sbuf++ = *tx_sbuf++;
1028 }
1029 }
1030
1031 /* Calculate Rx parameter for DMA transmitting */
1032 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1033 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
1034 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1035 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1036 } else {
1037 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1038 rem = PCH_DMA_TRANS_SIZE;
1039 }
1040 size = PCH_DMA_TRANS_SIZE;
1041 } else {
1042 num = 1;
1043 size = data->bpw_len;
1044 rem = data->bpw_len;
1045 }
1046 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1047 __func__, num, size, rem);
1048 spin_lock_irqsave(&data->lock, flags);
1049
1050 /* set receive fifo threshold and transmit fifo threshold */
1051 pch_spi_setclr_reg(data->master, PCH_SPCR,
1052 ((size - 1) << SPCR_RFIC_FIELD) |
1053 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1054 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1055
1056 spin_unlock_irqrestore(&data->lock, flags);
1057
1058 /* RX */
1059 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1060 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1061 /* offset, length setting */
1062 sg = dma->sg_rx_p;
1063 for (i = 0; i < num; i++, sg++) {
1064 if (i == (num - 2)) {
1065 sg->offset = size * i;
1066 sg->offset = sg->offset * (*bpw / 8);
1067 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1068 sg->offset);
1069 sg_dma_len(sg) = rem;
1070 } else if (i == (num - 1)) {
1071 sg->offset = size * (i - 1) + rem;
1072 sg->offset = sg->offset * (*bpw / 8);
1073 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1074 sg->offset);
1075 sg_dma_len(sg) = size;
1076 } else {
1077 sg->offset = size * i;
1078 sg->offset = sg->offset * (*bpw / 8);
1079 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1080 sg->offset);
1081 sg_dma_len(sg) = size;
1082 }
1083 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1084 }
1085 sg = dma->sg_rx_p;
1086 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1087 num, DMA_DEV_TO_MEM,
1088 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1089 if (!desc_rx) {
1090 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1091 __func__);
1092 return;
1093 }
1094 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1095 desc_rx->callback = pch_dma_rx_complete;
1096 desc_rx->callback_param = data;
1097 dma->nent = num;
1098 dma->desc_rx = desc_rx;
1099
1100 /* Calculate Tx parameter for DMA transmitting */
1101 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1102 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1103 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1104 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1105 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1106 } else {
1107 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1108 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1109 PCH_DMA_TRANS_SIZE - head;
1110 }
1111 size = PCH_DMA_TRANS_SIZE;
1112 } else {
1113 num = 1;
1114 size = data->bpw_len;
1115 rem = data->bpw_len;
1116 head = 0;
1117 }
1118
1119 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1120 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1121 /* offset, length setting */
1122 sg = dma->sg_tx_p;
1123 for (i = 0; i < num; i++, sg++) {
1124 if (i == 0) {
1125 sg->offset = 0;
1126 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1127 sg->offset);
1128 sg_dma_len(sg) = size + head;
1129 } else if (i == (num - 1)) {
1130 sg->offset = head + size * i;
1131 sg->offset = sg->offset * (*bpw / 8);
1132 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1133 sg->offset);
1134 sg_dma_len(sg) = rem;
1135 } else {
1136 sg->offset = head + size * i;
1137 sg->offset = sg->offset * (*bpw / 8);
1138 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1139 sg->offset);
1140 sg_dma_len(sg) = size;
1141 }
1142 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1143 }
1144 sg = dma->sg_tx_p;
1145 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1146 sg, num, DMA_MEM_TO_DEV,
1147 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1148 if (!desc_tx) {
1149 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1150 __func__);
1151 return;
1152 }
1153 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1154 desc_tx->callback = NULL;
1155 desc_tx->callback_param = data;
1156 dma->nent = num;
1157 dma->desc_tx = desc_tx;
1158
1159 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1160 "0x2 to SSNXCR\n", __func__);
1161
1162 spin_lock_irqsave(&data->lock, flags);
1163 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1164 desc_rx->tx_submit(desc_rx);
1165 desc_tx->tx_submit(desc_tx);
1166 spin_unlock_irqrestore(&data->lock, flags);
1167
1168 /* reset transfer complete flag */
1169 data->transfer_complete = false;
1170 }
1171
1172 static void pch_spi_process_messages(struct work_struct *pwork)
1173 {
1174 struct spi_message *pmsg, *tmp;
1175 struct pch_spi_data *data;
1176 int bpw;
1177
1178 data = container_of(pwork, struct pch_spi_data, work);
1179 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1180
1181 spin_lock(&data->lock);
1182 /* check if suspend has been initiated;if yes flush queue */
1183 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1184 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1185 "flushing queue\n", __func__);
1186 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1187 pmsg->status = -EIO;
1188
1189 if (pmsg->complete) {
1190 spin_unlock(&data->lock);
1191 pmsg->complete(pmsg->context);
1192 spin_lock(&data->lock);
1193 }
1194
1195 /* delete from queue */
1196 list_del_init(&pmsg->queue);
1197 }
1198
1199 spin_unlock(&data->lock);
1200 return;
1201 }
1202
1203 data->bcurrent_msg_processing = true;
1204 dev_dbg(&data->master->dev,
1205 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1206
1207 /* Get the message from the queue and delete it from there. */
1208 data->current_msg = list_entry(data->queue.next, struct spi_message,
1209 queue);
1210
1211 list_del_init(&data->current_msg->queue);
1212
1213 data->current_msg->status = 0;
1214
1215 pch_spi_select_chip(data, data->current_msg->spi);
1216
1217 spin_unlock(&data->lock);
1218
1219 if (data->use_dma)
1220 pch_spi_request_dma(data,
1221 data->current_msg->spi->bits_per_word);
1222 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1223 do {
1224 int cnt;
1225 /* If we are already processing a message get the next
1226 transfer structure from the message otherwise retrieve
1227 the 1st transfer request from the message. */
1228 spin_lock(&data->lock);
1229 if (data->cur_trans == NULL) {
1230 data->cur_trans =
1231 list_entry(data->current_msg->transfers.next,
1232 struct spi_transfer, transfer_list);
1233 dev_dbg(&data->master->dev, "%s "
1234 ":Getting 1st transfer message\n", __func__);
1235 } else {
1236 data->cur_trans =
1237 list_entry(data->cur_trans->transfer_list.next,
1238 struct spi_transfer, transfer_list);
1239 dev_dbg(&data->master->dev, "%s "
1240 ":Getting next transfer message\n", __func__);
1241 }
1242 spin_unlock(&data->lock);
1243
1244 if (!data->cur_trans->len)
1245 goto out;
1246 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1247 data->save_total_len = data->cur_trans->len;
1248 if (data->use_dma) {
1249 int i;
1250 char *save_rx_buf = data->cur_trans->rx_buf;
1251 for (i = 0; i < cnt; i ++) {
1252 pch_spi_handle_dma(data, &bpw);
1253 if (!pch_spi_start_transfer(data)) {
1254 data->transfer_complete = true;
1255 data->current_msg->status = -EIO;
1256 data->current_msg->complete
1257 (data->current_msg->context);
1258 data->bcurrent_msg_processing = false;
1259 data->current_msg = NULL;
1260 data->cur_trans = NULL;
1261 goto out;
1262 }
1263 pch_spi_copy_rx_data_for_dma(data, bpw);
1264 }
1265 data->cur_trans->rx_buf = save_rx_buf;
1266 } else {
1267 pch_spi_set_tx(data, &bpw);
1268 pch_spi_set_ir(data);
1269 pch_spi_copy_rx_data(data, bpw);
1270 kfree(data->pkt_rx_buff);
1271 data->pkt_rx_buff = NULL;
1272 kfree(data->pkt_tx_buff);
1273 data->pkt_tx_buff = NULL;
1274 }
1275 /* increment message count */
1276 data->cur_trans->len = data->save_total_len;
1277 data->current_msg->actual_length += data->cur_trans->len;
1278
1279 dev_dbg(&data->master->dev,
1280 "%s:data->current_msg->actual_length=%d\n",
1281 __func__, data->current_msg->actual_length);
1282
1283 /* check for delay */
1284 if (data->cur_trans->delay_usecs) {
1285 dev_dbg(&data->master->dev, "%s:"
1286 "delay in usec=%d\n", __func__,
1287 data->cur_trans->delay_usecs);
1288 udelay(data->cur_trans->delay_usecs);
1289 }
1290
1291 spin_lock(&data->lock);
1292
1293 /* No more transfer in this message. */
1294 if ((data->cur_trans->transfer_list.next) ==
1295 &(data->current_msg->transfers)) {
1296 pch_spi_nomore_transfer(data);
1297 }
1298
1299 spin_unlock(&data->lock);
1300
1301 } while (data->cur_trans != NULL);
1302
1303 out:
1304 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1305 if (data->use_dma)
1306 pch_spi_release_dma(data);
1307 }
1308
1309 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1310 struct pch_spi_data *data)
1311 {
1312 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1313
1314 /* free workqueue */
1315 if (data->wk != NULL) {
1316 destroy_workqueue(data->wk);
1317 data->wk = NULL;
1318 dev_dbg(&board_dat->pdev->dev,
1319 "%s destroy_workqueue invoked successfully\n",
1320 __func__);
1321 }
1322 }
1323
1324 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1325 struct pch_spi_data *data)
1326 {
1327 int retval = 0;
1328
1329 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1330
1331 /* create workqueue */
1332 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1333 if (!data->wk) {
1334 dev_err(&board_dat->pdev->dev,
1335 "%s create_singlet hread_workqueue failed\n", __func__);
1336 retval = -EBUSY;
1337 goto err_return;
1338 }
1339
1340 /* reset PCH SPI h/w */
1341 pch_spi_reset(data->master);
1342 dev_dbg(&board_dat->pdev->dev,
1343 "%s pch_spi_reset invoked successfully\n", __func__);
1344
1345 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1346
1347 err_return:
1348 if (retval != 0) {
1349 dev_err(&board_dat->pdev->dev,
1350 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1351 pch_spi_free_resources(board_dat, data);
1352 }
1353
1354 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1355
1356 return retval;
1357 }
1358
1359 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1360 struct pch_spi_data *data)
1361 {
1362 struct pch_spi_dma_ctrl *dma;
1363
1364 dma = &data->dma;
1365 if (dma->tx_buf_dma)
1366 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1367 dma->tx_buf_virt, dma->tx_buf_dma);
1368 if (dma->rx_buf_dma)
1369 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1370 dma->rx_buf_virt, dma->rx_buf_dma);
1371 return;
1372 }
1373
1374 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1375 struct pch_spi_data *data)
1376 {
1377 struct pch_spi_dma_ctrl *dma;
1378
1379 dma = &data->dma;
1380 /* Get Consistent memory for Tx DMA */
1381 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1382 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1383 /* Get Consistent memory for Rx DMA */
1384 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1385 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1386 }
1387
1388 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1389 {
1390 int ret;
1391 struct spi_master *master;
1392 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1393 struct pch_spi_data *data;
1394
1395 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1396
1397 master = spi_alloc_master(&board_dat->pdev->dev,
1398 sizeof(struct pch_spi_data));
1399 if (!master) {
1400 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1401 plat_dev->id);
1402 return -ENOMEM;
1403 }
1404
1405 data = spi_master_get_devdata(master);
1406 data->master = master;
1407
1408 platform_set_drvdata(plat_dev, data);
1409
1410 /* baseaddress + address offset) */
1411 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1412 PCH_ADDRESS_SIZE * plat_dev->id;
1413 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1414 PCH_ADDRESS_SIZE * plat_dev->id;
1415 if (!data->io_remap_addr) {
1416 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1417 ret = -ENOMEM;
1418 goto err_pci_iomap;
1419 }
1420
1421 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1422 plat_dev->id, data->io_remap_addr);
1423
1424 /* initialize members of SPI master */
1425 master->num_chipselect = PCH_MAX_CS;
1426 master->setup = pch_spi_setup;
1427 master->transfer = pch_spi_transfer;
1428 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1429 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1430
1431 data->board_dat = board_dat;
1432 data->plat_dev = plat_dev;
1433 data->n_curnt_chip = 255;
1434 data->status = STATUS_RUNNING;
1435 data->ch = plat_dev->id;
1436 data->use_dma = use_dma;
1437
1438 INIT_LIST_HEAD(&data->queue);
1439 spin_lock_init(&data->lock);
1440 INIT_WORK(&data->work, pch_spi_process_messages);
1441 init_waitqueue_head(&data->wait);
1442
1443 ret = pch_spi_get_resources(board_dat, data);
1444 if (ret) {
1445 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1446 goto err_spi_get_resources;
1447 }
1448
1449 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1450 IRQF_SHARED, KBUILD_MODNAME, data);
1451 if (ret) {
1452 dev_err(&plat_dev->dev,
1453 "%s request_irq failed\n", __func__);
1454 goto err_request_irq;
1455 }
1456 data->irq_reg_sts = true;
1457
1458 pch_spi_set_master_mode(master);
1459
1460 ret = spi_register_master(master);
1461 if (ret != 0) {
1462 dev_err(&plat_dev->dev,
1463 "%s spi_register_master FAILED\n", __func__);
1464 goto err_spi_register_master;
1465 }
1466
1467 if (use_dma) {
1468 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1469 pch_alloc_dma_buf(board_dat, data);
1470 }
1471
1472 return 0;
1473
1474 err_spi_register_master:
1475 free_irq(board_dat->pdev->irq, data);
1476 err_request_irq:
1477 pch_spi_free_resources(board_dat, data);
1478 err_spi_get_resources:
1479 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1480 err_pci_iomap:
1481 spi_master_put(master);
1482
1483 return ret;
1484 }
1485
1486 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1487 {
1488 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1489 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1490 int count;
1491 unsigned long flags;
1492
1493 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1494 __func__, plat_dev->id, board_dat->pdev->irq);
1495
1496 if (use_dma)
1497 pch_free_dma_buf(board_dat, data);
1498
1499 /* check for any pending messages; no action is taken if the queue
1500 * is still full; but at least we tried. Unload anyway */
1501 count = 500;
1502 spin_lock_irqsave(&data->lock, flags);
1503 data->status = STATUS_EXITING;
1504 while ((list_empty(&data->queue) == 0) && --count) {
1505 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1506 __func__);
1507 spin_unlock_irqrestore(&data->lock, flags);
1508 msleep(PCH_SLEEP_TIME);
1509 spin_lock_irqsave(&data->lock, flags);
1510 }
1511 spin_unlock_irqrestore(&data->lock, flags);
1512
1513 pch_spi_free_resources(board_dat, data);
1514 /* disable interrupts & free IRQ */
1515 if (data->irq_reg_sts) {
1516 /* disable interrupts */
1517 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1518 data->irq_reg_sts = false;
1519 free_irq(board_dat->pdev->irq, data);
1520 }
1521
1522 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1523 spi_unregister_master(data->master);
1524
1525 return 0;
1526 }
1527 #ifdef CONFIG_PM
1528 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1529 pm_message_t state)
1530 {
1531 u8 count;
1532 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1533 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1534
1535 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1536
1537 if (!board_dat) {
1538 dev_err(&pd_dev->dev,
1539 "%s pci_get_drvdata returned NULL\n", __func__);
1540 return -EFAULT;
1541 }
1542
1543 /* check if the current message is processed:
1544 Only after thats done the transfer will be suspended */
1545 count = 255;
1546 while ((--count) > 0) {
1547 if (!(data->bcurrent_msg_processing))
1548 break;
1549 msleep(PCH_SLEEP_TIME);
1550 }
1551
1552 /* Free IRQ */
1553 if (data->irq_reg_sts) {
1554 /* disable all interrupts */
1555 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1556 pch_spi_reset(data->master);
1557 free_irq(board_dat->pdev->irq, data);
1558
1559 data->irq_reg_sts = false;
1560 dev_dbg(&pd_dev->dev,
1561 "%s free_irq invoked successfully.\n", __func__);
1562 }
1563
1564 return 0;
1565 }
1566
1567 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1568 {
1569 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1570 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1571 int retval;
1572
1573 if (!board_dat) {
1574 dev_err(&pd_dev->dev,
1575 "%s pci_get_drvdata returned NULL\n", __func__);
1576 return -EFAULT;
1577 }
1578
1579 if (!data->irq_reg_sts) {
1580 /* register IRQ */
1581 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1582 IRQF_SHARED, KBUILD_MODNAME, data);
1583 if (retval < 0) {
1584 dev_err(&pd_dev->dev,
1585 "%s request_irq failed\n", __func__);
1586 return retval;
1587 }
1588
1589 /* reset PCH SPI h/w */
1590 pch_spi_reset(data->master);
1591 pch_spi_set_master_mode(data->master);
1592 data->irq_reg_sts = true;
1593 }
1594 return 0;
1595 }
1596 #else
1597 #define pch_spi_pd_suspend NULL
1598 #define pch_spi_pd_resume NULL
1599 #endif
1600
1601 static struct platform_driver pch_spi_pd_driver = {
1602 .driver = {
1603 .name = "pch-spi",
1604 .owner = THIS_MODULE,
1605 },
1606 .probe = pch_spi_pd_probe,
1607 .remove = pch_spi_pd_remove,
1608 .suspend = pch_spi_pd_suspend,
1609 .resume = pch_spi_pd_resume
1610 };
1611
1612 static int pch_spi_probe(struct pci_dev *pdev,
1613 const struct pci_device_id *id)
1614 {
1615 struct pch_spi_board_data *board_dat;
1616 struct platform_device *pd_dev = NULL;
1617 int retval;
1618 int i;
1619 struct pch_pd_dev_save *pd_dev_save;
1620
1621 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1622 if (!pd_dev_save) {
1623 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1624 return -ENOMEM;
1625 }
1626
1627 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1628 if (!board_dat) {
1629 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1630 retval = -ENOMEM;
1631 goto err_no_mem;
1632 }
1633
1634 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1635 if (retval) {
1636 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1637 goto pci_request_regions;
1638 }
1639
1640 board_dat->pdev = pdev;
1641 board_dat->num = id->driver_data;
1642 pd_dev_save->num = id->driver_data;
1643 pd_dev_save->board_dat = board_dat;
1644
1645 retval = pci_enable_device(pdev);
1646 if (retval) {
1647 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1648 goto pci_enable_device;
1649 }
1650
1651 for (i = 0; i < board_dat->num; i++) {
1652 pd_dev = platform_device_alloc("pch-spi", i);
1653 if (!pd_dev) {
1654 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1655 retval = -ENOMEM;
1656 goto err_platform_device;
1657 }
1658 pd_dev_save->pd_save[i] = pd_dev;
1659 pd_dev->dev.parent = &pdev->dev;
1660
1661 retval = platform_device_add_data(pd_dev, board_dat,
1662 sizeof(*board_dat));
1663 if (retval) {
1664 dev_err(&pdev->dev,
1665 "platform_device_add_data failed\n");
1666 platform_device_put(pd_dev);
1667 goto err_platform_device;
1668 }
1669
1670 retval = platform_device_add(pd_dev);
1671 if (retval) {
1672 dev_err(&pdev->dev, "platform_device_add failed\n");
1673 platform_device_put(pd_dev);
1674 goto err_platform_device;
1675 }
1676 }
1677
1678 pci_set_drvdata(pdev, pd_dev_save);
1679
1680 return 0;
1681
1682 err_platform_device:
1683 pci_disable_device(pdev);
1684 pci_enable_device:
1685 pci_release_regions(pdev);
1686 pci_request_regions:
1687 kfree(board_dat);
1688 err_no_mem:
1689 kfree(pd_dev_save);
1690
1691 return retval;
1692 }
1693
1694 static void pch_spi_remove(struct pci_dev *pdev)
1695 {
1696 int i;
1697 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1698
1699 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1700
1701 for (i = 0; i < pd_dev_save->num; i++)
1702 platform_device_unregister(pd_dev_save->pd_save[i]);
1703
1704 pci_disable_device(pdev);
1705 pci_release_regions(pdev);
1706 kfree(pd_dev_save->board_dat);
1707 kfree(pd_dev_save);
1708 }
1709
1710 #ifdef CONFIG_PM
1711 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1712 {
1713 int retval;
1714 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1715
1716 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1717
1718 pd_dev_save->board_dat->suspend_sts = true;
1719
1720 /* save config space */
1721 retval = pci_save_state(pdev);
1722 if (retval == 0) {
1723 pci_enable_wake(pdev, PCI_D3hot, 0);
1724 pci_disable_device(pdev);
1725 pci_set_power_state(pdev, PCI_D3hot);
1726 } else {
1727 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1728 }
1729
1730 return retval;
1731 }
1732
1733 static int pch_spi_resume(struct pci_dev *pdev)
1734 {
1735 int retval;
1736 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1737 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1738
1739 pci_set_power_state(pdev, PCI_D0);
1740 pci_restore_state(pdev);
1741
1742 retval = pci_enable_device(pdev);
1743 if (retval < 0) {
1744 dev_err(&pdev->dev,
1745 "%s pci_enable_device failed\n", __func__);
1746 } else {
1747 pci_enable_wake(pdev, PCI_D3hot, 0);
1748
1749 /* set suspend status to false */
1750 pd_dev_save->board_dat->suspend_sts = false;
1751 }
1752
1753 return retval;
1754 }
1755 #else
1756 #define pch_spi_suspend NULL
1757 #define pch_spi_resume NULL
1758
1759 #endif
1760
1761 static struct pci_driver pch_spi_pcidev_driver = {
1762 .name = "pch_spi",
1763 .id_table = pch_spi_pcidev_id,
1764 .probe = pch_spi_probe,
1765 .remove = pch_spi_remove,
1766 .suspend = pch_spi_suspend,
1767 .resume = pch_spi_resume,
1768 };
1769
1770 static int __init pch_spi_init(void)
1771 {
1772 int ret;
1773 ret = platform_driver_register(&pch_spi_pd_driver);
1774 if (ret)
1775 return ret;
1776
1777 ret = pci_register_driver(&pch_spi_pcidev_driver);
1778 if (ret) {
1779 platform_driver_unregister(&pch_spi_pd_driver);
1780 return ret;
1781 }
1782
1783 return 0;
1784 }
1785 module_init(pch_spi_init);
1786
1787 static void __exit pch_spi_exit(void)
1788 {
1789 pci_unregister_driver(&pch_spi_pcidev_driver);
1790 platform_driver_unregister(&pch_spi_pd_driver);
1791 }
1792 module_exit(pch_spi_exit);
1793
1794 module_param(use_dma, int, 0644);
1795 MODULE_PARM_DESC(use_dma,
1796 "to use DMA for data transfers pass 1 else 0; default 1");
1797
1798 MODULE_LICENSE("GPL");
1799 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1800 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1801
Linux with added FPC-III support