drivers/staging/comedi/comedi.h

   1 /*
   2     include/comedi.h (installed as /usr/include/comedi.h)
   3     header file for comedi
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU Lesser General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 #ifndef _COMEDI_H
  20 #define _COMEDI_H
  21
  22 #define COMEDI_MAJORVERSION     0
  23 #define COMEDI_MINORVERSION     7
  24 #define COMEDI_MICROVERSION     76
  25 #define VERSION "0.7.76"
  26
  27 /* comedi's major device number */
  28 #define COMEDI_MAJOR 98
  29
  30 /*
  31    maximum number of minor devices.  This can be increased, although
  32    kernel structures are currently statically allocated, thus you
  33    don't want this to be much more than you actually use.
  34  */
  35 #define COMEDI_NDEVICES 16
  36
  37 /* number of config options in the config structure */
  38 #define COMEDI_NDEVCONFOPTS 32
  39
  40 /*
  41  * NOTE: 'comedi_config --init-data' is deprecated
  42  *
  43  * The following indexes in the config options were used by
  44  * comedi_config to pass firmware blobs from user space to the
  45  * comedi drivers. The request_firmware() hotplug interface is
  46  * now used by all comedi drivers instead.
  47  */
  48
  49 /* length of nth chunk of firmware data -*/
  50 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  51 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  52 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  53 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  54 /* most significant 32 bits of pointer address (if needed) */
  55 #define COMEDI_DEVCONF_AUX_DATA_HI              29
  56 /* least significant 32 bits of pointer address */
  57 #define COMEDI_DEVCONF_AUX_DATA_LO              30
  58 #define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  59
  60 /* max length of device and driver names */
  61 #define COMEDI_NAMELEN 20
  62
  63 /* packs and unpacks a channel/range number */
  64
  65 #define CR_PACK(chan, rng, aref)                                        \
  66         ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  67 #define CR_PACK_FLAGS(chan, range, aref, flags)                         \
  68         (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  69
  70 #define CR_CHAN(a)      ((a)&0xffff)
  71 #define CR_RANGE(a)     (((a)>>16)&0xff)
  72 #define CR_AREF(a)      (((a)>>24)&0x03)
  73
  74 #define CR_FLAGS_MASK   0xfc000000
  75 #define CR_ALT_FILTER   (1<<26)
  76 #define CR_DITHER       CR_ALT_FILTER
  77 #define CR_DEGLITCH     CR_ALT_FILTER
  78 #define CR_ALT_SOURCE   (1<<27)
  79 #define CR_EDGE         (1<<30)
  80 #define CR_INVERT       (1<<31)
  81
  82 #define AREF_GROUND     0x00    /* analog ref = analog ground */
  83 #define AREF_COMMON     0x01    /* analog ref = analog common */
  84 #define AREF_DIFF       0x02    /* analog ref = differential */
  85 #define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  86
  87 /* counters -- these are arbitrary values */
  88 #define GPCT_RESET              0x0001
  89 #define GPCT_SET_SOURCE         0x0002
  90 #define GPCT_SET_GATE           0x0004
  91 #define GPCT_SET_DIRECTION      0x0008
  92 #define GPCT_SET_OPERATION      0x0010
  93 #define GPCT_ARM                0x0020
  94 #define GPCT_DISARM             0x0040
  95 #define GPCT_GET_INT_CLK_FRQ    0x0080
  96
  97 #define GPCT_INT_CLOCK          0x0001
  98 #define GPCT_EXT_PIN            0x0002
  99 #define GPCT_NO_GATE            0x0004
 100 #define GPCT_UP                 0x0008
 101 #define GPCT_DOWN               0x0010
 102 #define GPCT_HWUD               0x0020
 103 #define GPCT_SIMPLE_EVENT       0x0040
 104 #define GPCT_SINGLE_PERIOD      0x0080
 105 #define GPCT_SINGLE_PW          0x0100
 106 #define GPCT_CONT_PULSE_OUT     0x0200
 107 #define GPCT_SINGLE_PULSE_OUT   0x0400
 108
 109 /* instructions */
 110
 111 #define INSN_MASK_WRITE         0x8000000
 112 #define INSN_MASK_READ          0x4000000
 113 #define INSN_MASK_SPECIAL       0x2000000
 114
 115 #define INSN_READ               (0 | INSN_MASK_READ)
 116 #define INSN_WRITE              (1 | INSN_MASK_WRITE)
 117 #define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 118 #define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 119 #define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 120 #define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 121 #define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 122
 123 /* trigger flags */
 124 /* These flags are used in comedi_trig structures */
 125
 126 #define TRIG_BOGUS      0x0001  /* do the motions */
 127 #define TRIG_DITHER     0x0002  /* enable dithering */
 128 #define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 129         /*#define TRIG_RT       0x0008 *//* perform op in real time */
 130 #define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 131 #define TRIG_WAKE_EOS   0x0020  /* wake up on end-of-scan events */
 132         /*#define TRIG_WRITE    0x0040*//* write to bidirectional devices */
 133
 134 /* command flags */
 135 /* These flags are used in comedi_cmd structures */
 136
 137 /* try to use a real-time interrupt while performing command */
 138 #define CMDF_PRIORITY           0x00000008
 139
 140 #define TRIG_RT         CMDF_PRIORITY   /* compatibility definition */
 141
 142 #define CMDF_WRITE              0x00000040
 143 #define TRIG_WRITE      CMDF_WRITE      /* compatibility definition */
 144
 145 #define CMDF_RAWDATA            0x00000080
 146
 147 #define COMEDI_EV_START         0x00040000
 148 #define COMEDI_EV_SCAN_BEGIN    0x00080000
 149 #define COMEDI_EV_CONVERT       0x00100000
 150 #define COMEDI_EV_SCAN_END      0x00200000
 151 #define COMEDI_EV_STOP          0x00400000
 152
 153 #define TRIG_ROUND_MASK         0x00030000
 154 #define TRIG_ROUND_NEAREST      0x00000000
 155 #define TRIG_ROUND_DOWN         0x00010000
 156 #define TRIG_ROUND_UP           0x00020000
 157 #define TRIG_ROUND_UP_NEXT      0x00030000
 158
 159 /* trigger sources */
 160
 161 #define TRIG_ANY        0xffffffff
 162 #define TRIG_INVALID    0x00000000
 163
 164 #define TRIG_NONE       0x00000001 /* never trigger */
 165 #define TRIG_NOW        0x00000002 /* trigger now + N ns */
 166 #define TRIG_FOLLOW     0x00000004 /* trigger on next lower level trig */
 167 #define TRIG_TIME       0x00000008 /* trigger at time N ns */
 168 #define TRIG_TIMER      0x00000010 /* trigger at rate N ns */
 169 #define TRIG_COUNT      0x00000020 /* trigger when count reaches N */
 170 #define TRIG_EXT        0x00000040 /* trigger on external signal N */
 171 #define TRIG_INT        0x00000080 /* trigger on comedi-internal signal N */
 172 #define TRIG_OTHER      0x00000100 /* driver defined */
 173
 174 /* subdevice flags */
 175
 176 #define SDF_BUSY        0x0001  /* device is busy */
 177 #define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 178 #define SDF_LOCKED      0x0004  /* subdevice is locked */
 179 #define SDF_LOCK_OWNER  0x0008  /* you own lock */
 180 #define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 181 #define SDF_FLAGS       0x0020  /* flags depend on channel */
 182 #define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 183 #define SDF_MODE0       0x0080  /* can do mode 0 */
 184 #define SDF_MODE1       0x0100  /* can do mode 1 */
 185 #define SDF_MODE2       0x0200  /* can do mode 2 */
 186 #define SDF_MODE3       0x0400  /* can do mode 3 */
 187 #define SDF_MODE4       0x0800  /* can do mode 4 */
 188 #define SDF_CMD         0x1000  /* can do commands (deprecated) */
 189 #define SDF_SOFT_CALIBRATED     0x2000 /* subdevice uses software calibration */
 190 #define SDF_CMD_WRITE           0x4000 /* can do output commands */
 191 #define SDF_CMD_READ            0x8000 /* can do input commands */
 192
 193 /* subdevice can be read (e.g. analog input) */
 194 #define SDF_READABLE    0x00010000
 195 /* subdevice can be written (e.g. analog output) */
 196 #define SDF_WRITABLE    0x00020000
 197 #define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 198 /* subdevice does not have externally visible lines */
 199 #define SDF_INTERNAL    0x00040000
 200 #define SDF_GROUND      0x00100000      /* can do aref=ground */
 201 #define SDF_COMMON      0x00200000      /* can do aref=common */
 202 #define SDF_DIFF        0x00400000      /* can do aref=diff */
 203 #define SDF_OTHER       0x00800000      /* can do aref=other */
 204 #define SDF_DITHER      0x01000000      /* can do dithering */
 205 #define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 206 #define SDF_MMAP        0x04000000      /* can do mmap() */
 207 #define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 208 #define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 209 #define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 210 /* re recyle these flags for PWM */
 211 #define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 212 #define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 213
 214 /* subdevice types */
 215
 216 enum comedi_subdevice_type {
 217         COMEDI_SUBD_UNUSED,     /* unused by driver */
 218         COMEDI_SUBD_AI,         /* analog input */
 219         COMEDI_SUBD_AO,         /* analog output */
 220         COMEDI_SUBD_DI,         /* digital input */
 221         COMEDI_SUBD_DO,         /* digital output */
 222         COMEDI_SUBD_DIO,        /* digital input/output */
 223         COMEDI_SUBD_COUNTER,    /* counter */
 224         COMEDI_SUBD_TIMER,      /* timer */
 225         COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 226         COMEDI_SUBD_CALIB,      /* calibration DACs */
 227         COMEDI_SUBD_PROC,       /* processor, DSP */
 228         COMEDI_SUBD_SERIAL,     /* serial IO */
 229         COMEDI_SUBD_PWM         /* PWM */
 230 };
 231
 232 /* configuration instructions */
 233
 234 enum configuration_ids {
 235         INSN_CONFIG_DIO_INPUT = 0,
 236         INSN_CONFIG_DIO_OUTPUT = 1,
 237         INSN_CONFIG_DIO_OPENDRAIN = 2,
 238         INSN_CONFIG_ANALOG_TRIG = 16,
 239 /*      INSN_CONFIG_WAVEFORM = 17, */
 240 /*      INSN_CONFIG_TRIG = 18, */
 241 /*      INSN_CONFIG_COUNTER = 19, */
 242         INSN_CONFIG_ALT_SOURCE = 20,
 243         INSN_CONFIG_DIGITAL_TRIG = 21,
 244         INSN_CONFIG_BLOCK_SIZE = 22,
 245         INSN_CONFIG_TIMER_1 = 23,
 246         INSN_CONFIG_FILTER = 24,
 247         INSN_CONFIG_CHANGE_NOTIFY = 25,
 248
 249         INSN_CONFIG_SERIAL_CLOCK = 26,  /*ALPHA*/
 250         INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 251         INSN_CONFIG_DIO_QUERY = 28,
 252         INSN_CONFIG_PWM_OUTPUT = 29,
 253         INSN_CONFIG_GET_PWM_OUTPUT = 30,
 254         INSN_CONFIG_ARM = 31,
 255         INSN_CONFIG_DISARM = 32,
 256         INSN_CONFIG_GET_COUNTER_STATUS = 33,
 257         INSN_CONFIG_RESET = 34,
 258         /* Use CTR as single pulsegenerator */
 259         INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001,
 260         /* Use CTR as pulsetraingenerator */
 261         INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,
 262         /* Use the counter as encoder */
 263         INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,
 264         INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 265         INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 266         /* Set master clock source */
 267         INSN_CONFIG_SET_CLOCK_SRC = 2003,
 268         INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */
 269         INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */
 270         /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
 271         /* Get size in bytes of subdevice's on-board fifos used during
 272          * streaming input/output */
 273         INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,
 274         INSN_CONFIG_SET_COUNTER_MODE = 4097,
 275         /* INSN_CONFIG_8254_SET_MODE is deprecated */
 276         INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,
 277         INSN_CONFIG_8254_READ_STATUS = 4098,
 278         INSN_CONFIG_SET_ROUTING = 4099,
 279         INSN_CONFIG_GET_ROUTING = 4109,
 280         /* PWM */
 281         INSN_CONFIG_PWM_SET_PERIOD = 5000,      /* sets frequency */
 282         INSN_CONFIG_PWM_GET_PERIOD = 5001,      /* gets frequency */
 283         INSN_CONFIG_GET_PWM_STATUS = 5002,      /* is it running? */
 284         /* sets H bridge: duty cycle and sign bit for a relay at the
 285          * same time */
 286         INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
 287         /* gets H bridge data: duty cycle and the sign bit */
 288         INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
 289 };
 290
 291 /*
 292  * Settings for INSN_CONFIG_DIGITAL_TRIG:
 293  * data[0] = INSN_CONFIG_DIGITAL_TRIG
 294  * data[1] = trigger ID
 295  * data[2] = configuration operation
 296  * data[3] = configuration parameter 1
 297  * data[4] = configuration parameter 2
 298  * data[5] = configuration parameter 3
 299  *
 300  * operation                           parameter 1   parameter 2   parameter 3
 301  * ---------------------------------   -----------   -----------   -----------
 302  * COMEDI_DIGITAL_TRIG_DISABLE
 303  * COMEDI_DIGITAL_TRIG_ENABLE_EDGES    left-shift    rising-edges  falling-edges
 304  * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS   left-shift    high-levels   low-levels
 305  *
 306  * COMEDI_DIGITAL_TRIG_DISABLE returns the trigger to its default, inactive,
 307  * unconfigured state.
 308  *
 309  * COMEDI_DIGITAL_TRIG_ENABLE_EDGES sets the rising and/or falling edge inputs
 310  * that each can fire the trigger.
 311  *
 312  * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS sets a combination of high and/or low
 313  * level inputs that can fire the trigger.
 314  *
 315  * "left-shift" is useful if the trigger has more than 32 inputs to specify the
 316  * first input for this configuration.
 317  *
 318  * Some sequences of INSN_CONFIG_DIGITAL_TRIG instructions may have a (partly)
 319  * accumulative effect, depending on the low-level driver.  This is useful
 320  * when setting up a trigger that has more than 32 inputs or has a combination
 321  * of edge and level triggered inputs.
 322  */
 323 enum comedi_digital_trig_op {
 324         COMEDI_DIGITAL_TRIG_DISABLE = 0,
 325         COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1,
 326         COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2
 327 };
 328
 329 enum comedi_io_direction {
 330         COMEDI_INPUT = 0,
 331         COMEDI_OUTPUT = 1,
 332         COMEDI_OPENDRAIN = 2
 333 };
 334
 335 enum comedi_support_level {
 336         COMEDI_UNKNOWN_SUPPORT = 0,
 337         COMEDI_SUPPORTED,
 338         COMEDI_UNSUPPORTED
 339 };
 340
 341 /* ioctls */
 342
 343 #define CIO 'd'
 344 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
 345 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
 346 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
 347 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
 348 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 349 #define COMEDI_LOCK _IO(CIO, 5)
 350 #define COMEDI_UNLOCK _IO(CIO, 6)
 351 #define COMEDI_CANCEL _IO(CIO, 7)
 352 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
 353 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
 354 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
 355 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
 356 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
 357 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
 358 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
 359 #define COMEDI_POLL _IO(CIO, 15)
 360
 361 /* structures */
 362
 363 struct comedi_trig {
 364         unsigned int subdev;    /* subdevice */
 365         unsigned int mode;      /* mode */
 366         unsigned int flags;
 367         unsigned int n_chan;    /* number of channels */
 368         unsigned int *chanlist; /* channel/range list */
 369         short *data;            /* data list, size depends on subd flags */
 370         unsigned int n;         /* number of scans */
 371         unsigned int trigsrc;
 372         unsigned int trigvar;
 373         unsigned int trigvar1;
 374         unsigned int data_len;
 375         unsigned int unused[3];
 376 };
 377
 378 struct comedi_insn {
 379         unsigned int insn;
 380         unsigned int n;
 381         unsigned int __user *data;
 382         unsigned int subdev;
 383         unsigned int chanspec;
 384         unsigned int unused[3];
 385 };
 386
 387 struct comedi_insnlist {
 388         unsigned int n_insns;
 389         struct comedi_insn __user *insns;
 390 };
 391
 392 struct comedi_cmd {
 393         unsigned int subdev;
 394         unsigned int flags;
 395
 396         unsigned int start_src;
 397         unsigned int start_arg;
 398
 399         unsigned int scan_begin_src;
 400         unsigned int scan_begin_arg;
 401
 402         unsigned int convert_src;
 403         unsigned int convert_arg;
 404
 405         unsigned int scan_end_src;
 406         unsigned int scan_end_arg;
 407
 408         unsigned int stop_src;
 409         unsigned int stop_arg;
 410
 411         unsigned int *chanlist; /* channel/range list */
 412         unsigned int chanlist_len;
 413
 414         short __user *data; /* data list, size depends on subd flags */
 415         unsigned int data_len;
 416 };
 417
 418 struct comedi_chaninfo {
 419         unsigned int subdev;
 420         unsigned int __user *maxdata_list;
 421         unsigned int __user *flaglist;
 422         unsigned int __user *rangelist;
 423         unsigned int unused[4];
 424 };
 425
 426 struct comedi_rangeinfo {
 427         unsigned int range_type;
 428         void __user *range_ptr;
 429 };
 430
 431 struct comedi_krange {
 432         int min;        /* fixed point, multiply by 1e-6 */
 433         int max;        /* fixed point, multiply by 1e-6 */
 434         unsigned int flags;
 435 };
 436
 437 struct comedi_subdinfo {
 438         unsigned int type;
 439         unsigned int n_chan;
 440         unsigned int subd_flags;
 441         unsigned int timer_type;
 442         unsigned int len_chanlist;
 443         unsigned int maxdata;
 444         unsigned int flags;             /* channel flags */
 445         unsigned int range_type;        /* lookup in kernel */
 446         unsigned int settling_time_0;
 447         /* see support_level enum for values */
 448         unsigned insn_bits_support;
 449         unsigned int unused[8];
 450 };
 451
 452 struct comedi_devinfo {
 453         unsigned int version_code;
 454         unsigned int n_subdevs;
 455         char driver_name[COMEDI_NAMELEN];
 456         char board_name[COMEDI_NAMELEN];
 457         int read_subdevice;
 458         int write_subdevice;
 459         int unused[30];
 460 };
 461
 462 struct comedi_devconfig {
 463         char board_name[COMEDI_NAMELEN];
 464         int options[COMEDI_NDEVCONFOPTS];
 465 };
 466
 467 struct comedi_bufconfig {
 468         unsigned int subdevice;
 469         unsigned int flags;
 470
 471         unsigned int maximum_size;
 472         unsigned int size;
 473
 474         unsigned int unused[4];
 475 };
 476
 477 struct comedi_bufinfo {
 478         unsigned int subdevice;
 479         unsigned int bytes_read;
 480
 481         unsigned int buf_write_ptr;
 482         unsigned int buf_read_ptr;
 483         unsigned int buf_write_count;
 484         unsigned int buf_read_count;
 485
 486         unsigned int bytes_written;
 487
 488         unsigned int unused[4];
 489 };
 490
 491 /* range stuff */
 492
 493 #define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 494
 495 #define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 496 #define RANGE_LENGTH(b)         ((b)&0xffff)
 497
 498 #define RF_UNIT(flags)          ((flags)&0xff)
 499 #define RF_EXTERNAL             (1<<8)
 500
 501 #define UNIT_volt               0
 502 #define UNIT_mA                 1
 503 #define UNIT_none               2
 504
 505 #define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 506
 507 /* callback stuff */
 508 /* only relevant to kernel modules. */
 509
 510 #define COMEDI_CB_EOS           1       /* end of scan */
 511 #define COMEDI_CB_EOA           2       /* end of acquisition/output */
 512 #define COMEDI_CB_BLOCK         4       /* data has arrived:
 513                                          * wakes up read() / write() */
 514 #define COMEDI_CB_EOBUF         8       /* DEPRECATED: end of buffer */
 515 #define COMEDI_CB_ERROR         16      /* card error during acquisition */
 516 #define COMEDI_CB_OVERFLOW      32      /* buffer overflow/underflow */
 517
 518 /**********************************************************/
 519 /* everything after this line is ALPHA */
 520 /**********************************************************/
 521
 522 /*
 523   8254 specific configuration.
 524
 525   It supports two config commands:
 526
 527   0 ID: INSN_CONFIG_SET_COUNTER_MODE
 528   1 8254 Mode
 529     I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 530     OR'ed with:
 531     I8254_BCD, I8254_BINARY
 532
 533   0 ID: INSN_CONFIG_8254_READ_STATUS
 534   1 <-- Status byte returned here.
 535     B7 = Output
 536     B6 = NULL Count
 537     B5 - B0 Current mode.
 538
 539 */
 540
 541 enum i8254_mode {
 542         I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 543         I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 544         I8254_MODE2 = (2 << 1), /* Rate generator */
 545         I8254_MODE3 = (3 << 1), /* Square wave mode */
 546         I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 547         I8254_MODE5 = (5 << 1), /* Hardware triggered strobe
 548                                  * (retriggerable) */
 549         I8254_BCD = 1,          /* use binary-coded decimal instead of binary
 550                                  * (pretty useless) */
 551         I8254_BINARY = 0
 552 };
 553
 554 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
 555 {
 556         if (pfi_channel < 10)
 557                 return 0x1 + pfi_channel;
 558         else
 559                 return 0xb + pfi_channel;
 560 }
 561
 562 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
 563 {
 564         if (rtsi_channel < 7)
 565                 return 0xb + rtsi_channel;
 566         else
 567                 return 0x1b;
 568 }
 569
 570 /* mode bits for NI general-purpose counters, set with
 571  * INSN_CONFIG_SET_COUNTER_MODE */
 572 #define NI_GPCT_COUNTING_MODE_SHIFT 16
 573 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 574 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 575 enum ni_gpct_mode_bits {
 576         NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 577         NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 578         NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 579         NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 580         NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 581         NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 582         NI_GPCT_STOP_MODE_MASK = 0x60,
 583         NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 584         NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 585         NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 586         NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 587         NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 588         NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 589         NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 590         NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 591         NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 592         NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 593         NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 594         NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 595         NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 596         NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 597         NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 598         NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 599         NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 600                 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 601         NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 602                 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 603         NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 604                 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 605         NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 606                 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 607         NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 608                 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 609         NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 610                 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 611         NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 612         NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 613                 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 614         NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 615                 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 616         NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 617                 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 618         NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 619                 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 620         NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 621         NI_GPCT_COUNTING_DIRECTION_MASK =
 622                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 623         NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 624                 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 625         NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 626                 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 627         NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 628                 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 629         NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 630                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 631         NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 632         NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 633         NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 634         NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 635         NI_GPCT_OR_GATE_BIT = 0x10000000,
 636         NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 637 };
 638
 639 /* Bits for setting a clock source with
 640  * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 641 enum ni_gpct_clock_source_bits {
 642         NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 643         NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 644         NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 645         NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 646         NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 647         NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 648         NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 649         /* NI 660x-specific */
 650         NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,
 651         NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 652         NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 653         NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 654         NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 655         NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 656         /* divide source by 2 */
 657         NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,
 658         /* divide source by 8 */
 659         NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
 660         NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 661 };
 662 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
 663 {
 664         /* NI 660x-specific */
 665         return 0x10 + n;
 666 }
 667 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
 668 {
 669         return 0x18 + n;
 670 }
 671 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
 672 {
 673         /* no pfi on NI 660x */
 674         return 0x20 + n;
 675 }
 676
 677 /* Possibilities for setting a gate source with
 678 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 679 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 680 enum ni_gpct_gate_select {
 681         /* m-series gates */
 682         NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 683         NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 684         NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 685         NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 686         NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 687         NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 688         NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 689         NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 690         /* more gates for 660x */
 691         NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 692         NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 693         /* more gates for 660x "second gate" */
 694         NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 695         NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 696         /* m-series "second gate" sources are unknown,
 697          * we should add them here with an offset of 0x300 when
 698          * known. */
 699         NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 700 };
 701 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
 702 {
 703         return 0x102 + n;
 704 }
 705 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
 706 {
 707         return NI_USUAL_RTSI_SELECT(n);
 708 }
 709 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
 710 {
 711         return NI_USUAL_PFI_SELECT(n);
 712 }
 713 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
 714 {
 715         return 0x202 + n;
 716 }
 717
 718 /* Possibilities for setting a source with
 719 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 720 enum ni_gpct_other_index {
 721         NI_GPCT_SOURCE_ENCODER_A,
 722         NI_GPCT_SOURCE_ENCODER_B,
 723         NI_GPCT_SOURCE_ENCODER_Z
 724 };
 725 enum ni_gpct_other_select {
 726         /* m-series gates */
 727         /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 728         NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 729 };
 730 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
 731 {
 732         return NI_USUAL_PFI_SELECT(n);
 733 }
 734
 735 /* start sources for ni general-purpose counters for use with
 736 INSN_CONFIG_ARM */
 737 enum ni_gpct_arm_source {
 738         NI_GPCT_ARM_IMMEDIATE = 0x0,
 739         NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
 740                                              * and the adjacent paired
 741                                              * counter simultaneously */
 742         /* NI doesn't document bits for selecting hardware arm triggers.
 743          * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 744          * significant bits (3 bits for 660x or 5 bits for m-series)
 745          * through to the hardware.  This will at least allow someone to
 746          * figure out what the bits do later. */
 747         NI_GPCT_ARM_UNKNOWN = 0x1000,
 748 };
 749
 750 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 751 enum ni_gpct_filter_select {
 752         NI_GPCT_FILTER_OFF = 0x0,
 753         NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 754         NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 755         NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 756         NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 757         NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 758         NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 759 };
 760
 761 /* PFI digital filtering options for ni m-series for use with
 762  * INSN_CONFIG_FILTER. */
 763 enum ni_pfi_filter_select {
 764         NI_PFI_FILTER_OFF = 0x0,
 765         NI_PFI_FILTER_125ns = 0x1,
 766         NI_PFI_FILTER_6425ns = 0x2,
 767         NI_PFI_FILTER_2550us = 0x3
 768 };
 769
 770 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 771 enum ni_mio_clock_source {
 772         NI_MIO_INTERNAL_CLOCK = 0,
 773         NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 774                                    NI_MIO_PLL_RTSI_CLOCK() */
 775         /* the NI_MIO_PLL_* sources are m-series only */
 776         NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 777         NI_MIO_PLL_PXI10_CLOCK = 3,
 778         NI_MIO_PLL_RTSI0_CLOCK = 4
 779 };
 780 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
 781 {
 782         return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
 783 }
 784
 785 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 786  The numbers assigned are not arbitrary, they correspond to the bits required
 787  to program the board. */
 788 enum ni_rtsi_routing {
 789         NI_RTSI_OUTPUT_ADR_START1 = 0,
 790         NI_RTSI_OUTPUT_ADR_START2 = 1,
 791         NI_RTSI_OUTPUT_SCLKG = 2,
 792         NI_RTSI_OUTPUT_DACUPDN = 3,
 793         NI_RTSI_OUTPUT_DA_START1 = 4,
 794         NI_RTSI_OUTPUT_G_SRC0 = 5,
 795         NI_RTSI_OUTPUT_G_GATE0 = 6,
 796         NI_RTSI_OUTPUT_RGOUT0 = 7,
 797         NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 798         NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI
 799                                          * clock on line 7 */
 800 };
 801 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
 802 {
 803         return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
 804 }
 805
 806 /* Signals which can be routed to an NI PFI pin on an m-series board with
 807  * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 808  * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 809  * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 810  * to the bits required to program the board. */
 811 enum ni_pfi_routing {
 812         NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 813         NI_PFI_OUTPUT_AI_START1 = 1,
 814         NI_PFI_OUTPUT_AI_START2 = 2,
 815         NI_PFI_OUTPUT_AI_CONVERT = 3,
 816         NI_PFI_OUTPUT_G_SRC1 = 4,
 817         NI_PFI_OUTPUT_G_GATE1 = 5,
 818         NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 819         NI_PFI_OUTPUT_AO_START1 = 7,
 820         NI_PFI_OUTPUT_AI_START_PULSE = 8,
 821         NI_PFI_OUTPUT_G_SRC0 = 9,
 822         NI_PFI_OUTPUT_G_GATE0 = 10,
 823         NI_PFI_OUTPUT_EXT_STROBE = 11,
 824         NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 825         NI_PFI_OUTPUT_GOUT0 = 13,
 826         NI_PFI_OUTPUT_GOUT1 = 14,
 827         NI_PFI_OUTPUT_FREQ_OUT = 15,
 828         NI_PFI_OUTPUT_PFI_DO = 16,
 829         NI_PFI_OUTPUT_I_ATRIG = 17,
 830         NI_PFI_OUTPUT_RTSI0 = 18,
 831         NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 832         NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 833         NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 834         NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 835         NI_PFI_OUTPUT_CDO_UPDATE = 30
 836 };
 837 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
 838 {
 839         return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
 840 }
 841
 842 /* Signals which can be routed to output on a NI PFI pin on a 660x board
 843  with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 844  not arbitrary, they correspond to the bits required
 845  to program the board.  Lines 0 to 7 can only be set to
 846  NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 847  NI_660X_PFI_OUTPUT_COUNTER. */
 848 enum ni_660x_pfi_routing {
 849         NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 850         NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 851 };
 852
 853 /* NI External Trigger lines.  These values are not arbitrary, but are related
 854  * to the bits required to program the board (offset by 1 for historical
 855  * reasons). */
 856 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
 857 {
 858         return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
 859 }
 860 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
 861 {
 862         return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
 863 }
 864
 865 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 866 enum comedi_counter_status_flags {
 867         COMEDI_COUNTER_ARMED = 0x1,
 868         COMEDI_COUNTER_COUNTING = 0x2,
 869         COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 870 };
 871
 872 /* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 873  * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 874  * with CR_INVERT to change polarity. */
 875 enum ni_m_series_cdio_scan_begin_src {
 876         NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 877         NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 878         NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 879         NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 880         NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 881         NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 882         NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 883         NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 884         NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 885         NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 886 };
 887 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 888 {
 889         return NI_USUAL_PFI_SELECT(pfi_channel);
 890 }
 891 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 892 {
 893         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 894 }
 895
 896 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 897  * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 898  * change polarity. */
 899 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 900 {
 901         return NI_USUAL_PFI_SELECT(pfi_channel);
 902 }
 903 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 904 {
 905         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 906 }
 907
 908 /* Bits for setting a clock source with
 909  * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 910 enum ni_freq_out_clock_source_bits {
 911         NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 912         NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 913 };
 914
 915 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 916  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 917 enum amplc_dio_clock_source {
 918         AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 919                                    input/output pin (pin is only an
 920                                    input when clock source set to this
 921                                    value, otherwise it is an output) */
 922         AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 923         AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 924         AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 925         AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 926         AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 927         AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 928                                    (for channel 0, preceding counter
 929                                    channel is channel 2 on preceding
 930                                    counter subdevice, for first counter
 931                                    subdevice, preceding counter
 932                                    subdevice is the last counter
 933                                    subdevice) */
 934         AMPLC_DIO_CLK_EXT,      /* per chip external input pin */
 935         /* the following are "enhanced" clock sources for PCIe models */
 936         AMPLC_DIO_CLK_VCC,      /* clock input HIGH */
 937         AMPLC_DIO_CLK_GND,      /* clock input LOW */
 938         AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */
 939         AMPLC_DIO_CLK_20MHZ     /* 20 MHz internal clock */
 940 };
 941
 942 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 943  * timer subdevice on some Amplicon DIO PCIe boards (amplc_dio200 driver). */
 944 enum amplc_dio_ts_clock_src {
 945         AMPLC_DIO_TS_CLK_1GHZ,  /* 1 ns period with 20 ns granularity */
 946         AMPLC_DIO_TS_CLK_1MHZ,  /* 1 us period */
 947         AMPLC_DIO_TS_CLK_1KHZ   /* 1 ms period */
 948 };
 949
 950 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 951  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 952 enum amplc_dio_gate_source {
 953         AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 954         AMPLC_DIO_GAT_GND,      /* internal low logic level */
 955         AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 956         AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 957                                    minus 2 (for channels 0 or 1,
 958                                    channel minus 2 is channel 1 or 2 on
 959                                    the preceding counter subdevice, for
 960                                    the first counter subdevice the
 961                                    preceding counter subdevice is the
 962                                    last counter subdevice) */
 963         AMPLC_DIO_GAT_RESERVED4,
 964         AMPLC_DIO_GAT_RESERVED5,
 965         AMPLC_DIO_GAT_RESERVED6,
 966         AMPLC_DIO_GAT_RESERVED7,
 967         /* the following are "enhanced" gate sources for PCIe models */
 968         AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */
 969         AMPLC_DIO_GAT_OUTNM2,   /* non-negated output of counter
 970                                    channel minus 2 */
 971         AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */
 972         AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */
 973         AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */
 974         AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */
 975         AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */
 976         AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */
 977 };
 978
 979 #endif /* _COMEDI_H */