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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / staging / rtl8192u / r8192U.h
blobb484ee128c13fd1227f686a2bee544c8a54f192a
1 /*
2 * This is part of rtl8187 OpenSource driver.
3 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com>
4 * Released under the terms of GPL (General Public Licence)
5 *
6 * Parts of this driver are based on the GPL part of the
7 * official realtek driver
8 *
9 * Parts of this driver are based on the rtl8192 driver skeleton
10 * from Patric Schenke & Andres Salomon
11 *
12 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13 *
14 * We want to thank the Authors of those projects and the Ndiswrapper
15 * project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/slab.h>
28 #include <linux/netdevice.h>
29 #include <linux/usb.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/wireless.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h>
36 #include <linux/if_arp.h>
37 #include <linux/random.h>
38 #include <asm/io.h>
39 #include "ieee80211/ieee80211.h"
40
41 #define RTL8192U
42 #define RTL819xU_MODULE_NAME "rtl819xU"
43 /* HW security */
44 #define FALSE 0
45 #define TRUE 1
46 #define MAX_KEY_LEN 61
47 #define KEY_BUF_SIZE 5
48
49 #define BIT0 0x00000001
50 #define BIT1 0x00000002
51 #define BIT2 0x00000004
52 #define BIT3 0x00000008
53 #define BIT4 0x00000010
54 #define BIT5 0x00000020
55 #define BIT6 0x00000040
56 #define BIT7 0x00000080
57 #define BIT8 0x00000100
58 #define BIT9 0x00000200
59 #define BIT10 0x00000400
60 #define BIT11 0x00000800
61 #define BIT12 0x00001000
62 #define BIT13 0x00002000
63 #define BIT14 0x00004000
64 #define BIT15 0x00008000
65 #define BIT16 0x00010000
66 #define BIT17 0x00020000
67 #define BIT18 0x00040000
68 #define BIT19 0x00080000
69 #define BIT20 0x00100000
70 #define BIT21 0x00200000
71 #define BIT22 0x00400000
72 #define BIT23 0x00800000
73 #define BIT24 0x01000000
74 #define BIT25 0x02000000
75 #define BIT26 0x04000000
76 #define BIT27 0x08000000
77 #define BIT28 0x10000000
78 #define BIT29 0x20000000
79 #define BIT30 0x40000000
80 #define BIT31 0x80000000
81
82 #define Rx_Smooth_Factor 20
83 #define DMESG(x, a...)
84 #define DMESGW(x, a...)
85 #define DMESGE(x, a...)
86 extern u32 rt_global_debug_component;
87 #define RT_TRACE(component, x, args...) \
88 do { \
89 if (rt_global_debug_component & component) \
90 pr_debug("RTL8192U: " x "\n", ##args); \
91 } while (0)
92
93 #define COMP_TRACE BIT0 /* Function call tracing. */
94 #define COMP_DBG BIT1
95 #define COMP_INIT BIT2 /* Driver initialization/halt/reset. */
96
97
98 #define COMP_RECV BIT3 /* Receive data path. */
99 #define COMP_SEND BIT4 /* Send data path. */
100 #define COMP_IO BIT5
101 /* 802.11 Power Save mode or System/Device Power state. */
102 #define COMP_POWER BIT6
103 /* 802.11 link related: join/start BSS, leave BSS. */
104 #define COMP_EPROM BIT7
105 #define COMP_SWBW BIT8 /* Bandwidth switch. */
106 #define COMP_POWER_TRACKING BIT9 /* 8190 TX Power Tracking */
107 #define COMP_TURBO BIT10 /* Turbo Mode */
108 #define COMP_QOS BIT11
109 #define COMP_RATE BIT12 /* Rate Adaptive mechanism */
110 #define COMP_RM BIT13 /* Radio Measurement */
111 #define COMP_DIG BIT14
112 #define COMP_PHY BIT15
113 #define COMP_CH BIT16 /* Channel setting debug */
114 #define COMP_TXAGC BIT17 /* Tx power */
115 #define COMP_HIPWR BIT18 /* High Power Mechanism */
116 #define COMP_HALDM BIT19 /* HW Dynamic Mechanism */
117 #define COMP_SEC BIT20 /* Event handling */
118 #define COMP_LED BIT21
119 #define COMP_RF BIT22
120 #define COMP_RXDESC BIT23 /* Rx desc information for SD3 debug */
121
122 /* 11n or 8190 specific code */
123
124 #define COMP_FIRMWARE BIT24 /* Firmware downloading */
125 #define COMP_HT BIT25 /* 802.11n HT related information */
126 #define COMP_AMSDU BIT26 /* A-MSDU Debugging */
127 #define COMP_SCAN BIT27
128 #define COMP_DOWN BIT29 /* rm driver module */
129 #define COMP_RESET BIT30 /* Silent reset */
130 #define COMP_ERR BIT31 /* Error out, always on */
131
132 #define RTL819x_DEBUG
133 #ifdef RTL819x_DEBUG
134 #define RTL8192U_ASSERT(expr) \
135 do { \
136 if (!(expr)) { \
137 pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
139 } \
140 } while (0)
141 /*
142 * Debug out data buf.
143 * If you want to print DATA buffer related BA,
144 * please set ieee80211_debug_level to DATA|BA
145 */
146 #define RT_DEBUG_DATA(level, data, datalen) \
147 do { \
148 if ((rt_global_debug_component & (level)) == (level)) { \
149 int i; \
150 u8 *pdata = (u8 *) data; \
151 pr_debug("RTL8192U: %s()\n", __func__); \
152 for (i = 0; i < (int)(datalen); i++) { \
153 printk("%2x ", pdata[i]); \
154 if ((i+1)%16 == 0) \
155 printk("\n"); \
156 } \
157 printk("\n"); \
158 } \
159 } while (0)
160 #else
161 #define RTL8192U_ASSERT(expr) do {} while (0)
162 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
163 #endif /* RTL8169_DEBUG */
164
165
166 /* Queue Select Value in TxDesc */
167 #define QSLT_BK 0x1
168 #define QSLT_BE 0x0
169 #define QSLT_VI 0x4
170 #define QSLT_VO 0x6
171 #define QSLT_BEACON 0x10
172 #define QSLT_HIGH 0x11
173 #define QSLT_MGNT 0x12
174 #define QSLT_CMD 0x13
175
176 #define DESC90_RATE1M 0x00
177 #define DESC90_RATE2M 0x01
178 #define DESC90_RATE5_5M 0x02
179 #define DESC90_RATE11M 0x03
180 #define DESC90_RATE6M 0x04
181 #define DESC90_RATE9M 0x05
182 #define DESC90_RATE12M 0x06
183 #define DESC90_RATE18M 0x07
184 #define DESC90_RATE24M 0x08
185 #define DESC90_RATE36M 0x09
186 #define DESC90_RATE48M 0x0a
187 #define DESC90_RATE54M 0x0b
188 #define DESC90_RATEMCS0 0x00
189 #define DESC90_RATEMCS1 0x01
190 #define DESC90_RATEMCS2 0x02
191 #define DESC90_RATEMCS3 0x03
192 #define DESC90_RATEMCS4 0x04
193 #define DESC90_RATEMCS5 0x05
194 #define DESC90_RATEMCS6 0x06
195 #define DESC90_RATEMCS7 0x07
196 #define DESC90_RATEMCS8 0x08
197 #define DESC90_RATEMCS9 0x09
198 #define DESC90_RATEMCS10 0x0a
199 #define DESC90_RATEMCS11 0x0b
200 #define DESC90_RATEMCS12 0x0c
201 #define DESC90_RATEMCS13 0x0d
202 #define DESC90_RATEMCS14 0x0e
203 #define DESC90_RATEMCS15 0x0f
204 #define DESC90_RATEMCS32 0x20
205
206 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
207
208 #define IEEE80211_WATCH_DOG_TIME 2000
209 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
210 /* For Tx Power Tracking */
211 #define OFDM_Table_Length 19
212 #define CCK_Table_length 12
213
214 /* For rtl819x */
215 typedef struct _tx_desc_819x_usb {
216 /* DWORD 0 */
217 u16 PktSize;
218 u8 Offset;
219 u8 Reserved0:3;
220 u8 CmdInit:1;
221 u8 LastSeg:1;
222 u8 FirstSeg:1;
223 u8 LINIP:1;
224 u8 OWN:1;
225
226 /* DWORD 1 */
227 u8 TxFWInfoSize;
228 u8 RATid:3;
229 u8 DISFB:1;
230 u8 USERATE:1;
231 u8 MOREFRAG:1;
232 u8 NoEnc:1;
233 u8 PIFS:1;
234 u8 QueueSelect:5;
235 u8 NoACM:1;
236 u8 Reserved1:2;
237 u8 SecCAMID:5;
238 u8 SecDescAssign:1;
239 u8 SecType:2;
240
241 /* DWORD 2 */
242 u16 TxBufferSize;
243 u8 ResvForPaddingLen:7;
244 u8 Reserved3:1;
245 u8 Reserved4;
246
247 /* DWORD 3, 4, 5 */
248 u32 Reserved5;
249 u32 Reserved6;
250 u32 Reserved7;
251 } tx_desc_819x_usb, *ptx_desc_819x_usb;
252
253 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
254 typedef struct _tx_desc_819x_usb_aggr_subframe {
255 /* DWORD 0 */
256 u16 PktSize;
257 u8 Offset;
258 u8 TxFWInfoSize;
259
260 /* DWORD 1 */
261 u8 RATid:3;
262 u8 DISFB:1;
263 u8 USERATE:1;
264 u8 MOREFRAG:1;
265 u8 NoEnc:1;
266 u8 PIFS:1;
267 u8 QueueSelect:5;
268 u8 NoACM:1;
269 u8 Reserved1:2;
270 u8 SecCAMID:5;
271 u8 SecDescAssign:1;
272 u8 SecType:2;
273 u8 PacketID:7;
274 u8 OWN:1;
275 } tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
276 #endif
277
278
279
280 typedef struct _tx_desc_cmd_819x_usb {
281 /* DWORD 0 */
282 u16 Reserved0;
283 u8 Reserved1;
284 u8 Reserved2:3;
285 u8 CmdInit:1;
286 u8 LastSeg:1;
287 u8 FirstSeg:1;
288 u8 LINIP:1;
289 u8 OWN:1;
290
291 /* DOWRD 1 */
292 u8 TxFWInfoSize;
293 u8 Reserved3;
294 u8 QueueSelect;
295 u8 Reserved4;
296
297 /* DOWRD 2 */
298 u16 TxBufferSize;
299 u16 Reserved5;
300
301 /* DWORD 3, 4, 5 */
302 u32 Reserved6;
303 u32 Reserved7;
304 u32 Reserved8;
305 } tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
306
307
308 typedef struct _tx_fwinfo_819x_usb {
309 /* DOWRD 0 */
310 u8 TxRate:7;
311 u8 CtsEnable:1;
312 u8 RtsRate:7;
313 u8 RtsEnable:1;
314 u8 TxHT:1;
315 u8 Short:1; /* Error out, always on */
316 u8 TxBandwidth:1; /* Used for HT MCS rate only */
317 u8 TxSubCarrier:2; /* Used for legacy OFDM rate only */
318 u8 STBC:2;
319 u8 AllowAggregation:1;
320 /* Interpret RtsRate field as high throughput data rate */
321 u8 RtsHT:1;
322 u8 RtsShort:1; /* Short PLCP for CCK or short GI for 11n MCS */
323 u8 RtsBandwidth:1; /* Used for HT MCS rate only */
324 u8 RtsSubcarrier:2;/* Used for legacy OFDM rate only */
325 u8 RtsSTBC:2;
326 /* Enable firmware to recalculate and assign packet duration */
327 u8 EnableCPUDur:1;
328
329 /* DWORD 1 */
330 u32 RxMF:2;
331 u32 RxAMD:3;
332 /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
333 u32 TxPerPktInfoFeedback:1;
334 u32 Reserved1:2;
335 u32 TxAGCOffSet:4;
336 u32 TxAGCSign:1;
337 u32 Tx_INFO_RSVD:6;
338 u32 PacketID:13;
339 } tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
340
341 typedef struct rtl8192_rx_info {
342 struct urb *urb;
343 struct net_device *dev;
344 u8 out_pipe;
345 } rtl8192_rx_info ;
346
347 typedef struct rx_desc_819x_usb {
348 /* DOWRD 0 */
349 u16 Length:14;
350 u16 CRC32:1;
351 u16 ICV:1;
352 u8 RxDrvInfoSize;
353 u8 Shift:2;
354 u8 PHYStatus:1;
355 u8 SWDec:1;
356 u8 Reserved1:4;
357
358 /* DWORD 1 */
359 u32 Reserved2;
360 } rx_desc_819x_usb, *prx_desc_819x_usb;
361
362 #ifdef USB_RX_AGGREGATION_SUPPORT
363 typedef struct _rx_desc_819x_usb_aggr_subframe {
364 /* DOWRD 0 */
365 u16 Length:14;
366 u16 CRC32:1;
367 u16 ICV:1;
368 u8 Offset;
369 u8 RxDrvInfoSize;
370 /* DOWRD 1 */
371 u8 Shift:2;
372 u8 PHYStatus:1;
373 u8 SWDec:1;
374 u8 Reserved1:4;
375 u8 Reserved2;
376 u16 Reserved3;
377 } rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
378 #endif
379
380 typedef struct rx_drvinfo_819x_usb {
381 /* DWORD 0 */
382 u16 Reserved1:12;
383 u16 PartAggr:1;
384 u16 FirstAGGR:1;
385 u16 Reserved2:2;
386
387 u8 RxRate:7;
388 u8 RxHT:1;
389
390 u8 BW:1;
391 u8 SPLCP:1;
392 u8 Reserved3:2;
393 u8 PAM:1;
394 u8 Mcast:1;
395 u8 Bcast:1;
396 u8 Reserved4:1;
397
398 /* DWORD 1 */
399 u32 TSFL;
400
401 } rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
402
403 /* Support till 64 bit bus width OS */
404 #define MAX_DEV_ADDR_SIZE 8
405 /* For RTL8190 */
406 #define MAX_FIRMWARE_INFORMATION_SIZE 32
407 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
408 #define ENCRYPTION_MAX_OVERHEAD 128
409 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
410 #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
411 #define MAX_FRAGMENT_COUNT 8
412 #ifdef RTL8192U
413 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
414 #define MAX_TRANSMIT_BUFFER_SIZE 32000
415 #else
416 #define MAX_TRANSMIT_BUFFER_SIZE 8000
417 #endif
418 #else
419 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
420 #endif
421 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
422 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
423 #endif
424 /* Octets for crc32 (FCS, ICV) */
425 #define scrclng 4
426
427 typedef enum rf_optype {
428 RF_OP_By_SW_3wire = 0,
429 RF_OP_By_FW,
430 RF_OP_MAX
431 } rf_op_type;
432 /* 8190 Loopback Mode definition */
433 typedef enum _rtl819xUsb_loopback {
434 RTL819xU_NO_LOOPBACK = 0,
435 RTL819xU_MAC_LOOPBACK = 1,
436 RTL819xU_DMA_LOOPBACK = 2,
437 RTL819xU_CCK_LOOPBACK = 3,
438 } rtl819xUsb_loopback_e;
439
440 /* due to rtl8192 firmware */
441 typedef enum _desc_packet_type_e {
442 DESC_PACKET_TYPE_INIT = 0,
443 DESC_PACKET_TYPE_NORMAL = 1,
444 } desc_packet_type_e;
445
446 typedef enum _firmware_status {
447 FW_STATUS_0_INIT = 0,
448 FW_STATUS_1_MOVE_BOOT_CODE = 1,
449 FW_STATUS_2_MOVE_MAIN_CODE = 2,
450 FW_STATUS_3_TURNON_CPU = 3,
451 FW_STATUS_4_MOVE_DATA_CODE = 4,
452 FW_STATUS_5_READY = 5,
453 } firmware_status_e;
454
455 typedef struct _rt_firmare_seg_container {
456 u16 seg_size;
457 u8 *seg_ptr;
458 } fw_seg_container, *pfw_seg_container;
459 typedef struct _rt_firmware {
460 firmware_status_e firmware_status;
461 u16 cmdpacket_frag_thresold;
462 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
463 u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
464 u16 firmware_buf_size;
465 } rt_firmware, *prt_firmware;
466
467 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
468 #define MAX_RECEIVE_BUFFER_SIZE 9100
469
470 typedef struct _rt_firmware_info_819xUsb {
471 u8 sz_info[16];
472 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
473
474 /* Firmware Queue Layout */
475 #define NUM_OF_FIRMWARE_QUEUE 10
476 #define NUM_OF_PAGES_IN_FW 0x100
477
478 #ifdef USE_ONE_PIPE
479 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000
480 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000
481 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff
482 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000
483 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
484 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
485 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00
486 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
487 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0
488 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00
489 #else
490
491 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
492 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
493 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
494 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
495 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
496 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
497 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
498 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
499 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
500 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
501
502 #endif
503
504 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
505 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
506 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
507 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
508 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
509 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
510 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
511 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
512 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
513
514 /*
515 * =================================================================
516 * =================================================================
517 */
518
519 #define EPROM_93c46 0
520 #define EPROM_93c56 1
521
522 #define DEFAULT_FRAG_THRESHOLD 2342U
523 #define MIN_FRAG_THRESHOLD 256U
524 #define DEFAULT_BEACONINTERVAL 0x64U
525 #define DEFAULT_BEACON_ESSID "Rtl819xU"
526
527 #define DEFAULT_SSID ""
528 #define DEFAULT_RETRY_RTS 7
529 #define DEFAULT_RETRY_DATA 7
530 #define PRISM_HDR_SIZE 64
531
532 #define PHY_RSSI_SLID_WIN_MAX 100
533
534
535 typedef enum _WIRELESS_MODE {
536 WIRELESS_MODE_UNKNOWN = 0x00,
537 WIRELESS_MODE_A = 0x01,
538 WIRELESS_MODE_B = 0x02,
539 WIRELESS_MODE_G = 0x04,
540 WIRELESS_MODE_AUTO = 0x08,
541 WIRELESS_MODE_N_24G = 0x10,
542 WIRELESS_MODE_N_5G = 0x20
543 } WIRELESS_MODE;
544
545
546 #define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30)
547
548 typedef struct buffer {
549 struct buffer *next;
550 u32 *buf;
551
552 } buffer;
553
554 typedef struct rtl_reg_debug {
555 unsigned int cmd;
556 struct {
557 unsigned char type;
558 unsigned char addr;
559 unsigned char page;
560 unsigned char length;
561 } head;
562 unsigned char buf[0xff];
563 } rtl_reg_debug;
564
565
566
567
568
569
570 typedef struct _rt_9x_tx_rate_history {
571 u32 cck[4];
572 u32 ofdm[8];
573 u32 ht_mcs[4][16];
574 } rt_tx_rahis_t, *prt_tx_rahis_t;
575 typedef struct _RT_SMOOTH_DATA_4RF {
576 char elements[4][100]; /* array to store values */
577 u32 index; /* index to current array to store */
578 u32 TotalNum; /* num of valid elements */
579 u32 TotalVal[4]; /* sum of valid elements */
580 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
581
582 /* This maybe changed for D-cut larger aggregation size */
583 #define MAX_8192U_RX_SIZE 8192
584 /* Stats seems messed up, clean it ASAP */
585 typedef struct Stats {
586 unsigned long txrdu;
587 unsigned long rxok;
588 unsigned long rxframgment;
589 unsigned long rxurberr;
590 unsigned long rxstaterr;
591 /* 0: Total, 1: OK, 2: CRC, 3: ICV */
592 unsigned long received_rate_histogram[4][32];
593 /* 0: Long preamble/GI, 1: Short preamble/GI */
594 unsigned long received_preamble_GI[2][32];
595 /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
596 unsigned long rx_AMPDUsize_histogram[5];
597 /* level: (<5), (5~10), (10~20), (20~40), (>40) */
598 unsigned long rx_AMPDUnum_histogram[5];
599 unsigned long numpacket_matchbssid;
600 unsigned long numpacket_toself;
601 unsigned long num_process_phyinfo;
602 unsigned long numqry_phystatus;
603 unsigned long numqry_phystatusCCK;
604 unsigned long numqry_phystatusHT;
605 /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
606 unsigned long received_bwtype[5];
607 unsigned long txnperr;
608 unsigned long txnpdrop;
609 unsigned long txresumed;
610 unsigned long txnpokint;
611 unsigned long txoverflow;
612 unsigned long txlpokint;
613 unsigned long txlpdrop;
614 unsigned long txlperr;
615 unsigned long txbeokint;
616 unsigned long txbedrop;
617 unsigned long txbeerr;
618 unsigned long txbkokint;
619 unsigned long txbkdrop;
620 unsigned long txbkerr;
621 unsigned long txviokint;
622 unsigned long txvidrop;
623 unsigned long txvierr;
624 unsigned long txvookint;
625 unsigned long txvodrop;
626 unsigned long txvoerr;
627 unsigned long txbeaconokint;
628 unsigned long txbeacondrop;
629 unsigned long txbeaconerr;
630 unsigned long txmanageokint;
631 unsigned long txmanagedrop;
632 unsigned long txmanageerr;
633 unsigned long txdatapkt;
634 unsigned long txfeedback;
635 unsigned long txfeedbackok;
636
637 unsigned long txoktotal;
638 unsigned long txokbytestotal;
639 unsigned long txokinperiod;
640 unsigned long txmulticast;
641 unsigned long txbytesmulticast;
642 unsigned long txbroadcast;
643 unsigned long txbytesbroadcast;
644 unsigned long txunicast;
645 unsigned long txbytesunicast;
646
647 unsigned long rxoktotal;
648 unsigned long rxbytesunicast;
649 unsigned long txfeedbackfail;
650 unsigned long txerrtotal;
651 unsigned long txerrbytestotal;
652 unsigned long txerrmulticast;
653 unsigned long txerrbroadcast;
654 unsigned long txerrunicast;
655 unsigned long txretrycount;
656 unsigned long txfeedbackretry;
657 u8 last_packet_rate;
658 unsigned long slide_signal_strength[100];
659 unsigned long slide_evm[100];
660 /* For recording sliding window's RSSI value */
661 unsigned long slide_rssi_total;
662 /* For recording sliding window's EVM value */
663 unsigned long slide_evm_total;
664 /* Transformed in dbm. Beautified signal strength for UI, not correct */
665 long signal_strength;
666 long signal_quality;
667 long last_signal_strength_inpercent;
668 /* Correct smoothed ss in dbm, only used in driver
669 * to report real power now */
670 long recv_signal_power;
671 u8 rx_rssi_percentage[4];
672 u8 rx_evm_percentage[2];
673 long rxSNRdB[4];
674 rt_tx_rahis_t txrate;
675 /* For beacon RSSI */
676 u32 Slide_Beacon_pwdb[100];
677 u32 Slide_Beacon_Total;
678 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
679
680 u32 CurrentShowTxate;
681 } Stats;
682
683
684 /* Bandwidth Offset */
685 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
686 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
687 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
688
689
690 typedef struct ChnlAccessSetting {
691 u16 SIFS_Timer;
692 u16 DIFS_Timer;
693 u16 SlotTimeTimer;
694 u16 EIFS_Timer;
695 u16 CWminIndex;
696 u16 CWmaxIndex;
697 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
698
699 typedef struct _BB_REGISTER_DEFINITION {
700 /* set software control: 0x870~0x877 [8 bytes] */
701 u32 rfintfs;
702 /* readback data: 0x8e0~0x8e7 [8 bytes] */
703 u32 rfintfi;
704 /* output data: 0x860~0x86f [16 bytes] */
705 u32 rfintfo;
706 /* output enable: 0x860~0x86f [16 bytes] */
707 u32 rfintfe;
708 /* LSSI data: 0x840~0x84f [16 bytes] */
709 u32 rf3wireOffset;
710 /* BB Band Select: 0x878~0x87f [8 bytes] */
711 u32 rfLSSI_Select;
712 /* Tx gain stage: 0x80c~0x80f [4 bytes] */
713 u32 rfTxGainStage;
714 /* wire parameter control1: 0x820~0x823, 0x828~0x82b,
715 * 0x830~0x833, 0x838~0x83b [16 bytes] */
716 u32 rfHSSIPara1;
717 /* wire parameter control2: 0x824~0x827, 0x82c~0x82f,
718 * 0x834~0x837, 0x83c~0x83f [16 bytes] */
719 u32 rfHSSIPara2;
720 /* Tx Rx antenna control: 0x858~0x85f [16 bytes] */
721 u32 rfSwitchControl;
722 /* AGC parameter control1: 0xc50~0xc53, 0xc58~0xc5b,
723 * 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
724 u32 rfAGCControl1;
725 /* AGC parameter control2: 0xc54~0xc57, 0xc5c~0xc5f,
726 * 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
727 u32 rfAGCControl2;
728 /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
729 * 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
730 u32 rfRxIQImbalance;
731 /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
732 * 0xc10~0xc13, 0xc18~0xc1b,
733 * 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
734 u32 rfRxAFE;
735 /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
736 * 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
737 u32 rfTxIQImbalance;
738 /* Tx IQ DC Offset and Tx DFIR type:
739 * 0xc84~0xc87, 0xc8c~0xc8f,
740 * 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
741 u32 rfTxAFE;
742 /* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */
743 u32 rfLSSIReadBack;
744 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
745
746 typedef enum _RT_RF_TYPE_819xU {
747 RF_TYPE_MIN = 0,
748 RF_8225,
749 RF_8256,
750 RF_8258,
751 RF_PSEUDO_11N = 4,
752 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
753
754 typedef struct _rate_adaptive {
755 u8 rate_adaptive_disabled;
756 u8 ratr_state;
757 u16 reserve;
758
759 u32 high_rssi_thresh_for_ra;
760 u32 high2low_rssi_thresh_for_ra;
761 u8 low2high_rssi_thresh_for_ra40M;
762 u32 low_rssi_thresh_for_ra40M;
763 u8 low2high_rssi_thresh_for_ra20M;
764 u32 low_rssi_thresh_for_ra20M;
765 u32 upper_rssi_threshold_ratr;
766 u32 middle_rssi_threshold_ratr;
767 u32 low_rssi_threshold_ratr;
768 u32 low_rssi_threshold_ratr_40M;
769 u32 low_rssi_threshold_ratr_20M;
770 u8 ping_rssi_enable;
771 u32 ping_rssi_ratr;
772 u32 ping_rssi_thresh_for_ra;
773 u32 last_ratr;
774
775 } rate_adaptive, *prate_adaptive;
776
777 #define TxBBGainTableLength 37
778 #define CCKTxBBGainTableLength 23
779
780 typedef struct _txbbgain_struct {
781 long txbb_iq_amplifygain;
782 u32 txbbgain_value;
783 } txbbgain_struct, *ptxbbgain_struct;
784
785 typedef struct _ccktxbbgain_struct {
786 /* The value is from a22 to a29, one byte one time is much safer */
787 u8 ccktxbb_valuearray[8];
788 } ccktxbbgain_struct, *pccktxbbgain_struct;
789
790
791 typedef struct _init_gain {
792 u8 xaagccore1;
793 u8 xbagccore1;
794 u8 xcagccore1;
795 u8 xdagccore1;
796 u8 cca;
797
798 } init_gain, *pinit_gain;
799
800 typedef struct _phy_ofdm_rx_status_report_819xusb {
801 u8 trsw_gain_X[4];
802 u8 pwdb_all;
803 u8 cfosho_X[4];
804 u8 cfotail_X[4];
805 u8 rxevm_X[2];
806 u8 rxsnr_X[4];
807 u8 pdsnr_X[2];
808 u8 csi_current_X[2];
809 u8 csi_target_X[2];
810 u8 sigevm;
811 u8 max_ex_pwr;
812 u8 sgi_en;
813 u8 rxsc_sgien_exflg;
814 } phy_sts_ofdm_819xusb_t;
815
816 typedef struct _phy_cck_rx_status_report_819xusb {
817 /* For CCK rate descriptor. This is an unsigned 8:1 variable.
818 * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
819 * Range from -64~+63.5. */
820 u8 adc_pwdb_X[4];
821 u8 sq_rpt;
822 u8 cck_agc_rpt;
823 } phy_sts_cck_819xusb_t;
824
825
826 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag {
827 u8 reserved:4;
828 u8 rxsc:2;
829 u8 sgi_en:1;
830 u8 ex_intf_flag:1;
831 } phy_ofdm_rx_status_rxsc_sgien_exintfflag;
832
833 typedef enum _RT_CUSTOMER_ID {
834 RT_CID_DEFAULT = 0,
835 RT_CID_8187_ALPHA0 = 1,
836 RT_CID_8187_SERCOMM_PS = 2,
837 RT_CID_8187_HW_LED = 3,
838 RT_CID_8187_NETGEAR = 4,
839 RT_CID_WHQL = 5,
840 RT_CID_819x_CAMEO = 6,
841 RT_CID_819x_RUNTOP = 7,
842 RT_CID_819x_Senao = 8,
843 RT_CID_TOSHIBA = 9,
844 RT_CID_819x_Netcore = 10,
845 RT_CID_Nettronix = 11,
846 RT_CID_DLINK = 12,
847 RT_CID_PRONET = 13,
848 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
849
850 /*
851 * ==========================================================================
852 * LED customization.
853 * ==========================================================================
854 */
855
856 typedef enum _LED_STRATEGY_8190 {
857 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
858 SW_LED_MODE1, /* SW control for PCI Express */
859 SW_LED_MODE2, /* SW control for Cameo. */
860 SW_LED_MODE3, /* SW control for RunTop. */
861 SW_LED_MODE4, /* SW control for Netcore. */
862 /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
863 HW_LED,
864 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
865
866 typedef enum _RESET_TYPE {
867 RESET_TYPE_NORESET = 0x00,
868 RESET_TYPE_NORMAL = 0x01,
869 RESET_TYPE_SILENT = 0x02
870 } RESET_TYPE;
871
872 /* The simple tx command OP code. */
873 typedef enum _tag_TxCmd_Config_Index {
874 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
875 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
876 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
877 TXCMD_SET_TX_DURATION = 0xFF900003,
878 TXCMD_SET_RX_RSSI = 0xFF900004,
879 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
880 TXCMD_XXXX_CTRL,
881 } DCMD_TXCMD_OP;
882
883 typedef struct r8192_priv {
884 struct usb_device *udev;
885 /* For maintain info from eeprom */
886 short epromtype;
887 u16 eeprom_vid;
888 u16 eeprom_pid;
889 u8 eeprom_CustomerID;
890 u8 eeprom_ChannelPlan;
891 RT_CUSTOMER_ID CustomerID;
892 LED_STRATEGY_8190 LedStrategy;
893 u8 txqueue_to_outpipemap[9];
894 int irq;
895 struct ieee80211_device *ieee80211;
896
897 /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
898 short card_8192;
899 /* If TCR reports card V B/C, this discriminates */
900 u8 card_8192_version;
901 short enable_gpio0;
902 enum card_type {
903 PCI, MINIPCI, CARDBUS, USB
904 } card_type;
905 short hw_plcp_len;
906 short plcp_preamble_mode;
907
908 spinlock_t irq_lock;
909 spinlock_t tx_lock;
910 struct mutex mutex;
911
912 u16 irq_mask;
913 short chan;
914 short sens;
915 short max_sens;
916
917
918 short up;
919 /* If 1, allow bad crc frame, reception in monitor mode */
920 short crcmon;
921
922 struct semaphore wx_sem;
923 struct semaphore rf_sem; /* Used to lock rf write operation */
924
925 u8 rf_type; /* 0: 1T2R, 1: 2T4R */
926 RT_RF_TYPE_819xU rf_chip;
927
928 short (*rf_set_sens)(struct net_device *dev, short sens);
929 u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
930 void (*rf_close)(struct net_device *dev);
931 void (*rf_init)(struct net_device *dev);
932 short promisc;
933 /* Stats */
934 struct Stats stats;
935 struct iw_statistics wstats;
936
937 /* RX stuff */
938 struct urb **rx_urb;
939 struct urb **rx_cmd_urb;
940 #ifdef THOMAS_BEACON
941 u32 *oldaddr;
942 #endif
943 #ifdef THOMAS_TASKLET
944 atomic_t irt_counter; /* count for irq_rx_tasklet */
945 #endif
946 #ifdef JACKSON_NEW_RX
947 struct sk_buff **pp_rxskb;
948 int rx_inx;
949 #endif
950
951 struct sk_buff_head rx_queue;
952 struct sk_buff_head skb_queue;
953 struct work_struct qos_activate;
954 short tx_urb_index;
955 atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
956
957
958 struct tasklet_struct irq_rx_tasklet;
959 struct urb *rxurb_task;
960
961 /* Tx Related variables */
962 u16 ShortRetryLimit;
963 u16 LongRetryLimit;
964 u32 TransmitConfig;
965 u8 RegCWinMin; /* For turbo mode CW adaptive */
966
967 u32 LastRxDescTSFHigh;
968 u32 LastRxDescTSFLow;
969
970
971 /* Rx Related variables */
972 u16 EarlyRxThreshold;
973 u32 ReceiveConfig;
974 u8 AcmControl;
975
976 u8 RFProgType;
977
978 u8 retry_data;
979 u8 retry_rts;
980 u16 rts;
981
982 struct ChnlAccessSetting ChannelAccessSetting;
983 struct work_struct reset_wq;
984
985 /**********************************************************/
986 /* For rtl819xUsb */
987 u16 basic_rate;
988 u8 short_preamble;
989 u8 slot_time;
990 bool bDcut;
991 bool bCurrentRxAggrEnable;
992 u8 Rf_Mode; /* For Firmware RF -R/W switch */
993 prt_firmware pFirmware;
994 rtl819xUsb_loopback_e LoopbackMode;
995 u16 EEPROMTxPowerDiff;
996 u8 EEPROMThermalMeter;
997 u8 EEPROMPwDiff;
998 u8 EEPROMCrystalCap;
999 u8 EEPROM_Def_Ver;
1000 u8 EEPROMTxPowerLevelCCK; /* CCK channel 1~14 */
1001 u8 EEPROMTxPowerLevelCCK_V1[3];
1002 u8 EEPROMTxPowerLevelOFDM24G[3]; /* OFDM 2.4G channel 1~14 */
1003 u8 EEPROMTxPowerLevelOFDM5G[24]; /* OFDM 5G */
1004
1005 /* PHY related */
1006 BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */
1007 /* Read/write are allow for following hardware information variables */
1008 u32 MCSTxPowerLevelOriginalOffset[6];
1009 u32 CCKTxPowerLevelOriginalOffset;
1010 u8 TxPowerLevelCCK[14]; /* CCK channel 1~14 */
1011 u8 TxPowerLevelOFDM24G[14]; /* OFDM 2.4G channel 1~14 */
1012 u8 TxPowerLevelOFDM5G[14]; /* OFDM 5G */
1013 u32 Pwr_Track;
1014 u8 TxPowerDiff;
1015 u8 AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
1016 u8 CrystalCap;
1017 u8 ThermalMeter[2]; /* index 0: RFIC0, index 1: RFIC1 */
1018
1019 u8 CckPwEnl;
1020 /* Use to calculate PWBD */
1021 u8 bCckHighPower;
1022 long undecorated_smoothed_pwdb;
1023
1024 /* For set channel */
1025 u8 SwChnlInProgress;
1026 u8 SwChnlStage;
1027 u8 SwChnlStep;
1028 u8 SetBWModeInProgress;
1029 HT_CHANNEL_WIDTH CurrentChannelBW;
1030 u8 ChannelPlan;
1031 /* 8190 40MHz mode */
1032 /* Control channel sub-carrier */
1033 u8 nCur40MhzPrimeSC;
1034 /* Test for shorten RF configuration time.
1035 * We save RF reg0 in this variable to reduce RF reading. */
1036 u32 RfReg0Value[4];
1037 u8 NumTotalRFPath;
1038 bool brfpath_rxenable[4];
1039 /* RF set related */
1040 bool SetRFPowerStateInProgress;
1041 struct timer_list watch_dog_timer;
1042
1043 /* For dynamic mechanism */
1044 /* Tx Power Control for Near/Far Range */
1045 bool bdynamic_txpower;
1046 bool bDynamicTxHighPower;
1047 bool bDynamicTxLowPower;
1048 bool bLastDTPFlag_High;
1049 bool bLastDTPFlag_Low;
1050
1051 bool bstore_last_dtpflag;
1052 /* Define to discriminate on High power State or
1053 * on sitesurvey to change Tx gain index */
1054 bool bstart_txctrl_bydtp;
1055 rate_adaptive rate_adaptive;
1056 /* TX power tracking
1057 * OPEN/CLOSE TX POWER TRACKING */
1058 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1059 u8 txpower_count; /* For 6 sec do tracking again */
1060 bool btxpower_trackingInit;
1061 u8 OFDM_index;
1062 u8 CCK_index;
1063 /* CCK TX Power Tracking */
1064 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1065 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1066 u8 rfa_txpowertrackingindex;
1067 u8 rfa_txpowertrackingindex_real;
1068 u8 rfa_txpowertracking_default;
1069 u8 rfc_txpowertrackingindex;
1070 u8 rfc_txpowertrackingindex_real;
1071
1072 s8 cck_present_attentuation;
1073 u8 cck_present_attentuation_20Mdefault;
1074 u8 cck_present_attentuation_40Mdefault;
1075 char cck_present_attentuation_difference;
1076 bool btxpower_tracking;
1077 bool bcck_in_ch14;
1078 bool btxpowerdata_readfromEEPORM;
1079 u16 TSSI_13dBm;
1080 init_gain initgain_backup;
1081 u8 DefaultInitialGain[4];
1082 /* For EDCA Turbo mode */
1083 bool bis_any_nonbepkts;
1084 bool bcurrent_turbo_EDCA;
1085 bool bis_cur_rdlstate;
1086 struct timer_list fsync_timer;
1087 bool bfsync_processing; /* 500ms Fsync timer is active or not */
1088 u32 rate_record;
1089 u32 rateCountDiffRecord;
1090 u32 ContinueDiffCount;
1091 bool bswitch_fsync;
1092
1093 u8 framesync;
1094 u32 framesyncC34;
1095 u8 framesyncMonitor;
1096 u16 nrxAMPDU_size;
1097 u8 nrxAMPDU_aggr_num;
1098
1099 /* For gpio */
1100 bool bHwRadioOff;
1101
1102 u32 reset_count;
1103 bool bpbc_pressed;
1104 u32 txpower_checkcnt;
1105 u32 txpower_tracking_callback_cnt;
1106 u8 thermal_read_val[40];
1107 u8 thermal_readback_index;
1108 u32 ccktxpower_adjustcnt_not_ch14;
1109 u32 ccktxpower_adjustcnt_ch14;
1110 u8 tx_fwinfo_force_subcarriermode;
1111 u8 tx_fwinfo_force_subcarrierval;
1112 /* For silent reset */
1113 RESET_TYPE ResetProgress;
1114 bool bForcedSilentReset;
1115 bool bDisableNormalResetCheck;
1116 u16 TxCounter;
1117 u16 RxCounter;
1118 int IrpPendingCount;
1119 bool bResetInProgress;
1120 bool force_reset;
1121 u8 InitialGainOperateType;
1122
1123 u16 SifsTime;
1124
1125 /* Define work item */
1126
1127 struct delayed_work update_beacon_wq;
1128 struct delayed_work watch_dog_wq;
1129 struct delayed_work txpower_tracking_wq;
1130 struct delayed_work rfpath_check_wq;
1131 struct delayed_work gpio_change_rf_wq;
1132 struct delayed_work initialgain_operate_wq;
1133 struct workqueue_struct *priv_wq;
1134 } r8192_priv;
1135
1136 /* For rtl8187B */
1137 typedef enum{
1138 BULK_PRIORITY = 0x01,
1139 LOW_PRIORITY,
1140 NORM_PRIORITY,
1141 VO_PRIORITY,
1142 VI_PRIORITY,
1143 BE_PRIORITY,
1144 BK_PRIORITY,
1145 RSVD2,
1146 RSVD3,
1147 BEACON_PRIORITY,
1148 HIGH_PRIORITY,
1149 MANAGE_PRIORITY,
1150 RSVD4,
1151 RSVD5,
1152 UART_PRIORITY
1153 } priority_t;
1154
1155 typedef enum {
1156 NIC_8192U = 1,
1157 NIC_8190P = 2,
1158 NIC_8192E = 3,
1159 } nic_t;
1160
1161
1162 #ifdef JOHN_HWSEC
1163 struct ssid_thread {
1164 struct net_device *dev;
1165 u8 name[IW_ESSID_MAX_SIZE + 1];
1166 };
1167 #endif
1168
1169 bool init_firmware(struct net_device *dev);
1170 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1171 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1172
1173 u32 read_cam(struct net_device *dev, u8 addr);
1174 void write_cam(struct net_device *dev, u8 addr, u32 data);
1175
1176 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1177 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1178 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1179 int read_nic_word(struct net_device *dev, int x, u16 *data);
1180 void write_nic_byte(struct net_device *dev, int x, u8 y);
1181 void write_nic_byte_E(struct net_device *dev, int x, u8 y);
1182 void write_nic_word(struct net_device *dev, int x, u16 y);
1183 void write_nic_dword(struct net_device *dev, int x, u32 y);
1184 void force_pci_posting(struct net_device *dev);
1185
1186 void rtl8192_rtx_disable(struct net_device *);
1187 void rtl8192_rx_enable(struct net_device *);
1188 void rtl8192_tx_enable(struct net_device *);
1189
1190 void rtl8192_disassociate(struct net_device *dev);
1191 void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1192
1193 void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1194 void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1195 void rtl8192_update_msr(struct net_device *dev);
1196 int rtl8192_down(struct net_device *dev);
1197 int rtl8192_up(struct net_device *dev);
1198 void rtl8192_commit(struct net_device *dev);
1199 void rtl8192_set_chan(struct net_device *dev, short ch);
1200 void write_phy(struct net_device *dev, u8 adr, u8 data);
1201 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1202 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1203 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1204 void rtl8192_set_rxconf(struct net_device *dev);
1205 extern void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1206
1207 void EnableHWSecurityConfig8192(struct net_device *dev);
1208 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1209
1210
1211 #endif
Linux with added FPC-III support