drivers/staging/silicom/bypass.h

   1 /******************************************************************************/
   2 /*                                                                            */
   3 /* Bypass Control utility, Copyright (c) 2005 Silicom                         */
   4 /* All rights reserved.                                                       */
   5 /*                                                                            */
   6 /* This program is free software; you can redistribute it and/or modify       */
   7 /* it under the terms of the GNU General Public License as published by       */
   8 /* the Free Software Foundation, located in the file LICENSE.                 */
   9 /*                                                                            */
  10 /*                                                                            */
  11 /******************************************************************************/
  12
  13 #ifndef BYPASS_H
  14 #define BYPASS_H
  15
  16 /* Bypass related */
  17
  18 #define SYNC_CMD_VAL               2    /* 10b */
  19 #define SYNC_CMD_LEN               2
  20
  21 #define WR_CMD_VAL                 2    /* 10b */
  22 #define WR_CMD_LEN                 2
  23
  24 #define RD_CMD_VAL                 1    /* 10b */
  25 #define RD_CMD_LEN                 2
  26
  27 #define ADDR_CMD_LEN               4
  28
  29 #define WR_DATA_LEN                8
  30 #define RD_DATA_LEN                8
  31
  32 #define PIC_SIGN_REG_ADDR          0x7
  33 #define PIC_SIGN_VALUE         0xcd
  34
  35 #define STATUS_REG_ADDR           0
  36 #define WDT_EN_MASK            0x01     /* BIT_0 */
  37 #define CMND_EN_MASK           0x02     /* BIT_1 */
  38 #define DIS_BYPASS_CAP_MASK    0x04     /* BIT_2    Bypass Cap is disable*/
  39 #define DFLT_PWRON_MASK        0x08     /* BIT_3 */
  40 #define BYPASS_OFF_MASK        0x10     /* BIT_4 */
  41 #define BYPASS_FLAG_MASK       0x20     /* BIT_5 */
  42 #define STD_NIC_MASK           (DIS_BYPASS_CAP_MASK | BYPASS_OFF_MASK | DFLT_PWRON_MASK)
  43 #define WD_EXP_FLAG_MASK       0x40     /* BIT_6 */
  44 #define DFLT_PWROFF_MASK       0x80     /* BIT_7 */
  45 #define STD_NIC_PWOFF_MASK     (DIS_BYPASS_CAP_MASK | BYPASS_OFF_MASK | DFLT_PWRON_MASK | DFLT_PWROFF_MASK)
  46
  47 #define PRODUCT_CAP_REG_ADDR   0x5
  48 #define BYPASS_SUPPORT_MASK    0x01     /* BIT_0 */
  49 #define TAP_SUPPORT_MASK       0x02     /* BIT_1 */
  50 #define NORMAL_UNSUPPORT_MASK  0x04     /* BIT_2 */
  51 #define DISC_SUPPORT_MASK      0x08     /* BIT_3 */
  52 #define TPL2_SUPPORT_MASK      0x10     /* BIT_4 */
  53 #define DISC_PORT_SUPPORT_MASK 0x20     /* BIT_5 */
  54
  55 #define STATUS_TAP_REG_ADDR    0x6
  56 #define WDTE_TAP_BPN_MASK      0x01     /* BIT_1    1 when wdt expired -> TAP, 0 - Bypass */
  57 #define DIS_TAP_CAP_MASK       0x04     /* BIT_2    TAP Cap is disable*/
  58 #define DFLT_PWRON_TAP_MASK    0x08     /* BIT_3    */
  59 #define TAP_OFF_MASK           0x10     /* BIT_4    */
  60 #define TAP_FLAG_MASK          0x20     /* BIT_5    */
  61 #define TX_DISA_MASK            0x40
  62 #define TX_DISB_MASK            0x80
  63
  64 #define STD_NIC_TAP_MASK       (DIS_TAP_CAP_MASK | TAP_OFF_MASK | DFLT_PWRON_TAP_MASK)
  65
  66 #define STATUS_DISC_REG_ADDR    13
  67 #define WDTE_DISC_BPN_MASK      0x01    /* BIT_0    1 when wdt expired -> TAP, 0 - Bypass */
  68 #define STD_NIC_ON_MASK         0x02    /* BIT_1    */
  69 #define DIS_DISC_CAP_MASK       0x04    /* BIT_2    TAP Cap is disable*/
  70 #define DFLT_PWRON_DISC_MASK    0x08    /* BIT_3    */
  71 #define DISC_OFF_MASK           0x10    /* BIT_4    */
  72 #define DISC_FLAG_MASK          0x20    /* BIT_5    */
  73 #define TPL2_FLAG_MASK          0x40    /* BIT_6    */
  74 #define STD_NIC_DISC_MASK       DIS_DISC_CAP_MASK
  75
  76 #define CONT_CONFIG_REG_ADDR    12
  77 #define EN_HW_RESET_MASK       0x2      /* BIT_1 */
  78 #define WAIT_AT_PWUP_MASK      0x1      /* BIT_0 */
  79
  80 #define VER_REG_ADDR               0x1
  81 #define BP_FW_VER_A0         0xa0
  82 #define BP_FW_VER_A1         0xa1
  83
  84 #define INT_VER_MASK           0xf0
  85 #define EXT_VER_MASK           0xf
  86 /* */
  87 #define PXG2BPI_VER            0x0
  88 #define PXG2TBPI_VER           0x1
  89 #define PXE2TBPI_VER           0x2
  90 #define PXG4BPFI_VER           0x4
  91 #define BP_FW_EXT_VER7         0x6
  92 #define BP_FW_EXT_VER8         0x8
  93 #define BP_FW_EXT_VER9         0x9
  94
  95 #define OLD_IF_VER              -1
  96
  97 #define CMND_REG_ADDR              10   /* 1010b */
  98 #define WDT_REG_ADDR               4
  99 #define TMRL_REG_ADDR              2
 100 #define TMRH_REG_ADDR              3
 101
 102 /* NEW_FW */
 103 #define WDT_INTERVAL               1    /* 5     //8   */
 104 #define WDT_CMND_INTERVAL          200  /* 50          */
 105 #define CMND_INTERVAL              200  /* 100    usec */
 106 #define PULSE_TIME                 100
 107
 108 /* OLD_FW */
 109 #define INIT_CMND_INTERVAL         40
 110 #define PULSE_INTERVAL             5
 111 #define WDT_TIME_CNT               3
 112
 113 /* Intel Commands */
 114
 115 #define CMND_OFF_INT               0xf
 116 #define PWROFF_BYPASS_ON_INT       0x5
 117 #define BYPASS_ON_INT              0x6
 118 #define DIS_BYPASS_CAP_INT         0x4
 119 #define RESET_WDT_INT              0x1
 120
 121 /* Intel timing */
 122
 123 #define BYPASS_DELAY_INT           4    /* msec */
 124 #define CMND_INTERVAL_INT          2    /* msec */
 125
 126 /* Silicom Commands */
 127 #define CMND_ON                    0x4
 128 #define CMND_OFF                   0x2
 129 #define BYPASS_ON                  0xa
 130 #define BYPASS_OFF                 0x8
 131 #define PORT_LINK_EN               0xe
 132 #define PORT_LINK_DIS              0xc
 133 #define WDT_ON                     0x10 /* 0x1f (11111) - max */
 134 #define TIMEOUT_UNIT           100
 135 #define TIMEOUT_MAX_STEP       15
 136 #define WDT_TIMEOUT_MIN        100      /*  msec */
 137 #define WDT_TIMEOUT_MAX        3276800  /*  msec */
 138 #define WDT_AUTO_MIN_INT           500
 139 #define WDT_TIMEOUT_DEF        WDT_TIMEOUT_MIN
 140 #define WDT_OFF                    0x6
 141 #define WDT_RELOAD                 0x9
 142 #define RESET_CONT                 0x20
 143 #define DIS_BYPASS_CAP             0x22
 144 #define EN_BYPASS_CAP              0x24
 145 #define BYPASS_STATE_PWRON         0x26
 146 #define NORMAL_STATE_PWRON         0x28
 147 #define BYPASS_STATE_PWROFF        0x27
 148 #define NORMAL_STATE_PWROFF        0x29
 149 #define TAP_ON                     0xb
 150 #define TAP_OFF                    0x9
 151 #define TAP_STATE_PWRON            0x2a
 152 #define DIS_TAP_CAP                0x2c
 153 #define EN_TAP_CAP                 0x2e
 154 #define STD_NIC_OFF       0x86
 155 #define STD_NIC_ON       0x84
 156 #define DISC_ON           0x85
 157 #define DISC_OFF          0x8a
 158 #define DISC_STATE_PWRON  0x87
 159 #define DIS_DISC_CAP      0x88
 160 #define EN_DISC_CAP       0x89
 161 #define TPL2_ON                    0x8c
 162 #define TPL2_OFF                   0x8b
 163 #define BP_WAIT_AT_PWUP_EN        0x80
 164 #define BP_WAIT_AT_PWUP_DIS       0x81
 165 #define BP_HW_RESET_EN             0x82
 166 #define BP_HW_RESET_DIS            0x83
 167
 168 #define TX_DISA                0x8d
 169 #define TX_DISB                0x8e
 170 #define TX_ENA                 0xA0
 171 #define TX_ENB                 0xA1
 172
 173 #define TX_DISA_PWRUP          0xA2
 174 #define TX_DISB_PWRUP          0xA3
 175 #define TX_ENA_PWRUP           0xA4
 176 #define TX_ENB_PWRUP           0xA5
 177
 178 #define BYPASS_CAP_DELAY           21   /* msec */
 179 #define DFLT_PWRON_DELAY           10   /* msec */
 180 #define LATCH_DELAY                13   /* msec */
 181 #define EEPROM_WR_DELAY             8   /* msec */
 182
 183 #define BP_LINK_MON_DELAY          4    /* sec */
 184
 185 #define BP_FW_EXT_VER0                 0xa0
 186 #define BP_FW_EXT_VER1                 0xa1
 187 #define BP_FW_EXT_VER2                0xb1
 188
 189 #define BP_OK        0
 190 #define BP_NOT_CAP  -1
 191 #define WDT_STATUS_EXP -2
 192 #define WDT_STATUS_UNKNOWN -1
 193 #define WDT_STATUS_EN 1
 194 #define WDT_STATUS_DIS 0
 195
 196 #ifdef BP_SELF_TEST
 197 #define ETH_P_BPTEST 0xabba
 198
 199 #define BPTEST_DATA_LEN 60
 200 #endif
 201
 202 #endif                          /* BYPASS_H */