| blob | c26418d806fb335851bb7a688ad1294094cc8a6d |
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: baseband.c
21 *
22 * Purpose: Implement functions to access baseband
23 *
24 * Author: Kyle Hsu
25 *
26 * Date: Aug.22, 2002
27 *
28 * Functions:
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
39 *
40 * Revision History:
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
45 * Add the comments.
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
48 *
49 *
50 */
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
77 #define CB_VT3253_INIT_FOR_RFMD 446
525 };
527 #define CB_VT3253B0_INIT_FOR_RFMD 256
785 };
787 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
788 // For RFMD2959
985 };
987 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
988 // For AIROHA
1098 //{0x6c, 0x80},
1247 };
1249 #define CB_VT3253B0_INIT_FOR_UW2451 256
1250 //For UW2451
1360 //{0x6c, 0x80},
1509 };
1511 #define CB_VT3253B0_AGC 193
1512 // For AIROHA
1707 };
1712 /*--------------------- Static Functions --------------------------*/
1714 static
1715 unsigned long
1718 static
1719 void
1721 PSDevice pDevice
1722 );
1724 static
1725 void
1727 PSDevice pDevice
1728 )
1729 {
1734 else
1740 else
1742 }
1749 }
1750 }
1752 /*--------------------- Export Variables --------------------------*/
1753 /*
1754 * Description: Calculate data frame transmitting time
1755 *
1756 * Parameters:
1757 * In:
1758 * byPreambleType - Preamble Type
1759 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1760 * cbFrameLength - Baseband Type
1761 * wRate - Tx Rate
1762 * Out:
1763 *
1764 * Return Value: FrameTime
1765 *
1766 */
1767 unsigned int
1772 unsigned short wRate
1773 )
1774 {
1784 }
1794 }
1798 uFrameTime++;
1799 }
1806 uFrameTime++;
1807 }
1811 }
1813 }
1814 }
1816 /*
1817 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1818 *
1819 * Parameters:
1820 * In:
1821 * pDevice - Device Structure
1822 * cbFrameLength - Tx Frame Length
1823 * wRate - Tx Rate
1824 * Out:
1825 * pwPhyLen - pointer to Phy Length field
1826 * pbyPhySrv - pointer to Phy Service field
1827 * pbyPhySgn - pointer to Phy Signal field
1828 *
1829 * Return Value: none
1830 *
1831 */
1832 void
1834 PSDevice pDevice,
1841 )
1842 {
1869 cbBitCount++;
1873 cbUsCount++;
1883 cbBitCount++;
1887 cbUsCount++;
1890 }
1902 }
1910 }
1918 }
1926 }
1934 }
1942 }
1950 }
1958 }
1966 }
1968 }
1978 }
1979 }
1981 /*
1982 * Description: Read a byte from BASEBAND, by embedded programming
1983 *
1984 * Parameters:
1985 * In:
1986 * dwIoBase - I/O base address
1987 * byBBAddr - address of register in Baseband
1988 * Out:
1989 * pbyData - data read
1990 *
1991 * Return Value: true if succeeded; false if failed.
1992 *
1993 */
1995 {
1999 // BB reg offset
2002 // turn on REGR
2004 // W_MAX_TIMEOUT is the timeout period
2009 }
2011 // get BB data
2018 }
2020 }
2022 /*
2023 * Description: Write a Byte to BASEBAND, by embedded programming
2024 *
2025 * Parameters:
2026 * In:
2027 * dwIoBase - I/O base address
2028 * byBBAddr - address of register in Baseband
2029 * byData - data to write
2030 * Out:
2031 * none
2032 *
2033 * Return Value: true if succeeded; false if failed.
2034 *
2035 */
2037 {
2041 // BB reg offset
2043 // set BB data
2046 // turn on BBREGCTL_REGW
2048 // W_MAX_TIMEOUT is the timeout period
2053 }
2059 }
2061 }
2063 /*
2064 * Description: Test if all bits are set for the Baseband register
2065 *
2066 * Parameters:
2067 * In:
2068 * dwIoBase - I/O base address
2069 * byBBAddr - address of register in Baseband
2070 * byTestBits - TestBits
2071 * Out:
2072 * none
2073 *
2074 * Return Value: true if all TestBits are set; false otherwise.
2075 *
2076 */
2078 {
2083 }
2085 /*
2086 * Description: Test if all bits are clear for the Baseband register
2087 *
2088 * Parameters:
2089 * In:
2090 * dwIoBase - I/O base address
2091 * byBBAddr - address of register in Baseband
2092 * byTestBits - TestBits
2093 * Out:
2094 * none
2095 *
2096 * Return Value: true if all TestBits are clear; false otherwise.
2097 *
2098 */
2100 {
2105 }
2107 /*
2108 * Description: VIA VT3253 Baseband chip init function
2109 *
2110 * Parameters:
2111 * In:
2112 * dwIoBase - I/O base address
2113 * byRevId - Revision ID
2114 * byRFType - RF type
2115 * Out:
2116 * none
2117 *
2118 * Return Value: true if succeeded; false if failed.
2119 *
2120 */
2123 {
2133 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2134 }
2138 }
2140 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2141 }
2144 }
2155 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2156 }
2159 }
2171 }
2174 }
2189 }
2190 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2191 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2192 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2193 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2194 // Select VC1/VC2, CR215 = 0x02->0x06
2197 //{{RobertYu:20050125, request by Jack
2200 //}}
2202 //{{RobertYu:20050221, request by Jack
2205 //}}
2210 }
2211 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2212 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2222 //}} RobertYu
2226 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2227 }
2230 }
2239 // Fix VT3226 DFC system timing issue
2241 //{{ RobertYu: 20050104
2244 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2245 }
2247 //{{ RobertYu:20050223, request by JerryChung
2248 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2249 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2250 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2251 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2252 // Select VC1/VC2, CR215 = 0x02->0x06
2254 //}}
2258 }
2267 //}} RobertYu
2269 // No VGA Table now
2272 }
2277 }
2280 }
2282 /*
2283 * Description: Read All Baseband Registers
2284 *
2285 * Parameters:
2286 * In:
2287 * dwIoBase - I/O base address
2288 * pbyBBRegs - Point to struct that stores Baseband Registers
2289 * Out:
2290 * none
2291 *
2292 * Return Value: none
2293 *
2294 */
2296 {
2302 }
2303 }
2305 /*
2306 * Description: Turn on BaseBand Loopback mode
2307 *
2308 * Parameters:
2309 * In:
2310 * dwIoBase - I/O base address
2311 * bCCK - If CCK is set
2312 * Out:
2313 * none
2314 *
2315 * Return Value: none
2316 *
2317 */
2320 {
2324 //CR C9 = 0x00
2330 //CR 88 = 0x02(CCK), 0x03(OFDM)
2334 // Enable internal digital loopback: CR33 |= 0000 0001
2337 // CR154 = 0x00
2342 // Enable internal digital loopback:CR154 |= 0000 0001
2345 // CR33 = 0x00
2349 }
2351 //CR14 = 0x00
2354 // Disable TX_IQUN
2357 }
2359 /*
2360 * Description: Turn off BaseBand Loopback mode
2361 *
2362 * Parameters:
2363 * In:
2364 * pDevice - Device Structure
2365 *
2366 * Out:
2367 * none
2368 *
2369 * Return Value: none
2370 *
2371 */
2373 {
2383 // Set the CR33 Bit2 to disable internal Loopback.
2389 }
2392 }
2394 /*
2395 * Description: Set ShortSlotTime mode
2396 *
2397 * Parameters:
2398 * In:
2399 * pDevice - Device Structure
2400 * Out:
2401 * none
2402 *
2403 * Return Value: none
2404 *
2405 */
2406 void
2408 {
2418 }
2420 // patch for 3253B0 Baseband with Cardbus module
2424 }
2427 }
2430 {
2436 // patch for 3253B0 Baseband with Cardbus module
2443 }
2446 }
2448 /*
2449 * Description: Baseband SoftwareReset
2450 *
2451 * Parameters:
2452 * In:
2453 * dwIoBase - I/O base address
2454 * Out:
2455 * none
2456 *
2457 * Return Value: none
2458 *
2459 */
2460 void
2462 {
2467 }
2469 /*
2470 * Description: Baseband Power Save Mode ON
2471 *
2472 * Parameters:
2473 * In:
2474 * dwIoBase - I/O base address
2475 * Out:
2476 * none
2477 *
2478 * Return Value: none
2479 *
2480 */
2481 void
2483 {
2489 }
2491 /*
2492 * Description: Baseband Power Save Mode OFF
2493 *
2494 * Parameters:
2495 * In:
2496 * dwIoBase - I/O base address
2497 * Out:
2498 * none
2499 *
2500 * Return Value: none
2501 *
2502 */
2503 void
2505 {
2511 }
2513 /*
2514 * Description: Set Tx Antenna mode
2515 *
2516 * Parameters:
2517 * In:
2518 * pDevice - Device Structure
2519 * byAntennaMode - Antenna Mode
2520 * Out:
2521 * none
2522 *
2523 * Return Value: none
2524 *
2525 */
2527 void
2529 {
2534 // bit 1 is diversity
2537 // bit 2 is ANTSEL
2542 }
2544 }
2546 /*
2547 * Description: Set Rx Antenna mode
2548 *
2549 * Parameters:
2550 * In:
2551 * pDevice - Device Structure
2552 * byAntennaMode - Antenna Mode
2553 * Out:
2554 * none
2555 *
2556 * Return Value: none
2557 *
2558 */
2560 void
2562 {
2574 }
2576 }
2578 /*
2579 * Description: BBvSetDeepSleep
2580 *
2581 * Parameters:
2582 * In:
2583 * pDevice - Device Structure
2584 * Out:
2585 * none
2586 *
2587 * Return Value: none
2588 *
2589 */
2590 void
2592 {
2595 }
2597 void
2599 {
2602 }
2604 static
2605 unsigned long
2607 {
2612 //This is a thousand-ratio
2617 //ulRatio = (pDevice->uNumSQ3[RATE_54M] * 1000 / pDevice->uDiversityCnt);
2619 }
2623 //ulRatio = (pDevice->uNumSQ3[RATE_48M] * 1000 / pDevice->uDiversityCnt);
2626 }
2631 //ulRatio = (pDevice->uNumSQ3[RATE_36M] * 1000 / pDevice->uDiversityCnt);
2634 }
2639 //ulRatio = (pDevice->uNumSQ3[RATE_24M] * 1000 / pDevice->uDiversityCnt);
2642 }
2648 //ulRatio = (pDevice->uNumSQ3[RATE_18M] * 1000 / pDevice->uDiversityCnt);
2651 }
2657 //ulRatio = (pDevice->uNumSQ3[RATE_12M] * 1000 / pDevice->uDiversityCnt);
2660 }
2666 //ulRatio = (pDevice->uNumSQ3[RATE_11M] * 1000 / pDevice->uDiversityCnt);
2669 }
2675 //ulRatio = (pDevice->uNumSQ3[RATE_9M] * 1000 / pDevice->uDiversityCnt);
2678 }
2683 //ulRatio = (pDevice->uNumSQ3[RATE_6M] * 1000 / pDevice->uDiversityCnt);
2686 }
2691 //ulRatio = (pDevice->uNumSQ3[RATE_5M] * 1000 / pDevice->uDiversityCnt);
2694 }
2698 //ulRatio = (pDevice->uNumSQ3[RATE_2M] * 1000 / pDevice->uDiversityCnt);
2701 }
2705 //ulRatio = (pDevice->uNumSQ3[RATE_1M] * 1000 / pDevice->uDiversityCnt);
2707 }
2710 }
2712 void
2714 {
2720 }
2721 }
2723 /*
2724 * Description: Antenna Diversity
2725 *
2726 * Parameters:
2727 * In:
2728 * pDevice - Device Structure
2729 * byRSR - RSR from received packet
2730 * bySQ3 - SQ3 value from received packet
2731 * Out:
2732 * none
2733 *
2734 * Return Value: none
2735 *
2736 */
2738 void
2740 {
2743 }
2745 // DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "pDevice->uDiversityCnt = %d\n", (int)pDevice->uDiversityCnt);
2756 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2774 }
2777 }
2798 }
2801 }
2803 }
2805 /*+
2806 *
2807 * Description:
2808 * Timer for SQ3 antenna diversity
2809 *
2810 * Parameters:
2811 * In:
2812 * Out:
2813 * none
2814 *
2815 * Return Value: none
2816 *
2817 -*/
2819 void
2822 )
2823 {
2829 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "3.[%08x][%08x], %d\n", (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2842 }
2844 /*+
2845 *
2846 * Description:
2847 * Timer for SQ3 antenna diversity
2848 *
2849 * Parameters:
2850 * In:
2851 * pvSysSpec1
2852 * hDeviceContext - Pointer to the adapter
2853 * pvSysSpec2
2854 * pvSysSpec3
2855 * Out:
2856 * none
2857 *
2858 * Return Value: none
2859 *
2860 -*/
2862 void
2865 )
2866 {
2895 }
2896 }
2902 }