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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / staging / vt6655 / mac.h
blob3f177f7c581c1c8a88ac182f7a3db49f0ff27a91
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 *
20 * File: mac.h
21 *
22 * Purpose: MAC routines
23 *
24 * Author: Tevin Chen
25 *
26 * Date: May 21, 1996
27 *
28 * Revision History:
29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
32 */
33
34 #ifndef __MAC_H__
35 #define __MAC_H__
36
37 #include "ttype.h"
38 #include "tmacro.h"
39 #include "upc.h"
40
41 /*--------------------- Export Definitions -------------------------*/
42 //
43 // Registers in the MAC
44 //
45 #define MAC_MAX_CONTEXT_SIZE_PAGE0 256
46 #define MAC_MAX_CONTEXT_SIZE_PAGE1 128
47 #define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
48
49 // Registers not related to 802.11b
50 #define MAC_REG_BCFG0 0x00
51 #define MAC_REG_BCFG1 0x01
52 #define MAC_REG_FCR0 0x02
53 #define MAC_REG_FCR1 0x03
54 #define MAC_REG_BISTCMD 0x04
55 #define MAC_REG_BISTSR0 0x05
56 #define MAC_REG_BISTSR1 0x06
57 #define MAC_REG_BISTSR2 0x07
58 #define MAC_REG_I2MCSR 0x08
59 #define MAC_REG_I2MTGID 0x09
60 #define MAC_REG_I2MTGAD 0x0A
61 #define MAC_REG_I2MCFG 0x0B
62 #define MAC_REG_I2MDIPT 0x0C
63 #define MAC_REG_I2MDOPT 0x0E
64 #define MAC_REG_PMC0 0x10
65 #define MAC_REG_PMC1 0x11
66 #define MAC_REG_STICKHW 0x12
67 #define MAC_REG_LOCALID 0x14
68 #define MAC_REG_TESTCFG 0x15
69 #define MAC_REG_JUMPER0 0x16
70 #define MAC_REG_JUMPER1 0x17
71 #define MAC_REG_TMCTL0 0x18
72 #define MAC_REG_TMCTL1 0x19
73 #define MAC_REG_TMDATA0 0x1C
74 // MAC Parameter related
75 #define MAC_REG_LRT 0x20 //
76 #define MAC_REG_SRT 0x21 //
77 #define MAC_REG_SIFS 0x22 //
78 #define MAC_REG_DIFS 0x23 //
79 #define MAC_REG_EIFS 0x24 //
80 #define MAC_REG_SLOT 0x25 //
81 #define MAC_REG_BI 0x26 //
82 #define MAC_REG_CWMAXMIN0 0x28 //
83 #define MAC_REG_LINKOFFTOTM 0x2A
84 #define MAC_REG_SWTMOT 0x2B
85 #define MAC_REG_MIBCNTR 0x2C
86 #define MAC_REG_RTSOKCNT 0x2C
87 #define MAC_REG_RTSFAILCNT 0x2D
88 #define MAC_REG_ACKFAILCNT 0x2E
89 #define MAC_REG_FCSERRCNT 0x2F
90 // TSF Related
91 #define MAC_REG_TSFCNTR 0x30 //
92 #define MAC_REG_NEXTTBTT 0x38 //
93 #define MAC_REG_TSFOFST 0x40 //
94 #define MAC_REG_TFTCTL 0x48 //
95 // WMAC Control/Status Related
96 #define MAC_REG_ENCFG 0x4C //
97 #define MAC_REG_PAGE1SEL 0x4F //
98 #define MAC_REG_CFG 0x50 //
99 #define MAC_REG_TEST 0x52 //
100 #define MAC_REG_HOSTCR 0x54 //
101 #define MAC_REG_MACCR 0x55 //
102 #define MAC_REG_RCR 0x56 //
103 #define MAC_REG_TCR 0x57 //
104 #define MAC_REG_IMR 0x58 //
105 #define MAC_REG_ISR 0x5C
106 // Power Saving Related
107 #define MAC_REG_PSCFG 0x60 //
108 #define MAC_REG_PSCTL 0x61 //
109 #define MAC_REG_PSPWRSIG 0x62 //
110 #define MAC_REG_BBCR13 0x63
111 #define MAC_REG_AIDATIM 0x64
112 #define MAC_REG_PWBT 0x66
113 #define MAC_REG_WAKEOKTMR 0x68
114 #define MAC_REG_CALTMR 0x69
115 #define MAC_REG_SYNSPACCNT 0x6A
116 #define MAC_REG_WAKSYNOPT 0x6B
117 // Baseband/IF Control Group
118 #define MAC_REG_BBREGCTL 0x6C //
119 #define MAC_REG_CHANNEL 0x6D
120 #define MAC_REG_BBREGADR 0x6E
121 #define MAC_REG_BBREGDATA 0x6F
122 #define MAC_REG_IFREGCTL 0x70 //
123 #define MAC_REG_IFDATA 0x71 //
124 #define MAC_REG_ITRTMSET 0x74 //
125 #define MAC_REG_PAPEDELAY 0x77
126 #define MAC_REG_SOFTPWRCTL 0x78 //
127 #define MAC_REG_GPIOCTL0 0x7A //
128 #define MAC_REG_GPIOCTL1 0x7B //
129
130 // MAC DMA Related Group
131 #define MAC_REG_TXDMACTL0 0x7C //
132 #define MAC_REG_TXDMAPTR0 0x80 //
133 #define MAC_REG_AC0DMACTL 0x84 //
134 #define MAC_REG_AC0DMAPTR 0x88 //
135 #define MAC_REG_BCNDMACTL 0x8C //
136 #define MAC_REG_BCNDMAPTR 0x90 //
137 #define MAC_REG_RXDMACTL0 0x94 //
138 #define MAC_REG_RXDMAPTR0 0x98 //
139 #define MAC_REG_RXDMACTL1 0x9C //
140 #define MAC_REG_RXDMAPTR1 0xA0 //
141 #define MAC_REG_SYNCDMACTL 0xA4 //
142 #define MAC_REG_SYNCDMAPTR 0xA8
143 #define MAC_REG_ATIMDMACTL 0xAC
144 #define MAC_REG_ATIMDMAPTR 0xB0
145 // MiscFF PIO related
146 #define MAC_REG_MISCFFNDEX 0xB4
147 #define MAC_REG_MISCFFCTL 0xB6
148 #define MAC_REG_MISCFFDATA 0xB8
149 // Extend SW Timer
150 #define MAC_REG_TMDATA1 0xBC
151 // WOW Related Group
152 #define MAC_REG_WAKEUPEN0 0xC0
153 #define MAC_REG_WAKEUPEN1 0xC1
154 #define MAC_REG_WAKEUPSR0 0xC2
155 #define MAC_REG_WAKEUPSR1 0xC3
156 #define MAC_REG_WAKE128_0 0xC4
157 #define MAC_REG_WAKE128_1 0xD4
158 #define MAC_REG_WAKE128_2 0xE4
159 #define MAC_REG_WAKE128_3 0xF4
160
161 /////////////// Page 1 ///////////////////
162 #define MAC_REG_CRC_128_0 0x04
163 #define MAC_REG_CRC_128_1 0x06
164 #define MAC_REG_CRC_128_2 0x08
165 #define MAC_REG_CRC_128_3 0x0A
166 // MAC Configuration Group
167 #define MAC_REG_PAR0 0x0C
168 #define MAC_REG_PAR4 0x10
169 #define MAC_REG_BSSID0 0x14
170 #define MAC_REG_BSSID4 0x18
171 #define MAC_REG_MAR0 0x1C
172 #define MAC_REG_MAR4 0x20
173 // MAC RSPPKT INFO Group
174 #define MAC_REG_RSPINF_B_1 0x24
175 #define MAC_REG_RSPINF_B_2 0x28
176 #define MAC_REG_RSPINF_B_5 0x2C
177 #define MAC_REG_RSPINF_B_11 0x30
178 #define MAC_REG_RSPINF_A_6 0x34
179 #define MAC_REG_RSPINF_A_9 0x36
180 #define MAC_REG_RSPINF_A_12 0x38
181 #define MAC_REG_RSPINF_A_18 0x3A
182 #define MAC_REG_RSPINF_A_24 0x3C
183 #define MAC_REG_RSPINF_A_36 0x3E
184 #define MAC_REG_RSPINF_A_48 0x40
185 #define MAC_REG_RSPINF_A_54 0x42
186 #define MAC_REG_RSPINF_A_72 0x44
187
188 // 802.11h relative
189 #define MAC_REG_QUIETINIT 0x60
190 #define MAC_REG_QUIETGAP 0x62
191 #define MAC_REG_QUIETDUR 0x64
192 #define MAC_REG_MSRCTL 0x66
193 #define MAC_REG_MSRBBSTS 0x67
194 #define MAC_REG_MSRSTART 0x68
195 #define MAC_REG_MSRDURATION 0x70
196 #define MAC_REG_CCAFRACTION 0x72
197 #define MAC_REG_PWRCCK 0x73
198 #define MAC_REG_PWROFDM 0x7C
199
200 //
201 // Bits in the BCFG0 register
202 //
203 #define BCFG0_PERROFF 0x40
204 #define BCFG0_MRDMDIS 0x20
205 #define BCFG0_MRDLDIS 0x10
206 #define BCFG0_MWMEN 0x08
207 #define BCFG0_VSERREN 0x02
208 #define BCFG0_LATMEN 0x01
209
210 //
211 // Bits in the BCFG1 register
212 //
213 #define BCFG1_CFUNOPT 0x80
214 #define BCFG1_CREQOPT 0x40
215 #define BCFG1_DMA8 0x10
216 #define BCFG1_ARBITOPT 0x08
217 #define BCFG1_PCIMEN 0x04
218 #define BCFG1_MIOEN 0x02
219 #define BCFG1_CISDLYEN 0x01
220
221 // Bits in RAMBIST registers
222 #define BISTCMD_TSTPAT5 0x00 //
223 #define BISTCMD_TSTPATA 0x80 //
224 #define BISTCMD_TSTERR 0x20 //
225 #define BISTCMD_TSTPATF 0x18 //
226 #define BISTCMD_TSTPAT0 0x10 //
227 #define BISTCMD_TSTMODE 0x04 //
228 #define BISTCMD_TSTITTX 0x03 //
229 #define BISTCMD_TSTATRX 0x02 //
230 #define BISTCMD_TSTATTX 0x01 //
231 #define BISTCMD_TSTRX 0x00 //
232 #define BISTSR0_BISTGO 0x01 //
233 #define BISTSR1_TSTSR 0x01 //
234 #define BISTSR2_CMDPRTEN 0x02 //
235 #define BISTSR2_RAMTSTEN 0x01 //
236
237 //
238 // Bits in the I2MCFG EEPROM register
239 //
240 #define I2MCFG_BOUNDCTL 0x80
241 #define I2MCFG_WAITCTL 0x20
242 #define I2MCFG_SCLOECTL 0x10
243 #define I2MCFG_WBUSYCTL 0x08
244 #define I2MCFG_NORETRY 0x04
245 #define I2MCFG_I2MLDSEQ 0x02
246 #define I2MCFG_I2CMFAST 0x01
247
248 //
249 // Bits in the I2MCSR EEPROM register
250 //
251 #define I2MCSR_EEMW 0x80
252 #define I2MCSR_EEMR 0x40
253 #define I2MCSR_AUTOLD 0x08
254 #define I2MCSR_NACK 0x02
255 #define I2MCSR_DONE 0x01
256
257 //
258 // Bits in the PMC1 register
259 //
260 #define SPS_RST 0x80
261 #define PCISTIKY 0x40
262 #define PME_OVR 0x02
263
264 //
265 // Bits in the STICKYHW register
266 //
267 #define STICKHW_DS1_SHADOW 0x02
268 #define STICKHW_DS0_SHADOW 0x01
269
270 //
271 // Bits in the TMCTL register
272 //
273 #define TMCTL_TSUSP 0x04
274 #define TMCTL_TMD 0x02
275 #define TMCTL_TE 0x01
276
277 //
278 // Bits in the TFTCTL register
279 //
280 #define TFTCTL_HWUTSF 0x80 //
281 #define TFTCTL_TBTTSYNC 0x40
282 #define TFTCTL_HWUTSFEN 0x20
283 #define TFTCTL_TSFCNTRRD 0x10 //
284 #define TFTCTL_TBTTSYNCEN 0x08 //
285 #define TFTCTL_TSFSYNCEN 0x04 //
286 #define TFTCTL_TSFCNTRST 0x02 //
287 #define TFTCTL_TSFCNTREN 0x01 //
288
289 //
290 // Bits in the EnhanceCFG register
291 //
292 #define EnCFG_BarkerPream 0x00020000
293 #define EnCFG_NXTBTTCFPSTR 0x00010000
294 #define EnCFG_BcnSusClr 0x00000200
295 #define EnCFG_BcnSusInd 0x00000100
296 #define EnCFG_CFP_ProtectEn 0x00000040
297 #define EnCFG_ProtectMd 0x00000020
298 #define EnCFG_HwParCFP 0x00000010
299 #define EnCFG_CFNULRSP 0x00000004
300 #define EnCFG_BBType_MASK 0x00000003
301 #define EnCFG_BBType_g 0x00000002
302 #define EnCFG_BBType_b 0x00000001
303 #define EnCFG_BBType_a 0x00000000
304
305 //
306 // Bits in the Page1Sel register
307 //
308 #define PAGE1_SEL 0x01
309
310 //
311 // Bits in the CFG register
312 //
313 #define CFG_TKIPOPT 0x80
314 #define CFG_RXDMAOPT 0x40
315 #define CFG_TMOT_SW 0x20
316 #define CFG_TMOT_HWLONG 0x10
317 #define CFG_TMOT_HW 0x00
318 #define CFG_CFPENDOPT 0x08
319 #define CFG_BCNSUSEN 0x04
320 #define CFG_NOTXTIMEOUT 0x02
321 #define CFG_NOBUFOPT 0x01
322
323 //
324 // Bits in the TEST register
325 //
326 #define TEST_LBEXT 0x80 //
327 #define TEST_LBINT 0x40 //
328 #define TEST_LBNONE 0x00 //
329 #define TEST_SOFTINT 0x20 //
330 #define TEST_CONTTX 0x10 //
331 #define TEST_TXPE 0x08 //
332 #define TEST_NAVDIS 0x04 //
333 #define TEST_NOCTS 0x02 //
334 #define TEST_NOACK 0x01 //
335
336 //
337 // Bits in the HOSTCR register
338 //
339 #define HOSTCR_TXONST 0x80 //
340 #define HOSTCR_RXONST 0x40 //
341 #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
342 #define HOSTCR_AP 0x10 // Port Type 1 = AP
343 #define HOSTCR_TXON 0x08 //0000 1000
344 #define HOSTCR_RXON 0x04 //0000 0100
345 #define HOSTCR_MACEN 0x02 //0000 0010
346 #define HOSTCR_SOFTRST 0x01 //0000 0001
347
348 //
349 // Bits in the MACCR register
350 //
351 #define MACCR_SYNCFLUSHOK 0x04 //
352 #define MACCR_SYNCFLUSH 0x02 //
353 #define MACCR_CLRNAV 0x01 //
354
355 // Bits in the MAC_REG_GPIOCTL0 register
356 //
357 #define LED_ACTSET 0x01 //
358 #define LED_RFOFF 0x02 //
359 #define LED_NOCONNECT 0x04 //
360 //
361 // Bits in the RCR register
362 //
363 #define RCR_SSID 0x80
364 #define RCR_RXALLTYPE 0x40 //
365 #define RCR_UNICAST 0x20 //
366 #define RCR_BROADCAST 0x10 //
367 #define RCR_MULTICAST 0x08 //
368 #define RCR_WPAERR 0x04 //
369 #define RCR_ERRCRC 0x02 //
370 #define RCR_BSSID 0x01 //
371
372 //
373 // Bits in the TCR register
374 //
375 #define TCR_SYNCDCFOPT 0x02 //
376 #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
377
378 //
379 // Bits in the IMR register
380 //
381 #define IMR_MEASURESTART 0x80000000 //
382 #define IMR_QUIETSTART 0x20000000 //
383 #define IMR_RADARDETECT 0x10000000 //
384 #define IMR_MEASUREEND 0x08000000 //
385 #define IMR_SOFTTIMER1 0x00200000 //
386 #define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
387 #define IMR_RXNOBUF 0x00000800 //
388 #define IMR_MIBNEARFULL 0x00000400 //
389 #define IMR_SOFTINT 0x00000200 //
390 #define IMR_FETALERR 0x00000100 //
391 #define IMR_WATCHDOG 0x00000080 //
392 #define IMR_SOFTTIMER 0x00000040 //
393 #define IMR_GPIO 0x00000020 //
394 #define IMR_TBTT 0x00000010 //
395 #define IMR_RXDMA0 0x00000008 //
396 #define IMR_BNTX 0x00000004 //
397 #define IMR_AC0DMA 0x00000002 //
398 #define IMR_TXDMA0 0x00000001 //
399
400 //
401 // Bits in the ISR register
402 //
403
404 #define ISR_MEASURESTART 0x80000000 //
405 #define ISR_QUIETSTART 0x20000000 //
406 #define ISR_RADARDETECT 0x10000000 //
407 #define ISR_MEASUREEND 0x08000000 //
408 #define ISR_SOFTTIMER1 0x00200000 //
409 #define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
410 #define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
411 #define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
412 #define ISR_SOFTINT 0x00000200 //
413 #define ISR_FETALERR 0x00000100 //
414 #define ISR_WATCHDOG 0x00000080 //
415 #define ISR_SOFTTIMER 0x00000040 //
416 #define ISR_GPIO 0x00000020 //
417 #define ISR_TBTT 0x00000010 //
418 #define ISR_RXDMA0 0x00000008 //
419 #define ISR_BNTX 0x00000004 //
420 #define ISR_AC0DMA 0x00000002 //
421 #define ISR_TXDMA0 0x00000001 //
422
423 //
424 // Bits in the PSCFG register
425 //
426 #define PSCFG_PHILIPMD 0x40 //
427 #define PSCFG_WAKECALEN 0x20 //
428 #define PSCFG_WAKETMREN 0x10 //
429 #define PSCFG_BBPSPROG 0x08 //
430 #define PSCFG_WAKESYN 0x04 //
431 #define PSCFG_SLEEPSYN 0x02 //
432 #define PSCFG_AUTOSLEEP 0x01 //
433
434 //
435 // Bits in the PSCTL register
436 //
437 #define PSCTL_WAKEDONE 0x20 //
438 #define PSCTL_PS 0x10 //
439 #define PSCTL_GO2DOZE 0x08 //
440 #define PSCTL_LNBCN 0x04 //
441 #define PSCTL_ALBCN 0x02 //
442 #define PSCTL_PSEN 0x01 //
443
444 //
445 // Bits in the PSPWSIG register
446 //
447 #define PSSIG_WPE3 0x80 //
448 #define PSSIG_WPE2 0x40 //
449 #define PSSIG_WPE1 0x20 //
450 #define PSSIG_WRADIOPE 0x10 //
451 #define PSSIG_SPE3 0x08 //
452 #define PSSIG_SPE2 0x04 //
453 #define PSSIG_SPE1 0x02 //
454 #define PSSIG_SRADIOPE 0x01 //
455
456 //
457 // Bits in the BBREGCTL register
458 //
459 #define BBREGCTL_DONE 0x04 //
460 #define BBREGCTL_REGR 0x02 //
461 #define BBREGCTL_REGW 0x01 //
462
463 //
464 // Bits in the IFREGCTL register
465 //
466 #define IFREGCTL_DONE 0x04 //
467 #define IFREGCTL_IFRF 0x02 //
468 #define IFREGCTL_REGW 0x01 //
469
470 //
471 // Bits in the SOFTPWRCTL register
472 //
473 #define SOFTPWRCTL_RFLEOPT 0x0800 //
474 #define SOFTPWRCTL_TXPEINV 0x0200 //
475 #define SOFTPWRCTL_SWPECTI 0x0100 //
476 #define SOFTPWRCTL_SWPAPE 0x0020 //
477 #define SOFTPWRCTL_SWCALEN 0x0010 //
478 #define SOFTPWRCTL_SWRADIO_PE 0x0008 //
479 #define SOFTPWRCTL_SWPE2 0x0004 //
480 #define SOFTPWRCTL_SWPE1 0x0002 //
481 #define SOFTPWRCTL_SWPE3 0x0001 //
482
483 //
484 // Bits in the GPIOCTL1 register
485 //
486 #define GPIO1_DATA1 0x20 //
487 #define GPIO1_MD1 0x10 //
488 #define GPIO1_DATA0 0x02 //
489 #define GPIO1_MD0 0x01 //
490
491 //
492 // Bits in the DMACTL register
493 //
494 #define DMACTL_CLRRUN 0x00080000 //
495 #define DMACTL_RUN 0x00000008 //
496 #define DMACTL_WAKE 0x00000004 //
497 #define DMACTL_DEAD 0x00000002 //
498 #define DMACTL_ACTIVE 0x00000001 //
499 //
500 // Bits in the RXDMACTL0 register
501 //
502 #define RX_PERPKT 0x00000100 //
503 #define RX_PERPKTCLR 0x01000000 //
504 //
505 // Bits in the BCNDMACTL register
506 //
507 #define BEACON_READY 0x01 //
508 //
509 // Bits in the MISCFFCTL register
510 //
511 #define MISCFFCTL_WRITE 0x0001 //
512
513 //
514 // Bits in WAKEUPEN0
515 //
516 #define WAKEUPEN0_DIRPKT 0x10
517 #define WAKEUPEN0_LINKOFF 0x08
518 #define WAKEUPEN0_ATIMEN 0x04
519 #define WAKEUPEN0_TIMEN 0x02
520 #define WAKEUPEN0_MAGICEN 0x01
521
522 //
523 // Bits in WAKEUPEN1
524 //
525 #define WAKEUPEN1_128_3 0x08
526 #define WAKEUPEN1_128_2 0x04
527 #define WAKEUPEN1_128_1 0x02
528 #define WAKEUPEN1_128_0 0x01
529
530 //
531 // Bits in WAKEUPSR0
532 //
533 #define WAKEUPSR0_DIRPKT 0x10
534 #define WAKEUPSR0_LINKOFF 0x08
535 #define WAKEUPSR0_ATIMEN 0x04
536 #define WAKEUPSR0_TIMEN 0x02
537 #define WAKEUPSR0_MAGICEN 0x01
538
539 //
540 // Bits in WAKEUPSR1
541 //
542 #define WAKEUPSR1_128_3 0x08
543 #define WAKEUPSR1_128_2 0x04
544 #define WAKEUPSR1_128_1 0x02
545 #define WAKEUPSR1_128_0 0x01
546
547 //
548 // Bits in the MAC_REG_GPIOCTL register
549 //
550 #define GPIO0_MD 0x01 //
551 #define GPIO0_DATA 0x02 //
552 #define GPIO0_INTMD 0x04 //
553 #define GPIO1_MD 0x10 //
554 #define GPIO1_DATA 0x20 //
555
556 //
557 // Bits in the MSRCTL register
558 //
559 #define MSRCTL_FINISH 0x80
560 #define MSRCTL_READY 0x40
561 #define MSRCTL_RADARDETECT 0x20
562 #define MSRCTL_EN 0x10
563 #define MSRCTL_QUIETTXCHK 0x08
564 #define MSRCTL_QUIETRPT 0x04
565 #define MSRCTL_QUIETINT 0x02
566 #define MSRCTL_QUIETEN 0x01
567 //
568 // Bits in the MSRCTL1 register
569 //
570 #define MSRCTL1_TXPWR 0x08
571 #define MSRCTL1_CSAPAREN 0x04
572 #define MSRCTL1_TXPAUSE 0x01
573
574 // Loopback mode
575 #define MAC_LB_EXT 0x02 //
576 #define MAC_LB_INTERNAL 0x01 //
577 #define MAC_LB_NONE 0x00 //
578
579 // Ethernet address filter type
580 #define PKT_TYPE_NONE 0x00 // turn off receiver
581 #define PKT_TYPE_ALL_MULTICAST 0x80
582 #define PKT_TYPE_PROMISCUOUS 0x40
583 #define PKT_TYPE_DIRECTED 0x20 // obsolete, directed address is always accepted
584 #define PKT_TYPE_BROADCAST 0x10
585 #define PKT_TYPE_MULTICAST 0x08
586 #define PKT_TYPE_ERROR_WPA 0x04
587 #define PKT_TYPE_ERROR_CRC 0x02
588 #define PKT_TYPE_BSSID 0x01
589
590 #define Default_BI 0x200
591
592 // MiscFIFO Offset
593 #define MISCFIFO_KEYETRY0 32
594 #define MISCFIFO_KEYENTRYSIZE 22
595 #define MISCFIFO_SYNINFO_IDX 10
596 #define MISCFIFO_SYNDATA_IDX 11
597 #define MISCFIFO_SYNDATASIZE 21
598
599 // enabled mask value of irq
600 #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
601 IMR_RXDMA1 | \
602 IMR_RXNOBUF | \
603 IMR_MIBNEARFULL | \
604 IMR_SOFTINT | \
605 IMR_FETALERR | \
606 IMR_WATCHDOG | \
607 IMR_SOFTTIMER | \
608 IMR_GPIO | \
609 IMR_TBTT | \
610 IMR_RXDMA0 | \
611 IMR_BNTX | \
612 IMR_AC0DMA | \
613 IMR_TXDMA0)
614
615 // max time out delay time
616 #define W_MAX_TIMEOUT 0xFFF0U //
617
618 // wait time within loop
619 #define CB_DELAY_LOOP_WAIT 10 // 10ms
620
621 //
622 // revision id
623 //
624 #define REV_ID_VT3253_A0 0x00
625 #define REV_ID_VT3253_A1 0x01
626 #define REV_ID_VT3253_B0 0x08
627 #define REV_ID_VT3253_B1 0x09
628
629 /*--------------------- Export Types ------------------------------*/
630
631 /*--------------------- Export Macros ------------------------------*/
632
633 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
634 do { \
635 unsigned char byData; \
636 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
637 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
638 } while (0)
639
640 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
641 do { \
642 unsigned short wData; \
643 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
644 VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
645 } while (0)
646
647 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
648 do { \
649 unsigned long dwData; \
650 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
651 VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
652 } while (0)
653
654 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
655 do { \
656 unsigned char byData; \
657 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
658 byData &= byMask; \
659 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
660 } while (0)
661
662 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
663 do { \
664 unsigned char byData; \
665 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
666 VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
667 } while (0)
668
669 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
670 do { \
671 unsigned short wData; \
672 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
673 VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
674 } while (0)
675
676 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
677 do { \
678 unsigned long dwData; \
679 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
680 VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
681 } while (0)
682
683 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
684 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
685 (unsigned long *)pdwCurrDescAddr)
686
687 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
688 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
689 (unsigned long *)pdwCurrDescAddr)
690
691 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
692 VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
693 (unsigned long *)pdwCurrDescAddr)
694
695 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
696 VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
697 (unsigned long *)pdwCurrDescAddr)
698
699 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
700 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
701 (unsigned long *)pdwCurrDescAddr)
702
703 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
704 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
705 (unsigned long *)pdwCurrDescAddr)
706
707 // set the chip with current BCN tx descriptor address
708 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
709 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
710 dwCurrDescAddr)
711
712 // set the chip with current BCN length
713 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
714 VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
715 wCurrBCNLength)
716
717 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
718 do { \
719 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
720 VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
721 (unsigned char *)pbyEtherAddr); \
722 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
723 pbyEtherAddr + 1); \
724 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
725 pbyEtherAddr + 2); \
726 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
727 pbyEtherAddr + 3); \
728 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
729 pbyEtherAddr + 4); \
730 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
731 pbyEtherAddr + 5); \
732 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
733 } while (0)
734
735 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
736 do { \
737 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
738 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
739 *(pbyEtherAddr)); \
740 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
741 *(pbyEtherAddr + 1)); \
742 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
743 *(pbyEtherAddr + 2)); \
744 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
745 *(pbyEtherAddr + 3)); \
746 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
747 *(pbyEtherAddr + 4)); \
748 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
749 *(pbyEtherAddr + 5)); \
750 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
751 } while (0)
752
753 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
754 do { \
755 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
756 VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
757 (unsigned char *)pbyEtherAddr); \
758 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
759 pbyEtherAddr + 1); \
760 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
761 pbyEtherAddr + 2); \
762 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
763 pbyEtherAddr + 3); \
764 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
765 pbyEtherAddr + 4); \
766 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
767 pbyEtherAddr + 5); \
768 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
769 } while (0)
770
771 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
772 do { \
773 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
774 VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
775 *pbyEtherAddr); \
776 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
777 *(pbyEtherAddr + 1)); \
778 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
779 *(pbyEtherAddr + 2)); \
780 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
781 *(pbyEtherAddr + 3)); \
782 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
783 *(pbyEtherAddr + 4)); \
784 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
785 *(pbyEtherAddr + 5)); \
786 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
787 } while (0)
788
789 #define MACvClearISR(dwIoBase) \
790 VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE)
791
792 #define MACvStart(dwIoBase) \
793 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
794 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
795
796 #define MACvRx0PerPktMode(dwIoBase) \
797 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT)
798
799 #define MACvRx0BufferFillMode(dwIoBase) \
800 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
801
802 #define MACvRx1PerPktMode(dwIoBase) \
803 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT)
804
805 #define MACvRx1BufferFillMode(dwIoBase) \
806 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
807
808 #define MACvRxOn(dwIoBase) \
809 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON)
810
811 #define MACvReceive0(dwIoBase) \
812 do { \
813 unsigned long dwData; \
814 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
815 if (dwData & DMACTL_RUN) \
816 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
817 else \
818 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
819 } while (0)
820
821 #define MACvReceive1(dwIoBase) \
822 do { \
823 unsigned long dwData; \
824 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
825 if (dwData & DMACTL_RUN) \
826 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
827 else \
828 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
829 } while (0)
830
831 #define MACvTxOn(dwIoBase) \
832 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON)
833
834 #define MACvTransmit0(dwIoBase) \
835 do { \
836 unsigned long dwData; \
837 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
838 if (dwData & DMACTL_RUN) \
839 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
840 else \
841 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
842 } while (0)
843
844 #define MACvTransmitAC0(dwIoBase) \
845 do { \
846 unsigned long dwData; \
847 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
848 if (dwData & DMACTL_RUN) \
849 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
850 else \
851 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
852 } while (0)
853
854 #define MACvTransmitSYNC(dwIoBase) \
855 do { \
856 unsigned long dwData; \
857 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
858 if (dwData & DMACTL_RUN) \
859 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
860 else \
861 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
862 } while (0)
863
864 #define MACvTransmitATIM(dwIoBase) \
865 do { \
866 unsigned long dwData; \
867 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
868 if (dwData & DMACTL_RUN) \
869 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
870 else \
871 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
872 } while (0)
873
874 #define MACvTransmitBCN(dwIoBase) \
875 VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY)
876
877 #define MACvClearStckDS(dwIoBase) \
878 do { \
879 unsigned char byOrgValue; \
880 VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
881 byOrgValue = byOrgValue & 0xFC; \
882 VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
883 } while (0)
884
885 #define MACvReadISR(dwIoBase, pdwValue) \
886 VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue)
887
888 #define MACvWriteISR(dwIoBase, dwValue) \
889 VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue)
890
891 #define MACvIntEnable(dwIoBase, dwMask) \
892 VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask)
893
894 #define MACvIntDisable(dwIoBase) \
895 VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0)
896
897 #define MACvSelectPage0(dwIoBase) \
898 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0)
899
900 #define MACvSelectPage1(dwIoBase) \
901 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1)
902
903 #define MACvReadMIBCounter(dwIoBase, pdwCounter) \
904 VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter)
905
906 #define MACvPwrEvntDisable(dwIoBase) \
907 VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000)
908
909 #define MACvEnableProtectMD(dwIoBase) \
910 do { \
911 unsigned long dwOrgValue; \
912 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
913 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
914 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
915 } while (0)
916
917 #define MACvDisableProtectMD(dwIoBase) \
918 do { \
919 unsigned long dwOrgValue; \
920 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
921 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
922 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
923 } while (0)
924
925 #define MACvEnableBarkerPreambleMd(dwIoBase) \
926 do { \
927 unsigned long dwOrgValue; \
928 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
929 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
930 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
931 } while (0)
932
933 #define MACvDisableBarkerPreambleMd(dwIoBase) \
934 do { \
935 unsigned long dwOrgValue; \
936 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
937 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
938 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
939 } while (0)
940
941 #define MACvSetBBType(dwIoBase, byTyp) \
942 do { \
943 unsigned long dwOrgValue; \
944 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
945 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
946 dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
947 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
948 } while (0)
949
950 #define MACvReadATIMW(dwIoBase, pwCounter) \
951 VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter)
952
953 #define MACvWriteATIMW(dwIoBase, wCounter) \
954 VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter)
955
956 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
957 do { \
958 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
959 VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
960 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
961 } while (0)
962
963 #define MACvGPIOIn(dwIoBase, pbyValue) \
964 VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue)
965
966 #define MACvSetRFLE_LatchBase(dwIoBase) \
967 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
968
969 /*--------------------- Export Classes ----------------------------*/
970
971 /*--------------------- Export Variables --------------------------*/
972
973 /*--------------------- Export Functions --------------------------*/
974
975 extern unsigned short TxRate_iwconfig;//2008-5-8 <add> by chester
976 void MACvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyMacRegs);
977
978 bool MACbIsRegBitsOn(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
979 bool MACbIsRegBitsOff(unsigned long dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
980
981 bool MACbIsIntDisable(unsigned long dwIoBase);
982
983 unsigned char MACbyReadMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx);
984 void MACvWriteMultiAddr(unsigned long dwIoBase, unsigned int uByteIdx, unsigned char byData);
985 void MACvSetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx);
986 void MACvResetMultiAddrByHash(unsigned long dwIoBase, unsigned char byHashIdx);
987
988 void MACvSetRxThreshold(unsigned long dwIoBase, unsigned char byThreshold);
989 void MACvGetRxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
990
991 void MACvSetTxThreshold(unsigned long dwIoBase, unsigned char byThreshold);
992 void MACvGetTxThreshold(unsigned long dwIoBase, unsigned char *pbyThreshold);
993
994 void MACvSetDmaLength(unsigned long dwIoBase, unsigned char byDmaLength);
995 void MACvGetDmaLength(unsigned long dwIoBase, unsigned char *pbyDmaLength);
996
997 void MACvSetShortRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit);
998 void MACvGetShortRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
999
1000 void MACvSetLongRetryLimit(unsigned long dwIoBase, unsigned char byRetryLimit);
1001 void MACvGetLongRetryLimit(unsigned long dwIoBase, unsigned char *pbyRetryLimit);
1002
1003 void MACvSetLoopbackMode(unsigned long dwIoBase, unsigned char byLoopbackMode);
1004 bool MACbIsInLoopbackMode(unsigned long dwIoBase);
1005
1006 void MACvSetPacketFilter(unsigned long dwIoBase, unsigned short wFilterType);
1007
1008 void MACvSaveContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1009 void MACvRestoreContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1010 bool MACbCompareContext(unsigned long dwIoBase, unsigned char *pbyCxtBuf);
1011
1012 bool MACbSoftwareReset(unsigned long dwIoBase);
1013 bool MACbSafeSoftwareReset(unsigned long dwIoBase);
1014 bool MACbSafeRxOff(unsigned long dwIoBase);
1015 bool MACbSafeTxOff(unsigned long dwIoBase);
1016 bool MACbSafeStop(unsigned long dwIoBase);
1017 bool MACbShutdown(unsigned long dwIoBase);
1018 void MACvInitialize(unsigned long dwIoBase);
1019 void MACvSetCurrRx0DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1020 void MACvSetCurrRx1DescAddr(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1021 void MACvSetCurrTXDescAddr(int iTxType, unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1022 void MACvSetCurrTx0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1023 void MACvSetCurrAC0DescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1024 void MACvSetCurrSyncDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1025 void MACvSetCurrATIMDescAddrEx(unsigned long dwIoBase, unsigned long dwCurrDescAddr);
1026 void MACvTimer0MicroSDelay(unsigned long dwIoBase, unsigned int uDelay);
1027 void MACvOneShotTimer0MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
1028 void MACvOneShotTimer1MicroSec(unsigned long dwIoBase, unsigned int uDelayTime);
1029
1030 void MACvSetMISCFifo(unsigned long dwIoBase, unsigned short wOffset, unsigned long dwData);
1031
1032 bool MACbTxDMAOff(unsigned long dwIoBase, unsigned int idx);
1033
1034 void MACvClearBusSusInd(unsigned long dwIoBase);
1035 void MACvEnableBusSusEn(unsigned long dwIoBase);
1036
1037 bool MACbFlushSYNCFifo(unsigned long dwIoBase);
1038 bool MACbPSWakeup(unsigned long dwIoBase);
1039
1040 void MACvSetKeyEntry(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx,
1041 unsigned int uKeyIdx, unsigned char *pbyAddr, unsigned long *pdwKey, unsigned char byLocalID);
1042 void MACvDisableKeyEntry(unsigned long dwIoBase, unsigned int uEntryIdx);
1043 void MACvSetDefaultKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
1044 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1045 //void MACvEnableDefaultKey(unsigned long dwIoBase, unsigned char byLocalID);
1046 void MACvDisableDefaultKey(unsigned long dwIoBase);
1047 void MACvSetDefaultTKIPKeyEntry(unsigned long dwIoBase, unsigned int uKeyLen,
1048 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1049 void MACvSetDefaultKeyCtl(unsigned long dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned char byLocalID);
1050
1051 #endif // __MAC_H__
Linux with added FPC-III support