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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_dw.c
blob70ecf541b77a11f54a622a17ca2de9a2889b6c7a
1 /*
2 * Synopsys DesignWare 8250 driver.
3 *
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
15 */
16 #include <linux/device.h>
17 #include <linux/init.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/serial_8250.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_reg.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/acpi.h>
29 #include <linux/clk.h>
30 #include <linux/pm_runtime.h>
31
32 #include <asm/byteorder.h>
33
34 #include "8250.h"
35
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
40
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
56
57
58 struct dw8250_data {
59 int last_mcr;
60 int line;
61 struct clk *clk;
62 u8 usr_reg;
63 };
64
65 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
66 {
67 struct dw8250_data *d = p->private_data;
68
69 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
70 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
71 value |= UART_MSR_CTS;
72 value &= ~UART_MSR_DCTS;
73 }
74
75 return value;
76 }
77
78 static void dw8250_force_idle(struct uart_port *p)
79 {
80 serial8250_clear_and_reinit_fifos(container_of
81 (p, struct uart_8250_port, port));
82 (void)p->serial_in(p, UART_RX);
83 }
84
85 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
86 {
87 struct dw8250_data *d = p->private_data;
88
89 if (offset == UART_MCR)
90 d->last_mcr = value;
91
92 writeb(value, p->membase + (offset << p->regshift));
93
94 /* Make sure LCR write wasn't ignored */
95 if (offset == UART_LCR) {
96 int tries = 1000;
97 while (tries--) {
98 unsigned int lcr = p->serial_in(p, UART_LCR);
99 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
100 return;
101 dw8250_force_idle(p);
102 writeb(value, p->membase + (UART_LCR << p->regshift));
103 }
104 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
105 }
106 }
107
108 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
109 {
110 unsigned int value = readb(p->membase + (offset << p->regshift));
111
112 return dw8250_modify_msr(p, offset, value);
113 }
114
115 /* Read Back (rb) version to ensure register access ording. */
116 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
117 {
118 dw8250_serial_out(p, offset, value);
119 dw8250_serial_in(p, UART_LCR);
120 }
121
122 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
123 {
124 struct dw8250_data *d = p->private_data;
125
126 if (offset == UART_MCR)
127 d->last_mcr = value;
128
129 writel(value, p->membase + (offset << p->regshift));
130
131 /* Make sure LCR write wasn't ignored */
132 if (offset == UART_LCR) {
133 int tries = 1000;
134 while (tries--) {
135 unsigned int lcr = p->serial_in(p, UART_LCR);
136 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
137 return;
138 dw8250_force_idle(p);
139 writel(value, p->membase + (UART_LCR << p->regshift));
140 }
141 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
142 }
143 }
144
145 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
146 {
147 unsigned int value = readl(p->membase + (offset << p->regshift));
148
149 return dw8250_modify_msr(p, offset, value);
150 }
151
152 static int dw8250_handle_irq(struct uart_port *p)
153 {
154 struct dw8250_data *d = p->private_data;
155 unsigned int iir = p->serial_in(p, UART_IIR);
156
157 if (serial8250_handle_irq(p, iir)) {
158 return 1;
159 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
160 /* Clear the USR */
161 (void)p->serial_in(p, d->usr_reg);
162
163 return 1;
164 }
165
166 return 0;
167 }
168
169 static void
170 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
171 {
172 if (!state)
173 pm_runtime_get_sync(port->dev);
174
175 serial8250_do_pm(port, state, old);
176
177 if (state)
178 pm_runtime_put_sync_suspend(port->dev);
179 }
180
181 static void dw8250_setup_port(struct uart_8250_port *up)
182 {
183 struct uart_port *p = &up->port;
184 u32 reg = readl(p->membase + DW_UART_UCV);
185
186 /*
187 * If the Component Version Register returns zero, we know that
188 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
189 */
190 if (!reg)
191 return;
192
193 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
194 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
195
196 reg = readl(p->membase + DW_UART_CPR);
197 if (!reg)
198 return;
199
200 /* Select the type based on fifo */
201 if (reg & DW_UART_CPR_FIFO_MODE) {
202 p->type = PORT_16550A;
203 p->flags |= UPF_FIXED_TYPE;
204 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
205 up->tx_loadsz = p->fifosize;
206 up->capabilities = UART_CAP_FIFO;
207 }
208
209 if (reg & DW_UART_CPR_AFCE_MODE)
210 up->capabilities |= UART_CAP_AFE;
211 }
212
213 static int dw8250_probe_of(struct uart_port *p,
214 struct dw8250_data *data)
215 {
216 struct device_node *np = p->dev->of_node;
217 u32 val;
218 bool has_ucv = true;
219
220 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
221 #ifdef __BIG_ENDIAN
222 /*
223 * Low order bits of these 64-bit registers, when
224 * accessed as a byte, are 7 bytes further down in the
225 * address space in big endian mode.
226 */
227 p->membase += 7;
228 #endif
229 p->serial_out = dw8250_serial_out_rb;
230 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
231 p->type = PORT_OCTEON;
232 data->usr_reg = 0x27;
233 has_ucv = false;
234 } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
235 switch (val) {
236 case 1:
237 break;
238 case 4:
239 p->iotype = UPIO_MEM32;
240 p->serial_in = dw8250_serial_in32;
241 p->serial_out = dw8250_serial_out32;
242 break;
243 default:
244 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
245 return -EINVAL;
246 }
247 }
248 if (has_ucv)
249 dw8250_setup_port(container_of(p, struct uart_8250_port, port));
250
251 if (!of_property_read_u32(np, "reg-shift", &val))
252 p->regshift = val;
253
254 /* clock got configured through clk api, all done */
255 if (p->uartclk)
256 return 0;
257
258 /* try to find out clock frequency from DT as fallback */
259 if (of_property_read_u32(np, "clock-frequency", &val)) {
260 dev_err(p->dev, "clk or clock-frequency not defined\n");
261 return -EINVAL;
262 }
263 p->uartclk = val;
264
265 return 0;
266 }
267
268 #ifdef CONFIG_ACPI
269 static int dw8250_probe_acpi(struct uart_8250_port *up)
270 {
271 const struct acpi_device_id *id;
272 struct uart_port *p = &up->port;
273
274 dw8250_setup_port(up);
275
276 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
277 if (!id)
278 return -ENODEV;
279
280 p->iotype = UPIO_MEM32;
281 p->serial_in = dw8250_serial_in32;
282 p->serial_out = dw8250_serial_out32;
283 p->regshift = 2;
284
285 if (!p->uartclk)
286 p->uartclk = (unsigned int)id->driver_data;
287
288 up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
289 if (!up->dma)
290 return -ENOMEM;
291
292 up->dma->rxconf.src_maxburst = p->fifosize / 4;
293 up->dma->txconf.dst_maxburst = p->fifosize / 4;
294
295 return 0;
296 }
297 #else
298 static inline int dw8250_probe_acpi(struct uart_8250_port *up)
299 {
300 return -ENODEV;
301 }
302 #endif /* CONFIG_ACPI */
303
304 static int dw8250_probe(struct platform_device *pdev)
305 {
306 struct uart_8250_port uart = {};
307 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
308 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
309 struct dw8250_data *data;
310 int err;
311
312 if (!regs || !irq) {
313 dev_err(&pdev->dev, "no registers/irq defined\n");
314 return -EINVAL;
315 }
316
317 spin_lock_init(&uart.port.lock);
318 uart.port.mapbase = regs->start;
319 uart.port.irq = irq->start;
320 uart.port.handle_irq = dw8250_handle_irq;
321 uart.port.pm = dw8250_do_pm;
322 uart.port.type = PORT_8250;
323 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
324 uart.port.dev = &pdev->dev;
325
326 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
327 resource_size(regs));
328 if (!uart.port.membase)
329 return -ENOMEM;
330
331 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
332 if (!data)
333 return -ENOMEM;
334
335 data->usr_reg = DW_UART_USR;
336 data->clk = devm_clk_get(&pdev->dev, NULL);
337 if (!IS_ERR(data->clk)) {
338 clk_prepare_enable(data->clk);
339 uart.port.uartclk = clk_get_rate(data->clk);
340 }
341
342 uart.port.iotype = UPIO_MEM;
343 uart.port.serial_in = dw8250_serial_in;
344 uart.port.serial_out = dw8250_serial_out;
345 uart.port.private_data = data;
346
347 if (pdev->dev.of_node) {
348 err = dw8250_probe_of(&uart.port, data);
349 if (err)
350 return err;
351 } else if (ACPI_HANDLE(&pdev->dev)) {
352 err = dw8250_probe_acpi(&uart);
353 if (err)
354 return err;
355 } else {
356 return -ENODEV;
357 }
358
359 data->line = serial8250_register_8250_port(&uart);
360 if (data->line < 0)
361 return data->line;
362
363 platform_set_drvdata(pdev, data);
364
365 pm_runtime_set_active(&pdev->dev);
366 pm_runtime_enable(&pdev->dev);
367
368 return 0;
369 }
370
371 static int dw8250_remove(struct platform_device *pdev)
372 {
373 struct dw8250_data *data = platform_get_drvdata(pdev);
374
375 pm_runtime_get_sync(&pdev->dev);
376
377 serial8250_unregister_port(data->line);
378
379 if (!IS_ERR(data->clk))
380 clk_disable_unprepare(data->clk);
381
382 pm_runtime_disable(&pdev->dev);
383 pm_runtime_put_noidle(&pdev->dev);
384
385 return 0;
386 }
387
388 #ifdef CONFIG_PM
389 static int dw8250_suspend(struct device *dev)
390 {
391 struct dw8250_data *data = dev_get_drvdata(dev);
392
393 serial8250_suspend_port(data->line);
394
395 return 0;
396 }
397
398 static int dw8250_resume(struct device *dev)
399 {
400 struct dw8250_data *data = dev_get_drvdata(dev);
401
402 serial8250_resume_port(data->line);
403
404 return 0;
405 }
406 #endif /* CONFIG_PM */
407
408 #ifdef CONFIG_PM_RUNTIME
409 static int dw8250_runtime_suspend(struct device *dev)
410 {
411 struct dw8250_data *data = dev_get_drvdata(dev);
412
413 if (!IS_ERR(data->clk))
414 clk_disable_unprepare(data->clk);
415
416 return 0;
417 }
418
419 static int dw8250_runtime_resume(struct device *dev)
420 {
421 struct dw8250_data *data = dev_get_drvdata(dev);
422
423 if (!IS_ERR(data->clk))
424 clk_prepare_enable(data->clk);
425
426 return 0;
427 }
428 #endif
429
430 static const struct dev_pm_ops dw8250_pm_ops = {
431 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
432 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
433 };
434
435 static const struct of_device_id dw8250_of_match[] = {
436 { .compatible = "snps,dw-apb-uart" },
437 { .compatible = "cavium,octeon-3860-uart" },
438 { /* Sentinel */ }
439 };
440 MODULE_DEVICE_TABLE(of, dw8250_of_match);
441
442 static const struct acpi_device_id dw8250_acpi_match[] = {
443 { "INT33C4", 0 },
444 { "INT33C5", 0 },
445 { "INT3434", 0 },
446 { "INT3435", 0 },
447 { "80860F0A", 0 },
448 { },
449 };
450 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
451
452 static struct platform_driver dw8250_platform_driver = {
453 .driver = {
454 .name = "dw-apb-uart",
455 .owner = THIS_MODULE,
456 .pm = &dw8250_pm_ops,
457 .of_match_table = dw8250_of_match,
458 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
459 },
460 .probe = dw8250_probe,
461 .remove = dw8250_remove,
462 };
463
464 module_platform_driver(dw8250_platform_driver);
465
466 MODULE_AUTHOR("Jamie Iles");
467 MODULE_LICENSE("GPL");
468 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
Linux with added FPC-III support