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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_pci.c
blobf5df8b7067aded09f57bc643d6ecf4db1b5dcf42
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 #undef SERIAL_DEBUG_PCI
31
32 /*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38 struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_8250_port *, int);
63
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74 }
75
76 static int
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift)
79 {
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 base = pci_resource_start(dev, bar);
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
101 } else {
102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
107 }
108 return 0;
109 }
110
111 /*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_8250_port *port, int idx)
117 {
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136
137 /*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_8250_port *port, int idx)
144 {
145 unsigned int bar, offset = board->first_offset;
146
147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
155 return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157
158 /*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_8250_port *port, int idx)
199 {
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
220 return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222
223 /*
224 * Added for EKF Intel i960 serial boards
225 */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240 }
241
242 /*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 irq_config = 0x43;
262
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
274 /*
275 * enable/disable interrupts
276 */
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289 }
290
291 static void pci_plx9050_exit(struct pci_dev *dev)
292 {
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311 }
312
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315
316 static void pci_ni8420_exit(struct pci_dev *dev)
317 {
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348 static void pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368 }
369
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_8250_port *port, int idx)
374 {
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
388 return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400
401 static int sbs_init(struct pci_dev *dev)
402 {
403 u8 __iomem *p;
404
405 p = pci_ioremap_bar(dev, 0);
406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
411 udelay(50);
412 writeb(0x0, p + OCT_REG_CR_OFF);
413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419 }
420
421 /*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425 static void sbs_exit(struct pci_dev *dev)
426 {
427 u8 __iomem *p;
428
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
432 writeb(0, p + OCT_REG_CR_OFF);
433 iounmap(p);
434 }
435
436 /*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
448 *
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491 }
492
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511 }
512
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524 }
525
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_8250_port *port, int idx)
529 {
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538 }
539
540 /*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555 };
556
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562 };
563
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568
569 static const struct timedia_struct {
570 int num;
571 const unsigned short *ids;
572 } timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
577 };
578
579 /*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599 }
600
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603 const unsigned short *ids;
604 int i, j;
605
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613 }
614
615 /*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_8250_port *port, int idx)
623 {
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
639 /* FALLTHROUGH */
640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 /*
651 * Some Titan cards are also a little weird
652 */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_8250_port *port, int idx)
657 {
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
672 return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677 msleep(100);
678 return 0;
679 }
680
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704 }
705
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748 }
749
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_8250_port *port, int idx)
758 {
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_8250_port *port, int idx)
785 {
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
866 if (num_serial == 0)
867 return -ENODEV;
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038 {
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 /* Quatech devices have their own extra interface features */
1044
1045 struct quatech_feature {
1046 u16 devid;
1047 bool amcc;
1048 };
1049
1050 #define QPCR_TEST_FOR1 0x3F
1051 #define QPCR_TEST_GET1 0x00
1052 #define QPCR_TEST_FOR2 0x40
1053 #define QPCR_TEST_GET2 0x40
1054 #define QPCR_TEST_FOR3 0x80
1055 #define QPCR_TEST_GET3 0x40
1056 #define QPCR_TEST_FOR4 0xC0
1057 #define QPCR_TEST_GET4 0x80
1058
1059 #define QOPR_CLOCK_X1 0x0000
1060 #define QOPR_CLOCK_X2 0x0001
1061 #define QOPR_CLOCK_X4 0x0002
1062 #define QOPR_CLOCK_X8 0x0003
1063 #define QOPR_CLOCK_RATE_MASK 0x0003
1064
1065
1066 static struct quatech_feature quatech_cards[] = {
1067 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086 { 0, }
1087 };
1088
1089 static int pci_quatech_amcc(u16 devid)
1090 {
1091 struct quatech_feature *qf = &quatech_cards[0];
1092 while (qf->devid) {
1093 if (qf->devid == devid)
1094 return qf->amcc;
1095 qf++;
1096 }
1097 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098 return 0;
1099 };
1100
1101 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 {
1103 unsigned long base = port->port.iobase;
1104 u8 LCR, val;
1105
1106 LCR = inb(base + UART_LCR);
1107 outb(0xBF, base + UART_LCR);
1108 val = inb(base + UART_SCR);
1109 outb(LCR, base + UART_LCR);
1110 return val;
1111 }
1112
1113 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(qopr, base + UART_SCR);
1122 outb(LCR, base + UART_LCR);
1123 }
1124
1125 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR, val, qmcr;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 val = inb(base + UART_SCR);
1133 outb(val | 0x10, base + UART_SCR);
1134 qmcr = inb(base + UART_MCR);
1135 outb(val, base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137
1138 return qmcr;
1139 }
1140
1141 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 {
1143 unsigned long base = port->port.iobase;
1144 u8 LCR, val;
1145
1146 LCR = inb(base + UART_LCR);
1147 outb(0xBF, base + UART_LCR);
1148 val = inb(base + UART_SCR);
1149 outb(val | 0x10, base + UART_SCR);
1150 outb(qmcr, base + UART_MCR);
1151 outb(val, base + UART_SCR);
1152 outb(LCR, base + UART_LCR);
1153 }
1154
1155 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 {
1157 unsigned long base = port->port.iobase;
1158 u8 LCR, val;
1159
1160 LCR = inb(base + UART_LCR);
1161 outb(0xBF, base + UART_LCR);
1162 val = inb(base + UART_SCR);
1163 if (val & 0x20) {
1164 outb(0x80, UART_LCR);
1165 if (!(inb(UART_SCR) & 0x20)) {
1166 outb(LCR, base + UART_LCR);
1167 return 1;
1168 }
1169 }
1170 return 0;
1171 }
1172
1173 static int pci_quatech_test(struct uart_8250_port *port)
1174 {
1175 u8 reg;
1176 u8 qopr = pci_quatech_rqopr(port);
1177 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178 reg = pci_quatech_rqopr(port) & 0xC0;
1179 if (reg != QPCR_TEST_GET1)
1180 return -EINVAL;
1181 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182 reg = pci_quatech_rqopr(port) & 0xC0;
1183 if (reg != QPCR_TEST_GET2)
1184 return -EINVAL;
1185 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186 reg = pci_quatech_rqopr(port) & 0xC0;
1187 if (reg != QPCR_TEST_GET3)
1188 return -EINVAL;
1189 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190 reg = pci_quatech_rqopr(port) & 0xC0;
1191 if (reg != QPCR_TEST_GET4)
1192 return -EINVAL;
1193
1194 pci_quatech_wqopr(port, qopr);
1195 return 0;
1196 }
1197
1198 static int pci_quatech_clock(struct uart_8250_port *port)
1199 {
1200 u8 qopr, reg, set;
1201 unsigned long clock;
1202
1203 if (pci_quatech_test(port) < 0)
1204 return 1843200;
1205
1206 qopr = pci_quatech_rqopr(port);
1207
1208 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209 reg = pci_quatech_rqopr(port);
1210 if (reg & QOPR_CLOCK_X8) {
1211 clock = 1843200;
1212 goto out;
1213 }
1214 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215 reg = pci_quatech_rqopr(port);
1216 if (!(reg & QOPR_CLOCK_X8)) {
1217 clock = 1843200;
1218 goto out;
1219 }
1220 reg &= QOPR_CLOCK_X8;
1221 if (reg == QOPR_CLOCK_X2) {
1222 clock = 3685400;
1223 set = QOPR_CLOCK_X2;
1224 } else if (reg == QOPR_CLOCK_X4) {
1225 clock = 7372800;
1226 set = QOPR_CLOCK_X4;
1227 } else if (reg == QOPR_CLOCK_X8) {
1228 clock = 14745600;
1229 set = QOPR_CLOCK_X8;
1230 } else {
1231 clock = 1843200;
1232 set = QOPR_CLOCK_X1;
1233 }
1234 qopr &= ~QOPR_CLOCK_RATE_MASK;
1235 qopr |= set;
1236
1237 out:
1238 pci_quatech_wqopr(port, qopr);
1239 return clock;
1240 }
1241
1242 static int pci_quatech_rs422(struct uart_8250_port *port)
1243 {
1244 u8 qmcr;
1245 int rs422 = 0;
1246
1247 if (!pci_quatech_has_qmcr(port))
1248 return 0;
1249 qmcr = pci_quatech_rqmcr(port);
1250 pci_quatech_wqmcr(port, 0xFF);
1251 if (pci_quatech_rqmcr(port))
1252 rs422 = 1;
1253 pci_quatech_wqmcr(port, qmcr);
1254 return rs422;
1255 }
1256
1257 static int pci_quatech_init(struct pci_dev *dev)
1258 {
1259 if (pci_quatech_amcc(dev->device)) {
1260 unsigned long base = pci_resource_start(dev, 0);
1261 if (base) {
1262 u32 tmp;
1263 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1264 tmp = inl(base + 0x3c);
1265 outl(tmp | 0x01000000, base + 0x3c);
1266 outl(tmp &= ~0x01000000, base + 0x3c);
1267 }
1268 }
1269 return 0;
1270 }
1271
1272 static int pci_quatech_setup(struct serial_private *priv,
1273 const struct pciserial_board *board,
1274 struct uart_8250_port *port, int idx)
1275 {
1276 /* Needed by pci_quatech calls below */
1277 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278 /* Set up the clocking */
1279 port->port.uartclk = pci_quatech_clock(port);
1280 /* For now just warn about RS422 */
1281 if (pci_quatech_rs422(port))
1282 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283 return pci_default_setup(priv, board, port, idx);
1284 }
1285
1286 static void pci_quatech_exit(struct pci_dev *dev)
1287 {
1288 }
1289
1290 static int pci_default_setup(struct serial_private *priv,
1291 const struct pciserial_board *board,
1292 struct uart_8250_port *port, int idx)
1293 {
1294 unsigned int bar, offset = board->first_offset, maxnr;
1295
1296 bar = FL_GET_BASE(board->flags);
1297 if (board->flags & FL_BASE_BARS)
1298 bar += idx;
1299 else
1300 offset += idx * board->uart_offset;
1301
1302 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303 (board->reg_shift + 3);
1304
1305 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306 return 1;
1307
1308 return setup_port(priv, port, bar, offset, board->reg_shift);
1309 }
1310
1311 static int
1312 ce4100_serial_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1315 {
1316 int ret;
1317
1318 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1319 port->port.iotype = UPIO_MEM32;
1320 port->port.type = PORT_XSCALE;
1321 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322 port->port.regshift = 2;
1323
1324 return ret;
1325 }
1326
1327 static int
1328 pci_omegapci_setup(struct serial_private *priv,
1329 const struct pciserial_board *board,
1330 struct uart_8250_port *port, int idx)
1331 {
1332 return setup_port(priv, port, 2, idx * 8, 0);
1333 }
1334
1335 static int
1336 pci_brcm_trumanage_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339 {
1340 int ret = pci_default_setup(priv, board, port, idx);
1341
1342 port->port.type = PORT_BRCM_TRUMANAGE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 return ret;
1345 }
1346
1347 static int skip_tx_en_setup(struct serial_private *priv,
1348 const struct pciserial_board *board,
1349 struct uart_8250_port *port, int idx)
1350 {
1351 port->port.flags |= UPF_NO_TXEN_TEST;
1352 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353 "[%04x:%04x] subsystem [%04x:%04x]\n",
1354 priv->dev->vendor,
1355 priv->dev->device,
1356 priv->dev->subsystem_vendor,
1357 priv->dev->subsystem_device);
1358
1359 return pci_default_setup(priv, board, port, idx);
1360 }
1361
1362 static void kt_handle_break(struct uart_port *p)
1363 {
1364 struct uart_8250_port *up =
1365 container_of(p, struct uart_8250_port, port);
1366 /*
1367 * On receipt of a BI, serial device in Intel ME (Intel
1368 * management engine) needs to have its fifos cleared for sane
1369 * SOL (Serial Over Lan) output.
1370 */
1371 serial8250_clear_and_reinit_fifos(up);
1372 }
1373
1374 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375 {
1376 struct uart_8250_port *up =
1377 container_of(p, struct uart_8250_port, port);
1378 unsigned int val;
1379
1380 /*
1381 * When the Intel ME (management engine) gets reset its serial
1382 * port registers could return 0 momentarily. Functions like
1383 * serial8250_console_write, read and save the IER, perform
1384 * some operation and then restore it. In order to avoid
1385 * setting IER register inadvertently to 0, if the value read
1386 * is 0, double check with ier value in uart_8250_port and use
1387 * that instead. up->ier should be the same value as what is
1388 * currently configured.
1389 */
1390 val = inb(p->iobase + offset);
1391 if (offset == UART_IER) {
1392 if (val == 0)
1393 val = up->ier;
1394 }
1395 return val;
1396 }
1397
1398 static int kt_serial_setup(struct serial_private *priv,
1399 const struct pciserial_board *board,
1400 struct uart_8250_port *port, int idx)
1401 {
1402 port->port.flags |= UPF_BUG_THRE;
1403 port->port.serial_in = kt_serial_in;
1404 port->port.handle_break = kt_handle_break;
1405 return skip_tx_en_setup(priv, board, port, idx);
1406 }
1407
1408 static int pci_eg20t_init(struct pci_dev *dev)
1409 {
1410 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411 return -ENODEV;
1412 #else
1413 return 0;
1414 #endif
1415 }
1416
1417 static int
1418 pci_xr17c154_setup(struct serial_private *priv,
1419 const struct pciserial_board *board,
1420 struct uart_8250_port *port, int idx)
1421 {
1422 port->port.flags |= UPF_EXAR_EFR;
1423 return pci_default_setup(priv, board, port, idx);
1424 }
1425
1426 static int
1427 pci_xr17v35x_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430 {
1431 u8 __iomem *p;
1432
1433 p = pci_ioremap_bar(priv->dev, 0);
1434 if (p == NULL)
1435 return -ENOMEM;
1436
1437 port->port.flags |= UPF_EXAR_EFR;
1438
1439 /*
1440 * Setup Multipurpose Input/Output pins.
1441 */
1442 if (idx == 0) {
1443 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455 }
1456 writeb(0x00, p + UART_EXAR_8XMODE);
1457 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458 writeb(128, p + UART_EXAR_TXTRG);
1459 writeb(128, p + UART_EXAR_RXTRG);
1460 iounmap(p);
1461
1462 return pci_default_setup(priv, board, port, idx);
1463 }
1464
1465 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470 static int
1471 pci_fastcom335_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474 {
1475 u8 __iomem *p;
1476
1477 p = pci_ioremap_bar(priv->dev, 0);
1478 if (p == NULL)
1479 return -ENOMEM;
1480
1481 port->port.flags |= UPF_EXAR_EFR;
1482
1483 /*
1484 * Setup Multipurpose Input/Output pins.
1485 */
1486 if (idx == 0) {
1487 switch (priv->dev->device) {
1488 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493 break;
1494 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499 break;
1500 }
1501 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504 }
1505 writeb(0x00, p + UART_EXAR_8XMODE);
1506 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507 writeb(32, p + UART_EXAR_TXTRG);
1508 writeb(32, p + UART_EXAR_RXTRG);
1509 iounmap(p);
1510
1511 return pci_default_setup(priv, board, port, idx);
1512 }
1513
1514 static int
1515 pci_wch_ch353_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518 {
1519 port->port.flags |= UPF_FIXED_TYPE;
1520 port->port.type = PORT_16550A;
1521 return pci_default_setup(priv, board, port, idx);
1522 }
1523
1524 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1525 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1526 #define PCI_DEVICE_ID_OCTPRO 0x0001
1527 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1528 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1529 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1530 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1531 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1532 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1533 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1534 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1535 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1536 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1537 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1538 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1539 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1540 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1541 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1542 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1543 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1544 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1545 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1546 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1547 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1548 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1549 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1550 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1551 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1552 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1553 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1554 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1555 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1556 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1557 #define PCI_VENDOR_ID_WCH 0x4348
1558 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1559 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1560 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1561 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1562 #define PCI_VENDOR_ID_AGESTAR 0x5372
1563 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1564 #define PCI_VENDOR_ID_ASIX 0x9710
1565 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1566 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1567 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1568 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1569 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1570
1571 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1572 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1573
1574
1575 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1576 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1577 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1578
1579 /*
1580 * Master list of serial port init/setup/exit quirks.
1581 * This does not describe the general nature of the port.
1582 * (ie, baud base, number and location of ports, etc)
1583 *
1584 * This list is ordered alphabetically by vendor then device.
1585 * Specific entries must come before more generic entries.
1586 */
1587 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1588 /*
1589 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1590 */
1591 {
1592 .vendor = PCI_VENDOR_ID_AMCC,
1593 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1594 .subvendor = PCI_ANY_ID,
1595 .subdevice = PCI_ANY_ID,
1596 .setup = addidata_apci7800_setup,
1597 },
1598 /*
1599 * AFAVLAB cards - these may be called via parport_serial
1600 * It is not clear whether this applies to all products.
1601 */
1602 {
1603 .vendor = PCI_VENDOR_ID_AFAVLAB,
1604 .device = PCI_ANY_ID,
1605 .subvendor = PCI_ANY_ID,
1606 .subdevice = PCI_ANY_ID,
1607 .setup = afavlab_setup,
1608 },
1609 /*
1610 * HP Diva
1611 */
1612 {
1613 .vendor = PCI_VENDOR_ID_HP,
1614 .device = PCI_DEVICE_ID_HP_DIVA,
1615 .subvendor = PCI_ANY_ID,
1616 .subdevice = PCI_ANY_ID,
1617 .init = pci_hp_diva_init,
1618 .setup = pci_hp_diva_setup,
1619 },
1620 /*
1621 * Intel
1622 */
1623 {
1624 .vendor = PCI_VENDOR_ID_INTEL,
1625 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1626 .subvendor = 0xe4bf,
1627 .subdevice = PCI_ANY_ID,
1628 .init = pci_inteli960ni_init,
1629 .setup = pci_default_setup,
1630 },
1631 {
1632 .vendor = PCI_VENDOR_ID_INTEL,
1633 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1634 .subvendor = PCI_ANY_ID,
1635 .subdevice = PCI_ANY_ID,
1636 .setup = skip_tx_en_setup,
1637 },
1638 {
1639 .vendor = PCI_VENDOR_ID_INTEL,
1640 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1641 .subvendor = PCI_ANY_ID,
1642 .subdevice = PCI_ANY_ID,
1643 .setup = skip_tx_en_setup,
1644 },
1645 {
1646 .vendor = PCI_VENDOR_ID_INTEL,
1647 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1648 .subvendor = PCI_ANY_ID,
1649 .subdevice = PCI_ANY_ID,
1650 .setup = skip_tx_en_setup,
1651 },
1652 {
1653 .vendor = PCI_VENDOR_ID_INTEL,
1654 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1655 .subvendor = PCI_ANY_ID,
1656 .subdevice = PCI_ANY_ID,
1657 .setup = ce4100_serial_setup,
1658 },
1659 {
1660 .vendor = PCI_VENDOR_ID_INTEL,
1661 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1662 .subvendor = PCI_ANY_ID,
1663 .subdevice = PCI_ANY_ID,
1664 .setup = kt_serial_setup,
1665 },
1666 /*
1667 * ITE
1668 */
1669 {
1670 .vendor = PCI_VENDOR_ID_ITE,
1671 .device = PCI_DEVICE_ID_ITE_8872,
1672 .subvendor = PCI_ANY_ID,
1673 .subdevice = PCI_ANY_ID,
1674 .init = pci_ite887x_init,
1675 .setup = pci_default_setup,
1676 .exit = pci_ite887x_exit,
1677 },
1678 /*
1679 * National Instruments
1680 */
1681 {
1682 .vendor = PCI_VENDOR_ID_NI,
1683 .device = PCI_DEVICE_ID_NI_PCI23216,
1684 .subvendor = PCI_ANY_ID,
1685 .subdevice = PCI_ANY_ID,
1686 .init = pci_ni8420_init,
1687 .setup = pci_default_setup,
1688 .exit = pci_ni8420_exit,
1689 },
1690 {
1691 .vendor = PCI_VENDOR_ID_NI,
1692 .device = PCI_DEVICE_ID_NI_PCI2328,
1693 .subvendor = PCI_ANY_ID,
1694 .subdevice = PCI_ANY_ID,
1695 .init = pci_ni8420_init,
1696 .setup = pci_default_setup,
1697 .exit = pci_ni8420_exit,
1698 },
1699 {
1700 .vendor = PCI_VENDOR_ID_NI,
1701 .device = PCI_DEVICE_ID_NI_PCI2324,
1702 .subvendor = PCI_ANY_ID,
1703 .subdevice = PCI_ANY_ID,
1704 .init = pci_ni8420_init,
1705 .setup = pci_default_setup,
1706 .exit = pci_ni8420_exit,
1707 },
1708 {
1709 .vendor = PCI_VENDOR_ID_NI,
1710 .device = PCI_DEVICE_ID_NI_PCI2322,
1711 .subvendor = PCI_ANY_ID,
1712 .subdevice = PCI_ANY_ID,
1713 .init = pci_ni8420_init,
1714 .setup = pci_default_setup,
1715 .exit = pci_ni8420_exit,
1716 },
1717 {
1718 .vendor = PCI_VENDOR_ID_NI,
1719 .device = PCI_DEVICE_ID_NI_PCI2324I,
1720 .subvendor = PCI_ANY_ID,
1721 .subdevice = PCI_ANY_ID,
1722 .init = pci_ni8420_init,
1723 .setup = pci_default_setup,
1724 .exit = pci_ni8420_exit,
1725 },
1726 {
1727 .vendor = PCI_VENDOR_ID_NI,
1728 .device = PCI_DEVICE_ID_NI_PCI2322I,
1729 .subvendor = PCI_ANY_ID,
1730 .subdevice = PCI_ANY_ID,
1731 .init = pci_ni8420_init,
1732 .setup = pci_default_setup,
1733 .exit = pci_ni8420_exit,
1734 },
1735 {
1736 .vendor = PCI_VENDOR_ID_NI,
1737 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1738 .subvendor = PCI_ANY_ID,
1739 .subdevice = PCI_ANY_ID,
1740 .init = pci_ni8420_init,
1741 .setup = pci_default_setup,
1742 .exit = pci_ni8420_exit,
1743 },
1744 {
1745 .vendor = PCI_VENDOR_ID_NI,
1746 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1747 .subvendor = PCI_ANY_ID,
1748 .subdevice = PCI_ANY_ID,
1749 .init = pci_ni8420_init,
1750 .setup = pci_default_setup,
1751 .exit = pci_ni8420_exit,
1752 },
1753 {
1754 .vendor = PCI_VENDOR_ID_NI,
1755 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1756 .subvendor = PCI_ANY_ID,
1757 .subdevice = PCI_ANY_ID,
1758 .init = pci_ni8420_init,
1759 .setup = pci_default_setup,
1760 .exit = pci_ni8420_exit,
1761 },
1762 {
1763 .vendor = PCI_VENDOR_ID_NI,
1764 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1765 .subvendor = PCI_ANY_ID,
1766 .subdevice = PCI_ANY_ID,
1767 .init = pci_ni8420_init,
1768 .setup = pci_default_setup,
1769 .exit = pci_ni8420_exit,
1770 },
1771 {
1772 .vendor = PCI_VENDOR_ID_NI,
1773 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1774 .subvendor = PCI_ANY_ID,
1775 .subdevice = PCI_ANY_ID,
1776 .init = pci_ni8420_init,
1777 .setup = pci_default_setup,
1778 .exit = pci_ni8420_exit,
1779 },
1780 {
1781 .vendor = PCI_VENDOR_ID_NI,
1782 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1783 .subvendor = PCI_ANY_ID,
1784 .subdevice = PCI_ANY_ID,
1785 .init = pci_ni8420_init,
1786 .setup = pci_default_setup,
1787 .exit = pci_ni8420_exit,
1788 },
1789 {
1790 .vendor = PCI_VENDOR_ID_NI,
1791 .device = PCI_ANY_ID,
1792 .subvendor = PCI_ANY_ID,
1793 .subdevice = PCI_ANY_ID,
1794 .init = pci_ni8430_init,
1795 .setup = pci_ni8430_setup,
1796 .exit = pci_ni8430_exit,
1797 },
1798 /* Quatech */
1799 {
1800 .vendor = PCI_VENDOR_ID_QUATECH,
1801 .device = PCI_ANY_ID,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 .init = pci_quatech_init,
1805 .setup = pci_quatech_setup,
1806 .exit = pci_quatech_exit,
1807 },
1808 /*
1809 * Panacom
1810 */
1811 {
1812 .vendor = PCI_VENDOR_ID_PANACOM,
1813 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1814 .subvendor = PCI_ANY_ID,
1815 .subdevice = PCI_ANY_ID,
1816 .init = pci_plx9050_init,
1817 .setup = pci_default_setup,
1818 .exit = pci_plx9050_exit,
1819 },
1820 {
1821 .vendor = PCI_VENDOR_ID_PANACOM,
1822 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .init = pci_plx9050_init,
1826 .setup = pci_default_setup,
1827 .exit = pci_plx9050_exit,
1828 },
1829 /*
1830 * PLX
1831 */
1832 {
1833 .vendor = PCI_VENDOR_ID_PLX,
1834 .device = PCI_DEVICE_ID_PLX_9030,
1835 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1836 .subdevice = PCI_ANY_ID,
1837 .setup = pci_default_setup,
1838 },
1839 {
1840 .vendor = PCI_VENDOR_ID_PLX,
1841 .device = PCI_DEVICE_ID_PLX_9050,
1842 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1843 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1844 .init = pci_plx9050_init,
1845 .setup = pci_default_setup,
1846 .exit = pci_plx9050_exit,
1847 },
1848 {
1849 .vendor = PCI_VENDOR_ID_PLX,
1850 .device = PCI_DEVICE_ID_PLX_9050,
1851 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1852 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1853 .init = pci_plx9050_init,
1854 .setup = pci_default_setup,
1855 .exit = pci_plx9050_exit,
1856 },
1857 {
1858 .vendor = PCI_VENDOR_ID_PLX,
1859 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1860 .subvendor = PCI_VENDOR_ID_PLX,
1861 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1862 .init = pci_plx9050_init,
1863 .setup = pci_default_setup,
1864 .exit = pci_plx9050_exit,
1865 },
1866 /*
1867 * SBS Technologies, Inc., PMC-OCTALPRO 232
1868 */
1869 {
1870 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1871 .device = PCI_DEVICE_ID_OCTPRO,
1872 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1873 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1874 .init = sbs_init,
1875 .setup = sbs_setup,
1876 .exit = sbs_exit,
1877 },
1878 /*
1879 * SBS Technologies, Inc., PMC-OCTALPRO 422
1880 */
1881 {
1882 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1883 .device = PCI_DEVICE_ID_OCTPRO,
1884 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1885 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1886 .init = sbs_init,
1887 .setup = sbs_setup,
1888 .exit = sbs_exit,
1889 },
1890 /*
1891 * SBS Technologies, Inc., P-Octal 232
1892 */
1893 {
1894 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1895 .device = PCI_DEVICE_ID_OCTPRO,
1896 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1897 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1898 .init = sbs_init,
1899 .setup = sbs_setup,
1900 .exit = sbs_exit,
1901 },
1902 /*
1903 * SBS Technologies, Inc., P-Octal 422
1904 */
1905 {
1906 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1907 .device = PCI_DEVICE_ID_OCTPRO,
1908 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1909 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1910 .init = sbs_init,
1911 .setup = sbs_setup,
1912 .exit = sbs_exit,
1913 },
1914 /*
1915 * SIIG cards - these may be called via parport_serial
1916 */
1917 {
1918 .vendor = PCI_VENDOR_ID_SIIG,
1919 .device = PCI_ANY_ID,
1920 .subvendor = PCI_ANY_ID,
1921 .subdevice = PCI_ANY_ID,
1922 .init = pci_siig_init,
1923 .setup = pci_siig_setup,
1924 },
1925 /*
1926 * Titan cards
1927 */
1928 {
1929 .vendor = PCI_VENDOR_ID_TITAN,
1930 .device = PCI_DEVICE_ID_TITAN_400L,
1931 .subvendor = PCI_ANY_ID,
1932 .subdevice = PCI_ANY_ID,
1933 .setup = titan_400l_800l_setup,
1934 },
1935 {
1936 .vendor = PCI_VENDOR_ID_TITAN,
1937 .device = PCI_DEVICE_ID_TITAN_800L,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .setup = titan_400l_800l_setup,
1941 },
1942 /*
1943 * Timedia cards
1944 */
1945 {
1946 .vendor = PCI_VENDOR_ID_TIMEDIA,
1947 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1948 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1949 .subdevice = PCI_ANY_ID,
1950 .probe = pci_timedia_probe,
1951 .init = pci_timedia_init,
1952 .setup = pci_timedia_setup,
1953 },
1954 {
1955 .vendor = PCI_VENDOR_ID_TIMEDIA,
1956 .device = PCI_ANY_ID,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .setup = pci_timedia_setup,
1960 },
1961 /*
1962 * SUNIX (Timedia) cards
1963 * Do not "probe" for these cards as there is at least one combination
1964 * card that should be handled by parport_pc that doesn't match the
1965 * rule in pci_timedia_probe.
1966 * It is part number is MIO5079A but its subdevice ID is 0x0102.
1967 * There are some boards with part number SER5037AL that report
1968 * subdevice ID 0x0002.
1969 */
1970 {
1971 .vendor = PCI_VENDOR_ID_SUNIX,
1972 .device = PCI_DEVICE_ID_SUNIX_1999,
1973 .subvendor = PCI_VENDOR_ID_SUNIX,
1974 .subdevice = PCI_ANY_ID,
1975 .init = pci_timedia_init,
1976 .setup = pci_timedia_setup,
1977 },
1978 /*
1979 * Exar cards
1980 */
1981 {
1982 .vendor = PCI_VENDOR_ID_EXAR,
1983 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .setup = pci_xr17c154_setup,
1987 },
1988 {
1989 .vendor = PCI_VENDOR_ID_EXAR,
1990 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1991 .subvendor = PCI_ANY_ID,
1992 .subdevice = PCI_ANY_ID,
1993 .setup = pci_xr17c154_setup,
1994 },
1995 {
1996 .vendor = PCI_VENDOR_ID_EXAR,
1997 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1998 .subvendor = PCI_ANY_ID,
1999 .subdevice = PCI_ANY_ID,
2000 .setup = pci_xr17c154_setup,
2001 },
2002 {
2003 .vendor = PCI_VENDOR_ID_EXAR,
2004 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2005 .subvendor = PCI_ANY_ID,
2006 .subdevice = PCI_ANY_ID,
2007 .setup = pci_xr17v35x_setup,
2008 },
2009 {
2010 .vendor = PCI_VENDOR_ID_EXAR,
2011 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .setup = pci_xr17v35x_setup,
2015 },
2016 {
2017 .vendor = PCI_VENDOR_ID_EXAR,
2018 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2019 .subvendor = PCI_ANY_ID,
2020 .subdevice = PCI_ANY_ID,
2021 .setup = pci_xr17v35x_setup,
2022 },
2023 /*
2024 * Xircom cards
2025 */
2026 {
2027 .vendor = PCI_VENDOR_ID_XIRCOM,
2028 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .init = pci_xircom_init,
2032 .setup = pci_default_setup,
2033 },
2034 /*
2035 * Netmos cards - these may be called via parport_serial
2036 */
2037 {
2038 .vendor = PCI_VENDOR_ID_NETMOS,
2039 .device = PCI_ANY_ID,
2040 .subvendor = PCI_ANY_ID,
2041 .subdevice = PCI_ANY_ID,
2042 .init = pci_netmos_init,
2043 .setup = pci_netmos_9900_setup,
2044 },
2045 /*
2046 * For Oxford Semiconductor Tornado based devices
2047 */
2048 {
2049 .vendor = PCI_VENDOR_ID_OXSEMI,
2050 .device = PCI_ANY_ID,
2051 .subvendor = PCI_ANY_ID,
2052 .subdevice = PCI_ANY_ID,
2053 .init = pci_oxsemi_tornado_init,
2054 .setup = pci_default_setup,
2055 },
2056 {
2057 .vendor = PCI_VENDOR_ID_MAINPINE,
2058 .device = PCI_ANY_ID,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .init = pci_oxsemi_tornado_init,
2062 .setup = pci_default_setup,
2063 },
2064 {
2065 .vendor = PCI_VENDOR_ID_DIGI,
2066 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2067 .subvendor = PCI_SUBVENDOR_ID_IBM,
2068 .subdevice = PCI_ANY_ID,
2069 .init = pci_oxsemi_tornado_init,
2070 .setup = pci_default_setup,
2071 },
2072 {
2073 .vendor = PCI_VENDOR_ID_INTEL,
2074 .device = 0x8811,
2075 .subvendor = PCI_ANY_ID,
2076 .subdevice = PCI_ANY_ID,
2077 .init = pci_eg20t_init,
2078 .setup = pci_default_setup,
2079 },
2080 {
2081 .vendor = PCI_VENDOR_ID_INTEL,
2082 .device = 0x8812,
2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
2085 .init = pci_eg20t_init,
2086 .setup = pci_default_setup,
2087 },
2088 {
2089 .vendor = PCI_VENDOR_ID_INTEL,
2090 .device = 0x8813,
2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
2093 .init = pci_eg20t_init,
2094 .setup = pci_default_setup,
2095 },
2096 {
2097 .vendor = PCI_VENDOR_ID_INTEL,
2098 .device = 0x8814,
2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
2101 .init = pci_eg20t_init,
2102 .setup = pci_default_setup,
2103 },
2104 {
2105 .vendor = 0x10DB,
2106 .device = 0x8027,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .init = pci_eg20t_init,
2110 .setup = pci_default_setup,
2111 },
2112 {
2113 .vendor = 0x10DB,
2114 .device = 0x8028,
2115 .subvendor = PCI_ANY_ID,
2116 .subdevice = PCI_ANY_ID,
2117 .init = pci_eg20t_init,
2118 .setup = pci_default_setup,
2119 },
2120 {
2121 .vendor = 0x10DB,
2122 .device = 0x8029,
2123 .subvendor = PCI_ANY_ID,
2124 .subdevice = PCI_ANY_ID,
2125 .init = pci_eg20t_init,
2126 .setup = pci_default_setup,
2127 },
2128 {
2129 .vendor = 0x10DB,
2130 .device = 0x800C,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_eg20t_init,
2134 .setup = pci_default_setup,
2135 },
2136 {
2137 .vendor = 0x10DB,
2138 .device = 0x800D,
2139 .subvendor = PCI_ANY_ID,
2140 .subdevice = PCI_ANY_ID,
2141 .init = pci_eg20t_init,
2142 .setup = pci_default_setup,
2143 },
2144 /*
2145 * Cronyx Omega PCI (PLX-chip based)
2146 */
2147 {
2148 .vendor = PCI_VENDOR_ID_PLX,
2149 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = pci_omegapci_setup,
2153 },
2154 /* WCH CH353 2S1P card (16550 clone) */
2155 {
2156 .vendor = PCI_VENDOR_ID_WCH,
2157 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .setup = pci_wch_ch353_setup,
2161 },
2162 /* WCH CH353 4S card (16550 clone) */
2163 {
2164 .vendor = PCI_VENDOR_ID_WCH,
2165 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2166 .subvendor = PCI_ANY_ID,
2167 .subdevice = PCI_ANY_ID,
2168 .setup = pci_wch_ch353_setup,
2169 },
2170 /* WCH CH353 2S1PF card (16550 clone) */
2171 {
2172 .vendor = PCI_VENDOR_ID_WCH,
2173 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2174 .subvendor = PCI_ANY_ID,
2175 .subdevice = PCI_ANY_ID,
2176 .setup = pci_wch_ch353_setup,
2177 },
2178 /* WCH CH352 2S card (16550 clone) */
2179 {
2180 .vendor = PCI_VENDOR_ID_WCH,
2181 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = pci_wch_ch353_setup,
2185 },
2186 /*
2187 * ASIX devices with FIFO bug
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_ASIX,
2191 .device = PCI_ANY_ID,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .setup = pci_asix_setup,
2195 },
2196 /*
2197 * Commtech, Inc. Fastcom adapters
2198 *
2199 */
2200 {
2201 .vendor = PCI_VENDOR_ID_COMMTECH,
2202 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .setup = pci_fastcom335_setup,
2206 },
2207 {
2208 .vendor = PCI_VENDOR_ID_COMMTECH,
2209 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .setup = pci_fastcom335_setup,
2213 },
2214 {
2215 .vendor = PCI_VENDOR_ID_COMMTECH,
2216 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .setup = pci_fastcom335_setup,
2220 },
2221 {
2222 .vendor = PCI_VENDOR_ID_COMMTECH,
2223 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2224 .subvendor = PCI_ANY_ID,
2225 .subdevice = PCI_ANY_ID,
2226 .setup = pci_fastcom335_setup,
2227 },
2228 {
2229 .vendor = PCI_VENDOR_ID_COMMTECH,
2230 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2231 .subvendor = PCI_ANY_ID,
2232 .subdevice = PCI_ANY_ID,
2233 .setup = pci_xr17v35x_setup,
2234 },
2235 {
2236 .vendor = PCI_VENDOR_ID_COMMTECH,
2237 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2238 .subvendor = PCI_ANY_ID,
2239 .subdevice = PCI_ANY_ID,
2240 .setup = pci_xr17v35x_setup,
2241 },
2242 {
2243 .vendor = PCI_VENDOR_ID_COMMTECH,
2244 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .setup = pci_xr17v35x_setup,
2248 },
2249 /*
2250 * Broadcom TruManage (NetXtreme)
2251 */
2252 {
2253 .vendor = PCI_VENDOR_ID_BROADCOM,
2254 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .setup = pci_brcm_trumanage_setup,
2258 },
2259
2260 /*
2261 * Default "match everything" terminator entry
2262 */
2263 {
2264 .vendor = PCI_ANY_ID,
2265 .device = PCI_ANY_ID,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .setup = pci_default_setup,
2269 }
2270 };
2271
2272 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2273 {
2274 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2275 }
2276
2277 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2278 {
2279 struct pci_serial_quirk *quirk;
2280
2281 for (quirk = pci_serial_quirks; ; quirk++)
2282 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2283 quirk_id_matches(quirk->device, dev->device) &&
2284 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2285 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2286 break;
2287 return quirk;
2288 }
2289
2290 static inline int get_pci_irq(struct pci_dev *dev,
2291 const struct pciserial_board *board)
2292 {
2293 if (board->flags & FL_NOIRQ)
2294 return 0;
2295 else
2296 return dev->irq;
2297 }
2298
2299 /*
2300 * This is the configuration table for all of the PCI serial boards
2301 * which we support. It is directly indexed by the pci_board_num_t enum
2302 * value, which is encoded in the pci_device_id PCI probe table's
2303 * driver_data member.
2304 *
2305 * The makeup of these names are:
2306 * pbn_bn{_bt}_n_baud{_offsetinhex}
2307 *
2308 * bn = PCI BAR number
2309 * bt = Index using PCI BARs
2310 * n = number of serial ports
2311 * baud = baud rate
2312 * offsetinhex = offset for each sequential port (in hex)
2313 *
2314 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2315 *
2316 * Please note: in theory if n = 1, _bt infix should make no difference.
2317 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2318 */
2319 enum pci_board_num_t {
2320 pbn_default = 0,
2321
2322 pbn_b0_1_115200,
2323 pbn_b0_2_115200,
2324 pbn_b0_4_115200,
2325 pbn_b0_5_115200,
2326 pbn_b0_8_115200,
2327
2328 pbn_b0_1_921600,
2329 pbn_b0_2_921600,
2330 pbn_b0_4_921600,
2331
2332 pbn_b0_2_1130000,
2333
2334 pbn_b0_4_1152000,
2335
2336 pbn_b0_2_1152000_200,
2337 pbn_b0_4_1152000_200,
2338 pbn_b0_8_1152000_200,
2339
2340 pbn_b0_2_1843200,
2341 pbn_b0_4_1843200,
2342
2343 pbn_b0_2_1843200_200,
2344 pbn_b0_4_1843200_200,
2345 pbn_b0_8_1843200_200,
2346
2347 pbn_b0_1_4000000,
2348
2349 pbn_b0_bt_1_115200,
2350 pbn_b0_bt_2_115200,
2351 pbn_b0_bt_4_115200,
2352 pbn_b0_bt_8_115200,
2353
2354 pbn_b0_bt_1_460800,
2355 pbn_b0_bt_2_460800,
2356 pbn_b0_bt_4_460800,
2357
2358 pbn_b0_bt_1_921600,
2359 pbn_b0_bt_2_921600,
2360 pbn_b0_bt_4_921600,
2361 pbn_b0_bt_8_921600,
2362
2363 pbn_b1_1_115200,
2364 pbn_b1_2_115200,
2365 pbn_b1_4_115200,
2366 pbn_b1_8_115200,
2367 pbn_b1_16_115200,
2368
2369 pbn_b1_1_921600,
2370 pbn_b1_2_921600,
2371 pbn_b1_4_921600,
2372 pbn_b1_8_921600,
2373
2374 pbn_b1_2_1250000,
2375
2376 pbn_b1_bt_1_115200,
2377 pbn_b1_bt_2_115200,
2378 pbn_b1_bt_4_115200,
2379
2380 pbn_b1_bt_2_921600,
2381
2382 pbn_b1_1_1382400,
2383 pbn_b1_2_1382400,
2384 pbn_b1_4_1382400,
2385 pbn_b1_8_1382400,
2386
2387 pbn_b2_1_115200,
2388 pbn_b2_2_115200,
2389 pbn_b2_4_115200,
2390 pbn_b2_8_115200,
2391
2392 pbn_b2_1_460800,
2393 pbn_b2_4_460800,
2394 pbn_b2_8_460800,
2395 pbn_b2_16_460800,
2396
2397 pbn_b2_1_921600,
2398 pbn_b2_4_921600,
2399 pbn_b2_8_921600,
2400
2401 pbn_b2_8_1152000,
2402
2403 pbn_b2_bt_1_115200,
2404 pbn_b2_bt_2_115200,
2405 pbn_b2_bt_4_115200,
2406
2407 pbn_b2_bt_2_921600,
2408 pbn_b2_bt_4_921600,
2409
2410 pbn_b3_2_115200,
2411 pbn_b3_4_115200,
2412 pbn_b3_8_115200,
2413
2414 pbn_b4_bt_2_921600,
2415 pbn_b4_bt_4_921600,
2416 pbn_b4_bt_8_921600,
2417
2418 /*
2419 * Board-specific versions.
2420 */
2421 pbn_panacom,
2422 pbn_panacom2,
2423 pbn_panacom4,
2424 pbn_plx_romulus,
2425 pbn_oxsemi,
2426 pbn_oxsemi_1_4000000,
2427 pbn_oxsemi_2_4000000,
2428 pbn_oxsemi_4_4000000,
2429 pbn_oxsemi_8_4000000,
2430 pbn_intel_i960,
2431 pbn_sgi_ioc3,
2432 pbn_computone_4,
2433 pbn_computone_6,
2434 pbn_computone_8,
2435 pbn_sbsxrsio,
2436 pbn_exar_XR17C152,
2437 pbn_exar_XR17C154,
2438 pbn_exar_XR17C158,
2439 pbn_exar_XR17V352,
2440 pbn_exar_XR17V354,
2441 pbn_exar_XR17V358,
2442 pbn_exar_ibm_saturn,
2443 pbn_pasemi_1682M,
2444 pbn_ni8430_2,
2445 pbn_ni8430_4,
2446 pbn_ni8430_8,
2447 pbn_ni8430_16,
2448 pbn_ADDIDATA_PCIe_1_3906250,
2449 pbn_ADDIDATA_PCIe_2_3906250,
2450 pbn_ADDIDATA_PCIe_4_3906250,
2451 pbn_ADDIDATA_PCIe_8_3906250,
2452 pbn_ce4100_1_115200,
2453 pbn_omegapci,
2454 pbn_NETMOS9900_2s_115200,
2455 pbn_brcm_trumanage,
2456 };
2457
2458 /*
2459 * uart_offset - the space between channels
2460 * reg_shift - describes how the UART registers are mapped
2461 * to PCI memory by the card.
2462 * For example IER register on SBS, Inc. PMC-OctPro is located at
2463 * offset 0x10 from the UART base, while UART_IER is defined as 1
2464 * in include/linux/serial_reg.h,
2465 * see first lines of serial_in() and serial_out() in 8250.c
2466 */
2467
2468 static struct pciserial_board pci_boards[] = {
2469 [pbn_default] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 1,
2472 .base_baud = 115200,
2473 .uart_offset = 8,
2474 },
2475 [pbn_b0_1_115200] = {
2476 .flags = FL_BASE0,
2477 .num_ports = 1,
2478 .base_baud = 115200,
2479 .uart_offset = 8,
2480 },
2481 [pbn_b0_2_115200] = {
2482 .flags = FL_BASE0,
2483 .num_ports = 2,
2484 .base_baud = 115200,
2485 .uart_offset = 8,
2486 },
2487 [pbn_b0_4_115200] = {
2488 .flags = FL_BASE0,
2489 .num_ports = 4,
2490 .base_baud = 115200,
2491 .uart_offset = 8,
2492 },
2493 [pbn_b0_5_115200] = {
2494 .flags = FL_BASE0,
2495 .num_ports = 5,
2496 .base_baud = 115200,
2497 .uart_offset = 8,
2498 },
2499 [pbn_b0_8_115200] = {
2500 .flags = FL_BASE0,
2501 .num_ports = 8,
2502 .base_baud = 115200,
2503 .uart_offset = 8,
2504 },
2505 [pbn_b0_1_921600] = {
2506 .flags = FL_BASE0,
2507 .num_ports = 1,
2508 .base_baud = 921600,
2509 .uart_offset = 8,
2510 },
2511 [pbn_b0_2_921600] = {
2512 .flags = FL_BASE0,
2513 .num_ports = 2,
2514 .base_baud = 921600,
2515 .uart_offset = 8,
2516 },
2517 [pbn_b0_4_921600] = {
2518 .flags = FL_BASE0,
2519 .num_ports = 4,
2520 .base_baud = 921600,
2521 .uart_offset = 8,
2522 },
2523
2524 [pbn_b0_2_1130000] = {
2525 .flags = FL_BASE0,
2526 .num_ports = 2,
2527 .base_baud = 1130000,
2528 .uart_offset = 8,
2529 },
2530
2531 [pbn_b0_4_1152000] = {
2532 .flags = FL_BASE0,
2533 .num_ports = 4,
2534 .base_baud = 1152000,
2535 .uart_offset = 8,
2536 },
2537
2538 [pbn_b0_2_1152000_200] = {
2539 .flags = FL_BASE0,
2540 .num_ports = 2,
2541 .base_baud = 1152000,
2542 .uart_offset = 0x200,
2543 },
2544
2545 [pbn_b0_4_1152000_200] = {
2546 .flags = FL_BASE0,
2547 .num_ports = 4,
2548 .base_baud = 1152000,
2549 .uart_offset = 0x200,
2550 },
2551
2552 [pbn_b0_8_1152000_200] = {
2553 .flags = FL_BASE0,
2554 .num_ports = 8,
2555 .base_baud = 1152000,
2556 .uart_offset = 0x200,
2557 },
2558
2559 [pbn_b0_2_1843200] = {
2560 .flags = FL_BASE0,
2561 .num_ports = 2,
2562 .base_baud = 1843200,
2563 .uart_offset = 8,
2564 },
2565 [pbn_b0_4_1843200] = {
2566 .flags = FL_BASE0,
2567 .num_ports = 4,
2568 .base_baud = 1843200,
2569 .uart_offset = 8,
2570 },
2571
2572 [pbn_b0_2_1843200_200] = {
2573 .flags = FL_BASE0,
2574 .num_ports = 2,
2575 .base_baud = 1843200,
2576 .uart_offset = 0x200,
2577 },
2578 [pbn_b0_4_1843200_200] = {
2579 .flags = FL_BASE0,
2580 .num_ports = 4,
2581 .base_baud = 1843200,
2582 .uart_offset = 0x200,
2583 },
2584 [pbn_b0_8_1843200_200] = {
2585 .flags = FL_BASE0,
2586 .num_ports = 8,
2587 .base_baud = 1843200,
2588 .uart_offset = 0x200,
2589 },
2590 [pbn_b0_1_4000000] = {
2591 .flags = FL_BASE0,
2592 .num_ports = 1,
2593 .base_baud = 4000000,
2594 .uart_offset = 8,
2595 },
2596
2597 [pbn_b0_bt_1_115200] = {
2598 .flags = FL_BASE0|FL_BASE_BARS,
2599 .num_ports = 1,
2600 .base_baud = 115200,
2601 .uart_offset = 8,
2602 },
2603 [pbn_b0_bt_2_115200] = {
2604 .flags = FL_BASE0|FL_BASE_BARS,
2605 .num_ports = 2,
2606 .base_baud = 115200,
2607 .uart_offset = 8,
2608 },
2609 [pbn_b0_bt_4_115200] = {
2610 .flags = FL_BASE0|FL_BASE_BARS,
2611 .num_ports = 4,
2612 .base_baud = 115200,
2613 .uart_offset = 8,
2614 },
2615 [pbn_b0_bt_8_115200] = {
2616 .flags = FL_BASE0|FL_BASE_BARS,
2617 .num_ports = 8,
2618 .base_baud = 115200,
2619 .uart_offset = 8,
2620 },
2621
2622 [pbn_b0_bt_1_460800] = {
2623 .flags = FL_BASE0|FL_BASE_BARS,
2624 .num_ports = 1,
2625 .base_baud = 460800,
2626 .uart_offset = 8,
2627 },
2628 [pbn_b0_bt_2_460800] = {
2629 .flags = FL_BASE0|FL_BASE_BARS,
2630 .num_ports = 2,
2631 .base_baud = 460800,
2632 .uart_offset = 8,
2633 },
2634 [pbn_b0_bt_4_460800] = {
2635 .flags = FL_BASE0|FL_BASE_BARS,
2636 .num_ports = 4,
2637 .base_baud = 460800,
2638 .uart_offset = 8,
2639 },
2640
2641 [pbn_b0_bt_1_921600] = {
2642 .flags = FL_BASE0|FL_BASE_BARS,
2643 .num_ports = 1,
2644 .base_baud = 921600,
2645 .uart_offset = 8,
2646 },
2647 [pbn_b0_bt_2_921600] = {
2648 .flags = FL_BASE0|FL_BASE_BARS,
2649 .num_ports = 2,
2650 .base_baud = 921600,
2651 .uart_offset = 8,
2652 },
2653 [pbn_b0_bt_4_921600] = {
2654 .flags = FL_BASE0|FL_BASE_BARS,
2655 .num_ports = 4,
2656 .base_baud = 921600,
2657 .uart_offset = 8,
2658 },
2659 [pbn_b0_bt_8_921600] = {
2660 .flags = FL_BASE0|FL_BASE_BARS,
2661 .num_ports = 8,
2662 .base_baud = 921600,
2663 .uart_offset = 8,
2664 },
2665
2666 [pbn_b1_1_115200] = {
2667 .flags = FL_BASE1,
2668 .num_ports = 1,
2669 .base_baud = 115200,
2670 .uart_offset = 8,
2671 },
2672 [pbn_b1_2_115200] = {
2673 .flags = FL_BASE1,
2674 .num_ports = 2,
2675 .base_baud = 115200,
2676 .uart_offset = 8,
2677 },
2678 [pbn_b1_4_115200] = {
2679 .flags = FL_BASE1,
2680 .num_ports = 4,
2681 .base_baud = 115200,
2682 .uart_offset = 8,
2683 },
2684 [pbn_b1_8_115200] = {
2685 .flags = FL_BASE1,
2686 .num_ports = 8,
2687 .base_baud = 115200,
2688 .uart_offset = 8,
2689 },
2690 [pbn_b1_16_115200] = {
2691 .flags = FL_BASE1,
2692 .num_ports = 16,
2693 .base_baud = 115200,
2694 .uart_offset = 8,
2695 },
2696
2697 [pbn_b1_1_921600] = {
2698 .flags = FL_BASE1,
2699 .num_ports = 1,
2700 .base_baud = 921600,
2701 .uart_offset = 8,
2702 },
2703 [pbn_b1_2_921600] = {
2704 .flags = FL_BASE1,
2705 .num_ports = 2,
2706 .base_baud = 921600,
2707 .uart_offset = 8,
2708 },
2709 [pbn_b1_4_921600] = {
2710 .flags = FL_BASE1,
2711 .num_ports = 4,
2712 .base_baud = 921600,
2713 .uart_offset = 8,
2714 },
2715 [pbn_b1_8_921600] = {
2716 .flags = FL_BASE1,
2717 .num_ports = 8,
2718 .base_baud = 921600,
2719 .uart_offset = 8,
2720 },
2721 [pbn_b1_2_1250000] = {
2722 .flags = FL_BASE1,
2723 .num_ports = 2,
2724 .base_baud = 1250000,
2725 .uart_offset = 8,
2726 },
2727
2728 [pbn_b1_bt_1_115200] = {
2729 .flags = FL_BASE1|FL_BASE_BARS,
2730 .num_ports = 1,
2731 .base_baud = 115200,
2732 .uart_offset = 8,
2733 },
2734 [pbn_b1_bt_2_115200] = {
2735 .flags = FL_BASE1|FL_BASE_BARS,
2736 .num_ports = 2,
2737 .base_baud = 115200,
2738 .uart_offset = 8,
2739 },
2740 [pbn_b1_bt_4_115200] = {
2741 .flags = FL_BASE1|FL_BASE_BARS,
2742 .num_ports = 4,
2743 .base_baud = 115200,
2744 .uart_offset = 8,
2745 },
2746
2747 [pbn_b1_bt_2_921600] = {
2748 .flags = FL_BASE1|FL_BASE_BARS,
2749 .num_ports = 2,
2750 .base_baud = 921600,
2751 .uart_offset = 8,
2752 },
2753
2754 [pbn_b1_1_1382400] = {
2755 .flags = FL_BASE1,
2756 .num_ports = 1,
2757 .base_baud = 1382400,
2758 .uart_offset = 8,
2759 },
2760 [pbn_b1_2_1382400] = {
2761 .flags = FL_BASE1,
2762 .num_ports = 2,
2763 .base_baud = 1382400,
2764 .uart_offset = 8,
2765 },
2766 [pbn_b1_4_1382400] = {
2767 .flags = FL_BASE1,
2768 .num_ports = 4,
2769 .base_baud = 1382400,
2770 .uart_offset = 8,
2771 },
2772 [pbn_b1_8_1382400] = {
2773 .flags = FL_BASE1,
2774 .num_ports = 8,
2775 .base_baud = 1382400,
2776 .uart_offset = 8,
2777 },
2778
2779 [pbn_b2_1_115200] = {
2780 .flags = FL_BASE2,
2781 .num_ports = 1,
2782 .base_baud = 115200,
2783 .uart_offset = 8,
2784 },
2785 [pbn_b2_2_115200] = {
2786 .flags = FL_BASE2,
2787 .num_ports = 2,
2788 .base_baud = 115200,
2789 .uart_offset = 8,
2790 },
2791 [pbn_b2_4_115200] = {
2792 .flags = FL_BASE2,
2793 .num_ports = 4,
2794 .base_baud = 115200,
2795 .uart_offset = 8,
2796 },
2797 [pbn_b2_8_115200] = {
2798 .flags = FL_BASE2,
2799 .num_ports = 8,
2800 .base_baud = 115200,
2801 .uart_offset = 8,
2802 },
2803
2804 [pbn_b2_1_460800] = {
2805 .flags = FL_BASE2,
2806 .num_ports = 1,
2807 .base_baud = 460800,
2808 .uart_offset = 8,
2809 },
2810 [pbn_b2_4_460800] = {
2811 .flags = FL_BASE2,
2812 .num_ports = 4,
2813 .base_baud = 460800,
2814 .uart_offset = 8,
2815 },
2816 [pbn_b2_8_460800] = {
2817 .flags = FL_BASE2,
2818 .num_ports = 8,
2819 .base_baud = 460800,
2820 .uart_offset = 8,
2821 },
2822 [pbn_b2_16_460800] = {
2823 .flags = FL_BASE2,
2824 .num_ports = 16,
2825 .base_baud = 460800,
2826 .uart_offset = 8,
2827 },
2828
2829 [pbn_b2_1_921600] = {
2830 .flags = FL_BASE2,
2831 .num_ports = 1,
2832 .base_baud = 921600,
2833 .uart_offset = 8,
2834 },
2835 [pbn_b2_4_921600] = {
2836 .flags = FL_BASE2,
2837 .num_ports = 4,
2838 .base_baud = 921600,
2839 .uart_offset = 8,
2840 },
2841 [pbn_b2_8_921600] = {
2842 .flags = FL_BASE2,
2843 .num_ports = 8,
2844 .base_baud = 921600,
2845 .uart_offset = 8,
2846 },
2847
2848 [pbn_b2_8_1152000] = {
2849 .flags = FL_BASE2,
2850 .num_ports = 8,
2851 .base_baud = 1152000,
2852 .uart_offset = 8,
2853 },
2854
2855 [pbn_b2_bt_1_115200] = {
2856 .flags = FL_BASE2|FL_BASE_BARS,
2857 .num_ports = 1,
2858 .base_baud = 115200,
2859 .uart_offset = 8,
2860 },
2861 [pbn_b2_bt_2_115200] = {
2862 .flags = FL_BASE2|FL_BASE_BARS,
2863 .num_ports = 2,
2864 .base_baud = 115200,
2865 .uart_offset = 8,
2866 },
2867 [pbn_b2_bt_4_115200] = {
2868 .flags = FL_BASE2|FL_BASE_BARS,
2869 .num_ports = 4,
2870 .base_baud = 115200,
2871 .uart_offset = 8,
2872 },
2873
2874 [pbn_b2_bt_2_921600] = {
2875 .flags = FL_BASE2|FL_BASE_BARS,
2876 .num_ports = 2,
2877 .base_baud = 921600,
2878 .uart_offset = 8,
2879 },
2880 [pbn_b2_bt_4_921600] = {
2881 .flags = FL_BASE2|FL_BASE_BARS,
2882 .num_ports = 4,
2883 .base_baud = 921600,
2884 .uart_offset = 8,
2885 },
2886
2887 [pbn_b3_2_115200] = {
2888 .flags = FL_BASE3,
2889 .num_ports = 2,
2890 .base_baud = 115200,
2891 .uart_offset = 8,
2892 },
2893 [pbn_b3_4_115200] = {
2894 .flags = FL_BASE3,
2895 .num_ports = 4,
2896 .base_baud = 115200,
2897 .uart_offset = 8,
2898 },
2899 [pbn_b3_8_115200] = {
2900 .flags = FL_BASE3,
2901 .num_ports = 8,
2902 .base_baud = 115200,
2903 .uart_offset = 8,
2904 },
2905
2906 [pbn_b4_bt_2_921600] = {
2907 .flags = FL_BASE4,
2908 .num_ports = 2,
2909 .base_baud = 921600,
2910 .uart_offset = 8,
2911 },
2912 [pbn_b4_bt_4_921600] = {
2913 .flags = FL_BASE4,
2914 .num_ports = 4,
2915 .base_baud = 921600,
2916 .uart_offset = 8,
2917 },
2918 [pbn_b4_bt_8_921600] = {
2919 .flags = FL_BASE4,
2920 .num_ports = 8,
2921 .base_baud = 921600,
2922 .uart_offset = 8,
2923 },
2924
2925 /*
2926 * Entries following this are board-specific.
2927 */
2928
2929 /*
2930 * Panacom - IOMEM
2931 */
2932 [pbn_panacom] = {
2933 .flags = FL_BASE2,
2934 .num_ports = 2,
2935 .base_baud = 921600,
2936 .uart_offset = 0x400,
2937 .reg_shift = 7,
2938 },
2939 [pbn_panacom2] = {
2940 .flags = FL_BASE2|FL_BASE_BARS,
2941 .num_ports = 2,
2942 .base_baud = 921600,
2943 .uart_offset = 0x400,
2944 .reg_shift = 7,
2945 },
2946 [pbn_panacom4] = {
2947 .flags = FL_BASE2|FL_BASE_BARS,
2948 .num_ports = 4,
2949 .base_baud = 921600,
2950 .uart_offset = 0x400,
2951 .reg_shift = 7,
2952 },
2953
2954 /* I think this entry is broken - the first_offset looks wrong --rmk */
2955 [pbn_plx_romulus] = {
2956 .flags = FL_BASE2,
2957 .num_ports = 4,
2958 .base_baud = 921600,
2959 .uart_offset = 8 << 2,
2960 .reg_shift = 2,
2961 .first_offset = 0x03,
2962 },
2963
2964 /*
2965 * This board uses the size of PCI Base region 0 to
2966 * signal now many ports are available
2967 */
2968 [pbn_oxsemi] = {
2969 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2970 .num_ports = 32,
2971 .base_baud = 115200,
2972 .uart_offset = 8,
2973 },
2974 [pbn_oxsemi_1_4000000] = {
2975 .flags = FL_BASE0,
2976 .num_ports = 1,
2977 .base_baud = 4000000,
2978 .uart_offset = 0x200,
2979 .first_offset = 0x1000,
2980 },
2981 [pbn_oxsemi_2_4000000] = {
2982 .flags = FL_BASE0,
2983 .num_ports = 2,
2984 .base_baud = 4000000,
2985 .uart_offset = 0x200,
2986 .first_offset = 0x1000,
2987 },
2988 [pbn_oxsemi_4_4000000] = {
2989 .flags = FL_BASE0,
2990 .num_ports = 4,
2991 .base_baud = 4000000,
2992 .uart_offset = 0x200,
2993 .first_offset = 0x1000,
2994 },
2995 [pbn_oxsemi_8_4000000] = {
2996 .flags = FL_BASE0,
2997 .num_ports = 8,
2998 .base_baud = 4000000,
2999 .uart_offset = 0x200,
3000 .first_offset = 0x1000,
3001 },
3002
3003
3004 /*
3005 * EKF addition for i960 Boards form EKF with serial port.
3006 * Max 256 ports.
3007 */
3008 [pbn_intel_i960] = {
3009 .flags = FL_BASE0,
3010 .num_ports = 32,
3011 .base_baud = 921600,
3012 .uart_offset = 8 << 2,
3013 .reg_shift = 2,
3014 .first_offset = 0x10000,
3015 },
3016 [pbn_sgi_ioc3] = {
3017 .flags = FL_BASE0|FL_NOIRQ,
3018 .num_ports = 1,
3019 .base_baud = 458333,
3020 .uart_offset = 8,
3021 .reg_shift = 0,
3022 .first_offset = 0x20178,
3023 },
3024
3025 /*
3026 * Computone - uses IOMEM.
3027 */
3028 [pbn_computone_4] = {
3029 .flags = FL_BASE0,
3030 .num_ports = 4,
3031 .base_baud = 921600,
3032 .uart_offset = 0x40,
3033 .reg_shift = 2,
3034 .first_offset = 0x200,
3035 },
3036 [pbn_computone_6] = {
3037 .flags = FL_BASE0,
3038 .num_ports = 6,
3039 .base_baud = 921600,
3040 .uart_offset = 0x40,
3041 .reg_shift = 2,
3042 .first_offset = 0x200,
3043 },
3044 [pbn_computone_8] = {
3045 .flags = FL_BASE0,
3046 .num_ports = 8,
3047 .base_baud = 921600,
3048 .uart_offset = 0x40,
3049 .reg_shift = 2,
3050 .first_offset = 0x200,
3051 },
3052 [pbn_sbsxrsio] = {
3053 .flags = FL_BASE0,
3054 .num_ports = 8,
3055 .base_baud = 460800,
3056 .uart_offset = 256,
3057 .reg_shift = 4,
3058 },
3059 /*
3060 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3061 * Only basic 16550A support.
3062 * XR17C15[24] are not tested, but they should work.
3063 */
3064 [pbn_exar_XR17C152] = {
3065 .flags = FL_BASE0,
3066 .num_ports = 2,
3067 .base_baud = 921600,
3068 .uart_offset = 0x200,
3069 },
3070 [pbn_exar_XR17C154] = {
3071 .flags = FL_BASE0,
3072 .num_ports = 4,
3073 .base_baud = 921600,
3074 .uart_offset = 0x200,
3075 },
3076 [pbn_exar_XR17C158] = {
3077 .flags = FL_BASE0,
3078 .num_ports = 8,
3079 .base_baud = 921600,
3080 .uart_offset = 0x200,
3081 },
3082 [pbn_exar_XR17V352] = {
3083 .flags = FL_BASE0,
3084 .num_ports = 2,
3085 .base_baud = 7812500,
3086 .uart_offset = 0x400,
3087 .reg_shift = 0,
3088 .first_offset = 0,
3089 },
3090 [pbn_exar_XR17V354] = {
3091 .flags = FL_BASE0,
3092 .num_ports = 4,
3093 .base_baud = 7812500,
3094 .uart_offset = 0x400,
3095 .reg_shift = 0,
3096 .first_offset = 0,
3097 },
3098 [pbn_exar_XR17V358] = {
3099 .flags = FL_BASE0,
3100 .num_ports = 8,
3101 .base_baud = 7812500,
3102 .uart_offset = 0x400,
3103 .reg_shift = 0,
3104 .first_offset = 0,
3105 },
3106 [pbn_exar_ibm_saturn] = {
3107 .flags = FL_BASE0,
3108 .num_ports = 1,
3109 .base_baud = 921600,
3110 .uart_offset = 0x200,
3111 },
3112
3113 /*
3114 * PA Semi PWRficient PA6T-1682M on-chip UART
3115 */
3116 [pbn_pasemi_1682M] = {
3117 .flags = FL_BASE0,
3118 .num_ports = 1,
3119 .base_baud = 8333333,
3120 },
3121 /*
3122 * National Instruments 843x
3123 */
3124 [pbn_ni8430_16] = {
3125 .flags = FL_BASE0,
3126 .num_ports = 16,
3127 .base_baud = 3686400,
3128 .uart_offset = 0x10,
3129 .first_offset = 0x800,
3130 },
3131 [pbn_ni8430_8] = {
3132 .flags = FL_BASE0,
3133 .num_ports = 8,
3134 .base_baud = 3686400,
3135 .uart_offset = 0x10,
3136 .first_offset = 0x800,
3137 },
3138 [pbn_ni8430_4] = {
3139 .flags = FL_BASE0,
3140 .num_ports = 4,
3141 .base_baud = 3686400,
3142 .uart_offset = 0x10,
3143 .first_offset = 0x800,
3144 },
3145 [pbn_ni8430_2] = {
3146 .flags = FL_BASE0,
3147 .num_ports = 2,
3148 .base_baud = 3686400,
3149 .uart_offset = 0x10,
3150 .first_offset = 0x800,
3151 },
3152 /*
3153 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3154 */
3155 [pbn_ADDIDATA_PCIe_1_3906250] = {
3156 .flags = FL_BASE0,
3157 .num_ports = 1,
3158 .base_baud = 3906250,
3159 .uart_offset = 0x200,
3160 .first_offset = 0x1000,
3161 },
3162 [pbn_ADDIDATA_PCIe_2_3906250] = {
3163 .flags = FL_BASE0,
3164 .num_ports = 2,
3165 .base_baud = 3906250,
3166 .uart_offset = 0x200,
3167 .first_offset = 0x1000,
3168 },
3169 [pbn_ADDIDATA_PCIe_4_3906250] = {
3170 .flags = FL_BASE0,
3171 .num_ports = 4,
3172 .base_baud = 3906250,
3173 .uart_offset = 0x200,
3174 .first_offset = 0x1000,
3175 },
3176 [pbn_ADDIDATA_PCIe_8_3906250] = {
3177 .flags = FL_BASE0,
3178 .num_ports = 8,
3179 .base_baud = 3906250,
3180 .uart_offset = 0x200,
3181 .first_offset = 0x1000,
3182 },
3183 [pbn_ce4100_1_115200] = {
3184 .flags = FL_BASE_BARS,
3185 .num_ports = 2,
3186 .base_baud = 921600,
3187 .reg_shift = 2,
3188 },
3189 [pbn_omegapci] = {
3190 .flags = FL_BASE0,
3191 .num_ports = 8,
3192 .base_baud = 115200,
3193 .uart_offset = 0x200,
3194 },
3195 [pbn_NETMOS9900_2s_115200] = {
3196 .flags = FL_BASE0,
3197 .num_ports = 2,
3198 .base_baud = 115200,
3199 },
3200 [pbn_brcm_trumanage] = {
3201 .flags = FL_BASE0,
3202 .num_ports = 1,
3203 .reg_shift = 2,
3204 .base_baud = 115200,
3205 },
3206 };
3207
3208 static const struct pci_device_id blacklist[] = {
3209 /* softmodems */
3210 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3211 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3212 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3213
3214 /* multi-io cards handled by parport_serial */
3215 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3216 };
3217
3218 /*
3219 * Given a complete unknown PCI device, try to use some heuristics to
3220 * guess what the configuration might be, based on the pitiful PCI
3221 * serial specs. Returns 0 on success, 1 on failure.
3222 */
3223 static int
3224 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3225 {
3226 const struct pci_device_id *bldev;
3227 int num_iomem, num_port, first_port = -1, i;
3228
3229 /*
3230 * If it is not a communications device or the programming
3231 * interface is greater than 6, give up.
3232 *
3233 * (Should we try to make guesses for multiport serial devices
3234 * later?)
3235 */
3236 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3237 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3238 (dev->class & 0xff) > 6)
3239 return -ENODEV;
3240
3241 /*
3242 * Do not access blacklisted devices that are known not to
3243 * feature serial ports or are handled by other modules.
3244 */
3245 for (bldev = blacklist;
3246 bldev < blacklist + ARRAY_SIZE(blacklist);
3247 bldev++) {
3248 if (dev->vendor == bldev->vendor &&
3249 dev->device == bldev->device)
3250 return -ENODEV;
3251 }
3252
3253 num_iomem = num_port = 0;
3254 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3255 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3256 num_port++;
3257 if (first_port == -1)
3258 first_port = i;
3259 }
3260 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3261 num_iomem++;
3262 }
3263
3264 /*
3265 * If there is 1 or 0 iomem regions, and exactly one port,
3266 * use it. We guess the number of ports based on the IO
3267 * region size.
3268 */
3269 if (num_iomem <= 1 && num_port == 1) {
3270 board->flags = first_port;
3271 board->num_ports = pci_resource_len(dev, first_port) / 8;
3272 return 0;
3273 }
3274
3275 /*
3276 * Now guess if we've got a board which indexes by BARs.
3277 * Each IO BAR should be 8 bytes, and they should follow
3278 * consecutively.
3279 */
3280 first_port = -1;
3281 num_port = 0;
3282 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3283 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3284 pci_resource_len(dev, i) == 8 &&
3285 (first_port == -1 || (first_port + num_port) == i)) {
3286 num_port++;
3287 if (first_port == -1)
3288 first_port = i;
3289 }
3290 }
3291
3292 if (num_port > 1) {
3293 board->flags = first_port | FL_BASE_BARS;
3294 board->num_ports = num_port;
3295 return 0;
3296 }
3297
3298 return -ENODEV;
3299 }
3300
3301 static inline int
3302 serial_pci_matches(const struct pciserial_board *board,
3303 const struct pciserial_board *guessed)
3304 {
3305 return
3306 board->num_ports == guessed->num_ports &&
3307 board->base_baud == guessed->base_baud &&
3308 board->uart_offset == guessed->uart_offset &&
3309 board->reg_shift == guessed->reg_shift &&
3310 board->first_offset == guessed->first_offset;
3311 }
3312
3313 struct serial_private *
3314 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3315 {
3316 struct uart_8250_port uart;
3317 struct serial_private *priv;
3318 struct pci_serial_quirk *quirk;
3319 int rc, nr_ports, i;
3320
3321 nr_ports = board->num_ports;
3322
3323 /*
3324 * Find an init and setup quirks.
3325 */
3326 quirk = find_quirk(dev);
3327
3328 /*
3329 * Run the new-style initialization function.
3330 * The initialization function returns:
3331 * <0 - error
3332 * 0 - use board->num_ports
3333 * >0 - number of ports
3334 */
3335 if (quirk->init) {
3336 rc = quirk->init(dev);
3337 if (rc < 0) {
3338 priv = ERR_PTR(rc);
3339 goto err_out;
3340 }
3341 if (rc)
3342 nr_ports = rc;
3343 }
3344
3345 priv = kzalloc(sizeof(struct serial_private) +
3346 sizeof(unsigned int) * nr_ports,
3347 GFP_KERNEL);
3348 if (!priv) {
3349 priv = ERR_PTR(-ENOMEM);
3350 goto err_deinit;
3351 }
3352
3353 priv->dev = dev;
3354 priv->quirk = quirk;
3355
3356 memset(&uart, 0, sizeof(uart));
3357 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3358 uart.port.uartclk = board->base_baud * 16;
3359 uart.port.irq = get_pci_irq(dev, board);
3360 uart.port.dev = &dev->dev;
3361
3362 for (i = 0; i < nr_ports; i++) {
3363 if (quirk->setup(priv, board, &uart, i))
3364 break;
3365
3366 #ifdef SERIAL_DEBUG_PCI
3367 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3368 uart.port.iobase, uart.port.irq, uart.port.iotype);
3369 #endif
3370
3371 priv->line[i] = serial8250_register_8250_port(&uart);
3372 if (priv->line[i] < 0) {
3373 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3374 break;
3375 }
3376 }
3377 priv->nr = i;
3378 return priv;
3379
3380 err_deinit:
3381 if (quirk->exit)
3382 quirk->exit(dev);
3383 err_out:
3384 return priv;
3385 }
3386 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3387
3388 void pciserial_remove_ports(struct serial_private *priv)
3389 {
3390 struct pci_serial_quirk *quirk;
3391 int i;
3392
3393 for (i = 0; i < priv->nr; i++)
3394 serial8250_unregister_port(priv->line[i]);
3395
3396 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3397 if (priv->remapped_bar[i])
3398 iounmap(priv->remapped_bar[i]);
3399 priv->remapped_bar[i] = NULL;
3400 }
3401
3402 /*
3403 * Find the exit quirks.
3404 */
3405 quirk = find_quirk(priv->dev);
3406 if (quirk->exit)
3407 quirk->exit(priv->dev);
3408
3409 kfree(priv);
3410 }
3411 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3412
3413 void pciserial_suspend_ports(struct serial_private *priv)
3414 {
3415 int i;
3416
3417 for (i = 0; i < priv->nr; i++)
3418 if (priv->line[i] >= 0)
3419 serial8250_suspend_port(priv->line[i]);
3420
3421 /*
3422 * Ensure that every init quirk is properly torn down
3423 */
3424 if (priv->quirk->exit)
3425 priv->quirk->exit(priv->dev);
3426 }
3427 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3428
3429 void pciserial_resume_ports(struct serial_private *priv)
3430 {
3431 int i;
3432
3433 /*
3434 * Ensure that the board is correctly configured.
3435 */
3436 if (priv->quirk->init)
3437 priv->quirk->init(priv->dev);
3438
3439 for (i = 0; i < priv->nr; i++)
3440 if (priv->line[i] >= 0)
3441 serial8250_resume_port(priv->line[i]);
3442 }
3443 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3444
3445 /*
3446 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3447 * to the arrangement of serial ports on a PCI card.
3448 */
3449 static int
3450 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3451 {
3452 struct pci_serial_quirk *quirk;
3453 struct serial_private *priv;
3454 const struct pciserial_board *board;
3455 struct pciserial_board tmp;
3456 int rc;
3457
3458 quirk = find_quirk(dev);
3459 if (quirk->probe) {
3460 rc = quirk->probe(dev);
3461 if (rc)
3462 return rc;
3463 }
3464
3465 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3466 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3467 ent->driver_data);
3468 return -EINVAL;
3469 }
3470
3471 board = &pci_boards[ent->driver_data];
3472
3473 rc = pci_enable_device(dev);
3474 pci_save_state(dev);
3475 if (rc)
3476 return rc;
3477
3478 if (ent->driver_data == pbn_default) {
3479 /*
3480 * Use a copy of the pci_board entry for this;
3481 * avoid changing entries in the table.
3482 */
3483 memcpy(&tmp, board, sizeof(struct pciserial_board));
3484 board = &tmp;
3485
3486 /*
3487 * We matched one of our class entries. Try to
3488 * determine the parameters of this board.
3489 */
3490 rc = serial_pci_guess_board(dev, &tmp);
3491 if (rc)
3492 goto disable;
3493 } else {
3494 /*
3495 * We matched an explicit entry. If we are able to
3496 * detect this boards settings with our heuristic,
3497 * then we no longer need this entry.
3498 */
3499 memcpy(&tmp, &pci_boards[pbn_default],
3500 sizeof(struct pciserial_board));
3501 rc = serial_pci_guess_board(dev, &tmp);
3502 if (rc == 0 && serial_pci_matches(board, &tmp))
3503 moan_device("Redundant entry in serial pci_table.",
3504 dev);
3505 }
3506
3507 priv = pciserial_init_ports(dev, board);
3508 if (!IS_ERR(priv)) {
3509 pci_set_drvdata(dev, priv);
3510 return 0;
3511 }
3512
3513 rc = PTR_ERR(priv);
3514
3515 disable:
3516 pci_disable_device(dev);
3517 return rc;
3518 }
3519
3520 static void pciserial_remove_one(struct pci_dev *dev)
3521 {
3522 struct serial_private *priv = pci_get_drvdata(dev);
3523
3524 pci_set_drvdata(dev, NULL);
3525
3526 pciserial_remove_ports(priv);
3527
3528 pci_disable_device(dev);
3529 }
3530
3531 #ifdef CONFIG_PM
3532 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3533 {
3534 struct serial_private *priv = pci_get_drvdata(dev);
3535
3536 if (priv)
3537 pciserial_suspend_ports(priv);
3538
3539 pci_save_state(dev);
3540 pci_set_power_state(dev, pci_choose_state(dev, state));
3541 return 0;
3542 }
3543
3544 static int pciserial_resume_one(struct pci_dev *dev)
3545 {
3546 int err;
3547 struct serial_private *priv = pci_get_drvdata(dev);
3548
3549 pci_set_power_state(dev, PCI_D0);
3550 pci_restore_state(dev);
3551
3552 if (priv) {
3553 /*
3554 * The device may have been disabled. Re-enable it.
3555 */
3556 err = pci_enable_device(dev);
3557 /* FIXME: We cannot simply error out here */
3558 if (err)
3559 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3560 pciserial_resume_ports(priv);
3561 }
3562 return 0;
3563 }
3564 #endif
3565
3566 static struct pci_device_id serial_pci_tbl[] = {
3567 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3568 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3569 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3570 pbn_b2_8_921600 },
3571 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3572 PCI_SUBVENDOR_ID_CONNECT_TECH,
3573 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3574 pbn_b1_8_1382400 },
3575 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3576 PCI_SUBVENDOR_ID_CONNECT_TECH,
3577 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3578 pbn_b1_4_1382400 },
3579 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3580 PCI_SUBVENDOR_ID_CONNECT_TECH,
3581 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3582 pbn_b1_2_1382400 },
3583 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3584 PCI_SUBVENDOR_ID_CONNECT_TECH,
3585 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3586 pbn_b1_8_1382400 },
3587 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3588 PCI_SUBVENDOR_ID_CONNECT_TECH,
3589 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3590 pbn_b1_4_1382400 },
3591 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3592 PCI_SUBVENDOR_ID_CONNECT_TECH,
3593 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3594 pbn_b1_2_1382400 },
3595 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3596 PCI_SUBVENDOR_ID_CONNECT_TECH,
3597 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3598 pbn_b1_8_921600 },
3599 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3600 PCI_SUBVENDOR_ID_CONNECT_TECH,
3601 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3602 pbn_b1_8_921600 },
3603 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3604 PCI_SUBVENDOR_ID_CONNECT_TECH,
3605 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3606 pbn_b1_4_921600 },
3607 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3608 PCI_SUBVENDOR_ID_CONNECT_TECH,
3609 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3610 pbn_b1_4_921600 },
3611 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3612 PCI_SUBVENDOR_ID_CONNECT_TECH,
3613 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3614 pbn_b1_2_921600 },
3615 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3616 PCI_SUBVENDOR_ID_CONNECT_TECH,
3617 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3618 pbn_b1_8_921600 },
3619 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3620 PCI_SUBVENDOR_ID_CONNECT_TECH,
3621 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3622 pbn_b1_8_921600 },
3623 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3624 PCI_SUBVENDOR_ID_CONNECT_TECH,
3625 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3626 pbn_b1_4_921600 },
3627 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3628 PCI_SUBVENDOR_ID_CONNECT_TECH,
3629 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3630 pbn_b1_2_1250000 },
3631 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3632 PCI_SUBVENDOR_ID_CONNECT_TECH,
3633 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3634 pbn_b0_2_1843200 },
3635 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3636 PCI_SUBVENDOR_ID_CONNECT_TECH,
3637 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3638 pbn_b0_4_1843200 },
3639 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3640 PCI_VENDOR_ID_AFAVLAB,
3641 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3642 pbn_b0_4_1152000 },
3643 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3644 PCI_SUBVENDOR_ID_CONNECT_TECH,
3645 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3646 pbn_b0_2_1843200_200 },
3647 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3648 PCI_SUBVENDOR_ID_CONNECT_TECH,
3649 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3650 pbn_b0_4_1843200_200 },
3651 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3652 PCI_SUBVENDOR_ID_CONNECT_TECH,
3653 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3654 pbn_b0_8_1843200_200 },
3655 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3656 PCI_SUBVENDOR_ID_CONNECT_TECH,
3657 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3658 pbn_b0_2_1843200_200 },
3659 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3660 PCI_SUBVENDOR_ID_CONNECT_TECH,
3661 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3662 pbn_b0_4_1843200_200 },
3663 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3664 PCI_SUBVENDOR_ID_CONNECT_TECH,
3665 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3666 pbn_b0_8_1843200_200 },
3667 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3668 PCI_SUBVENDOR_ID_CONNECT_TECH,
3669 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3670 pbn_b0_2_1843200_200 },
3671 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3672 PCI_SUBVENDOR_ID_CONNECT_TECH,
3673 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3674 pbn_b0_4_1843200_200 },
3675 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3676 PCI_SUBVENDOR_ID_CONNECT_TECH,
3677 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3678 pbn_b0_8_1843200_200 },
3679 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3680 PCI_SUBVENDOR_ID_CONNECT_TECH,
3681 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3682 pbn_b0_2_1843200_200 },
3683 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3684 PCI_SUBVENDOR_ID_CONNECT_TECH,
3685 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3686 pbn_b0_4_1843200_200 },
3687 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3688 PCI_SUBVENDOR_ID_CONNECT_TECH,
3689 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3690 pbn_b0_8_1843200_200 },
3691 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3692 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3693 0, 0, pbn_exar_ibm_saturn },
3694
3695 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697 pbn_b2_bt_1_115200 },
3698 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700 pbn_b2_bt_2_115200 },
3701 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3703 pbn_b2_bt_4_115200 },
3704 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3706 pbn_b2_bt_2_115200 },
3707 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3709 pbn_b2_bt_4_115200 },
3710 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3712 pbn_b2_8_115200 },
3713 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3715 pbn_b2_8_460800 },
3716 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3718 pbn_b2_8_115200 },
3719
3720 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3722 pbn_b2_bt_2_115200 },
3723 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3725 pbn_b2_bt_2_921600 },
3726 /*
3727 * VScom SPCOM800, from sl@s.pl
3728 */
3729 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3731 pbn_b2_8_921600 },
3732 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3734 pbn_b2_4_921600 },
3735 /* Unknown card - subdevice 0x1584 */
3736 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3737 PCI_VENDOR_ID_PLX,
3738 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3739 pbn_b2_4_115200 },
3740 /* Unknown card - subdevice 0x1588 */
3741 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3742 PCI_VENDOR_ID_PLX,
3743 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3744 pbn_b2_8_115200 },
3745 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3746 PCI_SUBVENDOR_ID_KEYSPAN,
3747 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3748 pbn_panacom },
3749 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3751 pbn_panacom4 },
3752 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3754 pbn_panacom2 },
3755 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3756 PCI_VENDOR_ID_ESDGMBH,
3757 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3758 pbn_b2_4_115200 },
3759 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3760 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3761 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3762 pbn_b2_4_460800 },
3763 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3764 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3765 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3766 pbn_b2_8_460800 },
3767 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3768 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3769 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3770 pbn_b2_16_460800 },
3771 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3772 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3773 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3774 pbn_b2_16_460800 },
3775 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3776 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3777 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3778 pbn_b2_4_460800 },
3779 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3780 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3781 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3782 pbn_b2_8_460800 },
3783 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3784 PCI_SUBVENDOR_ID_EXSYS,
3785 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3786 pbn_b2_4_115200 },
3787 /*
3788 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3789 * (Exoray@isys.ca)
3790 */
3791 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3792 0x10b5, 0x106a, 0, 0,
3793 pbn_plx_romulus },
3794 /*
3795 * Quatech cards. These actually have configurable clocks but for
3796 * now we just use the default.
3797 *
3798 * 100 series are RS232, 200 series RS422,
3799 */
3800 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3802 pbn_b1_4_115200 },
3803 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3805 pbn_b1_2_115200 },
3806 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3808 pbn_b2_2_115200 },
3809 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3811 pbn_b1_2_115200 },
3812 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3814 pbn_b2_2_115200 },
3815 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3817 pbn_b1_4_115200 },
3818 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3820 pbn_b1_8_115200 },
3821 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3823 pbn_b1_8_115200 },
3824 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3826 pbn_b1_4_115200 },
3827 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3829 pbn_b1_2_115200 },
3830 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3832 pbn_b1_4_115200 },
3833 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3835 pbn_b1_2_115200 },
3836 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3838 pbn_b2_4_115200 },
3839 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3841 pbn_b2_2_115200 },
3842 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3844 pbn_b2_1_115200 },
3845 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3847 pbn_b2_4_115200 },
3848 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3850 pbn_b2_2_115200 },
3851 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3853 pbn_b2_1_115200 },
3854 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 pbn_b0_8_115200 },
3857
3858 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3859 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3860 0, 0,
3861 pbn_b0_4_921600 },
3862 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3863 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3864 0, 0,
3865 pbn_b0_4_1152000 },
3866 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3868 pbn_b0_bt_2_921600 },
3869
3870 /*
3871 * The below card is a little controversial since it is the
3872 * subject of a PCI vendor/device ID clash. (See
3873 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3874 * For now just used the hex ID 0x950a.
3875 */
3876 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3877 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3878 0, 0, pbn_b0_2_115200 },
3879 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3880 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3881 0, 0, pbn_b0_2_115200 },
3882 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_b0_2_1130000 },
3885 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3886 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3887 pbn_b0_1_921600 },
3888 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3890 pbn_b0_4_115200 },
3891 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3893 pbn_b0_bt_2_921600 },
3894 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3895 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3896 pbn_b2_8_1152000 },
3897
3898 /*
3899 * Oxford Semiconductor Inc. Tornado PCI express device range.
3900 */
3901 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903 pbn_b0_1_4000000 },
3904 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906 pbn_b0_1_4000000 },
3907 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909 pbn_oxsemi_1_4000000 },
3910 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912 pbn_oxsemi_1_4000000 },
3913 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915 pbn_b0_1_4000000 },
3916 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918 pbn_b0_1_4000000 },
3919 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921 pbn_oxsemi_1_4000000 },
3922 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3924 pbn_oxsemi_1_4000000 },
3925 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927 pbn_b0_1_4000000 },
3928 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3930 pbn_b0_1_4000000 },
3931 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933 pbn_b0_1_4000000 },
3934 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936 pbn_b0_1_4000000 },
3937 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939 pbn_oxsemi_2_4000000 },
3940 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942 pbn_oxsemi_2_4000000 },
3943 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945 pbn_oxsemi_4_4000000 },
3946 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 pbn_oxsemi_4_4000000 },
3949 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951 pbn_oxsemi_8_4000000 },
3952 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3954 pbn_oxsemi_8_4000000 },
3955 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3957 pbn_oxsemi_1_4000000 },
3958 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960 pbn_oxsemi_1_4000000 },
3961 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3963 pbn_oxsemi_1_4000000 },
3964 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3966 pbn_oxsemi_1_4000000 },
3967 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3969 pbn_oxsemi_1_4000000 },
3970 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3972 pbn_oxsemi_1_4000000 },
3973 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3975 pbn_oxsemi_1_4000000 },
3976 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3978 pbn_oxsemi_1_4000000 },
3979 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3981 pbn_oxsemi_1_4000000 },
3982 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3984 pbn_oxsemi_1_4000000 },
3985 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3987 pbn_oxsemi_1_4000000 },
3988 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990 pbn_oxsemi_1_4000000 },
3991 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993 pbn_oxsemi_1_4000000 },
3994 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996 pbn_oxsemi_1_4000000 },
3997 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3999 pbn_oxsemi_1_4000000 },
4000 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4002 pbn_oxsemi_1_4000000 },
4003 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4005 pbn_oxsemi_1_4000000 },
4006 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4008 pbn_oxsemi_1_4000000 },
4009 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4011 pbn_oxsemi_1_4000000 },
4012 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4014 pbn_oxsemi_1_4000000 },
4015 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4017 pbn_oxsemi_1_4000000 },
4018 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4020 pbn_oxsemi_1_4000000 },
4021 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4023 pbn_oxsemi_1_4000000 },
4024 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4026 pbn_oxsemi_1_4000000 },
4027 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4029 pbn_oxsemi_1_4000000 },
4030 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4032 pbn_oxsemi_1_4000000 },
4033 /*
4034 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4035 */
4036 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4037 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4038 pbn_oxsemi_1_4000000 },
4039 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4040 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4041 pbn_oxsemi_2_4000000 },
4042 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4043 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4044 pbn_oxsemi_4_4000000 },
4045 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4046 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4047 pbn_oxsemi_8_4000000 },
4048
4049 /*
4050 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4051 */
4052 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4053 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4054 pbn_oxsemi_2_4000000 },
4055
4056 /*
4057 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4058 * from skokodyn@yahoo.com
4059 */
4060 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4061 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4062 pbn_sbsxrsio },
4063 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4064 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4065 pbn_sbsxrsio },
4066 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4067 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4068 pbn_sbsxrsio },
4069 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4070 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4071 pbn_sbsxrsio },
4072
4073 /*
4074 * Digitan DS560-558, from jimd@esoft.com
4075 */
4076 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4078 pbn_b1_1_115200 },
4079
4080 /*
4081 * Titan Electronic cards
4082 * The 400L and 800L have a custom setup quirk.
4083 */
4084 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 pbn_b0_1_921600 },
4087 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089 pbn_b0_2_921600 },
4090 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092 pbn_b0_4_921600 },
4093 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095 pbn_b0_4_921600 },
4096 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4098 pbn_b1_1_921600 },
4099 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101 pbn_b1_bt_2_921600 },
4102 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104 pbn_b0_bt_4_921600 },
4105 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 pbn_b0_bt_8_921600 },
4108 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110 pbn_b4_bt_2_921600 },
4111 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113 pbn_b4_bt_4_921600 },
4114 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 pbn_b4_bt_8_921600 },
4117 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119 pbn_b0_4_921600 },
4120 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_b0_4_921600 },
4123 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 pbn_b0_4_921600 },
4126 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_oxsemi_1_4000000 },
4129 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_oxsemi_2_4000000 },
4132 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_oxsemi_4_4000000 },
4135 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_oxsemi_8_4000000 },
4138 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_oxsemi_2_4000000 },
4141 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_oxsemi_2_4000000 },
4144 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_b0_bt_2_921600 },
4147 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_b0_4_921600 },
4150 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_b0_4_921600 },
4153 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_b0_4_921600 },
4156 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_b0_4_921600 },
4159
4160 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162 pbn_b2_1_460800 },
4163 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165 pbn_b2_1_460800 },
4166 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168 pbn_b2_1_460800 },
4169 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_b2_bt_2_921600 },
4172 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174 pbn_b2_bt_2_921600 },
4175 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_b2_bt_2_921600 },
4178 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_b2_bt_4_921600 },
4181 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_b2_bt_4_921600 },
4184 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_b2_bt_4_921600 },
4187 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_b0_1_921600 },
4190 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_b0_1_921600 },
4193 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_b0_1_921600 },
4196 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_b0_bt_2_921600 },
4199 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_b0_bt_2_921600 },
4202 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_b0_bt_2_921600 },
4205 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_b0_bt_4_921600 },
4208 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_b0_bt_4_921600 },
4211 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_b0_bt_4_921600 },
4214 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_b0_bt_8_921600 },
4217 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_b0_bt_8_921600 },
4220 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_b0_bt_8_921600 },
4223
4224 /*
4225 * Computone devices submitted by Doug McNash dmcnash@computone.com
4226 */
4227 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4228 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4229 0, 0, pbn_computone_4 },
4230 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4231 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4232 0, 0, pbn_computone_8 },
4233 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4234 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4235 0, 0, pbn_computone_6 },
4236
4237 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_oxsemi },
4240 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4241 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4242 pbn_b0_bt_1_921600 },
4243
4244 /*
4245 * SUNIX (TIMEDIA)
4246 */
4247 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4248 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4249 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4250 pbn_b0_bt_1_921600 },
4251
4252 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4253 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4254 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4255 pbn_b0_bt_1_921600 },
4256
4257 /*
4258 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4259 */
4260 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 pbn_b0_bt_8_115200 },
4263 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265 pbn_b0_bt_8_115200 },
4266
4267 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_b0_bt_2_115200 },
4270 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_b0_bt_2_115200 },
4273 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_b0_bt_2_115200 },
4276 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_b0_bt_2_115200 },
4279 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_b0_bt_2_115200 },
4282 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b0_bt_4_460800 },
4285 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_b0_bt_4_460800 },
4288 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_b0_bt_2_460800 },
4291 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_b0_bt_2_460800 },
4294 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_b0_bt_2_460800 },
4297 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_b0_bt_1_115200 },
4300 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302 pbn_b0_bt_1_460800 },
4303
4304 /*
4305 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4306 * Cards are identified by their subsystem vendor IDs, which
4307 * (in hex) match the model number.
4308 *
4309 * Note that JC140x are RS422/485 cards which require ox950
4310 * ACR = 0x10, and as such are not currently fully supported.
4311 */
4312 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4313 0x1204, 0x0004, 0, 0,
4314 pbn_b0_4_921600 },
4315 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4316 0x1208, 0x0004, 0, 0,
4317 pbn_b0_4_921600 },
4318 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4319 0x1402, 0x0002, 0, 0,
4320 pbn_b0_2_921600 }, */
4321 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4322 0x1404, 0x0004, 0, 0,
4323 pbn_b0_4_921600 }, */
4324 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4325 0x1208, 0x0004, 0, 0,
4326 pbn_b0_4_921600 },
4327
4328 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4329 0x1204, 0x0004, 0, 0,
4330 pbn_b0_4_921600 },
4331 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4332 0x1208, 0x0004, 0, 0,
4333 pbn_b0_4_921600 },
4334 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4335 0x1208, 0x0004, 0, 0,
4336 pbn_b0_4_921600 },
4337 /*
4338 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4339 */
4340 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b1_1_1382400 },
4343
4344 /*
4345 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4346 */
4347 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 pbn_b1_1_1382400 },
4350
4351 /*
4352 * RAStel 2 port modem, gerg@moreton.com.au
4353 */
4354 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356 pbn_b2_bt_2_115200 },
4357
4358 /*
4359 * EKF addition for i960 Boards form EKF with serial port
4360 */
4361 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4362 0xE4BF, PCI_ANY_ID, 0, 0,
4363 pbn_intel_i960 },
4364
4365 /*
4366 * Xircom Cardbus/Ethernet combos
4367 */
4368 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 pbn_b0_1_115200 },
4371 /*
4372 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4373 */
4374 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_b0_1_115200 },
4377
4378 /*
4379 * Untested PCI modems, sent in from various folks...
4380 */
4381
4382 /*
4383 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4384 */
4385 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4386 0x1048, 0x1500, 0, 0,
4387 pbn_b1_1_115200 },
4388
4389 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4390 0xFF00, 0, 0, 0,
4391 pbn_sgi_ioc3 },
4392
4393 /*
4394 * HP Diva card
4395 */
4396 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4397 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4398 pbn_b1_1_115200 },
4399 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b0_5_115200 },
4402 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b2_1_115200 },
4405
4406 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408 pbn_b3_2_115200 },
4409 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 pbn_b3_4_115200 },
4412 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414 pbn_b3_8_115200 },
4415
4416 /*
4417 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4418 */
4419 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4420 PCI_ANY_ID, PCI_ANY_ID,
4421 0,
4422 0, pbn_exar_XR17C152 },
4423 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4424 PCI_ANY_ID, PCI_ANY_ID,
4425 0,
4426 0, pbn_exar_XR17C154 },
4427 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4428 PCI_ANY_ID, PCI_ANY_ID,
4429 0,
4430 0, pbn_exar_XR17C158 },
4431 /*
4432 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4433 */
4434 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4435 PCI_ANY_ID, PCI_ANY_ID,
4436 0,
4437 0, pbn_exar_XR17V352 },
4438 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4439 PCI_ANY_ID, PCI_ANY_ID,
4440 0,
4441 0, pbn_exar_XR17V354 },
4442 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4443 PCI_ANY_ID, PCI_ANY_ID,
4444 0,
4445 0, pbn_exar_XR17V358 },
4446
4447 /*
4448 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4449 */
4450 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_b0_1_115200 },
4453 /*
4454 * ITE
4455 */
4456 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4457 PCI_ANY_ID, PCI_ANY_ID,
4458 0, 0,
4459 pbn_b1_bt_1_115200 },
4460
4461 /*
4462 * IntaShield IS-200
4463 */
4464 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4466 pbn_b2_2_115200 },
4467 /*
4468 * IntaShield IS-400
4469 */
4470 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4472 pbn_b2_4_115200 },
4473 /*
4474 * Perle PCI-RAS cards
4475 */
4476 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4477 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4478 0, 0, pbn_b2_4_921600 },
4479 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4480 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4481 0, 0, pbn_b2_8_921600 },
4482
4483 /*
4484 * Mainpine series cards: Fairly standard layout but fools
4485 * parts of the autodetect in some cases and uses otherwise
4486 * unmatched communications subclasses in the PCI Express case
4487 */
4488
4489 { /* RockForceDUO */
4490 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4491 PCI_VENDOR_ID_MAINPINE, 0x0200,
4492 0, 0, pbn_b0_2_115200 },
4493 { /* RockForceQUATRO */
4494 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4495 PCI_VENDOR_ID_MAINPINE, 0x0300,
4496 0, 0, pbn_b0_4_115200 },
4497 { /* RockForceDUO+ */
4498 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4499 PCI_VENDOR_ID_MAINPINE, 0x0400,
4500 0, 0, pbn_b0_2_115200 },
4501 { /* RockForceQUATRO+ */
4502 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4503 PCI_VENDOR_ID_MAINPINE, 0x0500,
4504 0, 0, pbn_b0_4_115200 },
4505 { /* RockForce+ */
4506 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4507 PCI_VENDOR_ID_MAINPINE, 0x0600,
4508 0, 0, pbn_b0_2_115200 },
4509 { /* RockForce+ */
4510 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4511 PCI_VENDOR_ID_MAINPINE, 0x0700,
4512 0, 0, pbn_b0_4_115200 },
4513 { /* RockForceOCTO+ */
4514 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4515 PCI_VENDOR_ID_MAINPINE, 0x0800,
4516 0, 0, pbn_b0_8_115200 },
4517 { /* RockForceDUO+ */
4518 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4519 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4520 0, 0, pbn_b0_2_115200 },
4521 { /* RockForceQUARTRO+ */
4522 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4523 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4524 0, 0, pbn_b0_4_115200 },
4525 { /* RockForceOCTO+ */
4526 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4527 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4528 0, 0, pbn_b0_8_115200 },
4529 { /* RockForceD1 */
4530 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4531 PCI_VENDOR_ID_MAINPINE, 0x2000,
4532 0, 0, pbn_b0_1_115200 },
4533 { /* RockForceF1 */
4534 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4535 PCI_VENDOR_ID_MAINPINE, 0x2100,
4536 0, 0, pbn_b0_1_115200 },
4537 { /* RockForceD2 */
4538 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4539 PCI_VENDOR_ID_MAINPINE, 0x2200,
4540 0, 0, pbn_b0_2_115200 },
4541 { /* RockForceF2 */
4542 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4543 PCI_VENDOR_ID_MAINPINE, 0x2300,
4544 0, 0, pbn_b0_2_115200 },
4545 { /* RockForceD4 */
4546 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4547 PCI_VENDOR_ID_MAINPINE, 0x2400,
4548 0, 0, pbn_b0_4_115200 },
4549 { /* RockForceF4 */
4550 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4551 PCI_VENDOR_ID_MAINPINE, 0x2500,
4552 0, 0, pbn_b0_4_115200 },
4553 { /* RockForceD8 */
4554 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4555 PCI_VENDOR_ID_MAINPINE, 0x2600,
4556 0, 0, pbn_b0_8_115200 },
4557 { /* RockForceF8 */
4558 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4559 PCI_VENDOR_ID_MAINPINE, 0x2700,
4560 0, 0, pbn_b0_8_115200 },
4561 { /* IQ Express D1 */
4562 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4563 PCI_VENDOR_ID_MAINPINE, 0x3000,
4564 0, 0, pbn_b0_1_115200 },
4565 { /* IQ Express F1 */
4566 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4567 PCI_VENDOR_ID_MAINPINE, 0x3100,
4568 0, 0, pbn_b0_1_115200 },
4569 { /* IQ Express D2 */
4570 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4571 PCI_VENDOR_ID_MAINPINE, 0x3200,
4572 0, 0, pbn_b0_2_115200 },
4573 { /* IQ Express F2 */
4574 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4575 PCI_VENDOR_ID_MAINPINE, 0x3300,
4576 0, 0, pbn_b0_2_115200 },
4577 { /* IQ Express D4 */
4578 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4579 PCI_VENDOR_ID_MAINPINE, 0x3400,
4580 0, 0, pbn_b0_4_115200 },
4581 { /* IQ Express F4 */
4582 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4583 PCI_VENDOR_ID_MAINPINE, 0x3500,
4584 0, 0, pbn_b0_4_115200 },
4585 { /* IQ Express D8 */
4586 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4587 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4588 0, 0, pbn_b0_8_115200 },
4589 { /* IQ Express F8 */
4590 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4591 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4592 0, 0, pbn_b0_8_115200 },
4593
4594
4595 /*
4596 * PA Semi PA6T-1682M on-chip UART
4597 */
4598 { PCI_VENDOR_ID_PASEMI, 0xa004,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_pasemi_1682M },
4601
4602 /*
4603 * National Instruments
4604 */
4605 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b1_16_115200 },
4608 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b1_8_115200 },
4611 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b1_bt_4_115200 },
4614 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b1_bt_2_115200 },
4617 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b1_bt_4_115200 },
4620 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b1_bt_2_115200 },
4623 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b1_16_115200 },
4626 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_b1_8_115200 },
4629 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_b1_bt_4_115200 },
4632 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_b1_bt_2_115200 },
4635 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_b1_bt_4_115200 },
4638 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_b1_bt_2_115200 },
4641 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_ni8430_2 },
4644 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_ni8430_2 },
4647 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_ni8430_4 },
4650 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_ni8430_4 },
4653 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_ni8430_8 },
4656 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_ni8430_8 },
4659 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_ni8430_16 },
4662 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_ni8430_16 },
4665 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_ni8430_2 },
4668 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_ni8430_2 },
4671 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_ni8430_4 },
4674 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_ni8430_4 },
4677
4678 /*
4679 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4680 */
4681 { PCI_VENDOR_ID_ADDIDATA,
4682 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4683 PCI_ANY_ID,
4684 PCI_ANY_ID,
4685 0,
4686 0,
4687 pbn_b0_4_115200 },
4688
4689 { PCI_VENDOR_ID_ADDIDATA,
4690 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4691 PCI_ANY_ID,
4692 PCI_ANY_ID,
4693 0,
4694 0,
4695 pbn_b0_2_115200 },
4696
4697 { PCI_VENDOR_ID_ADDIDATA,
4698 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4699 PCI_ANY_ID,
4700 PCI_ANY_ID,
4701 0,
4702 0,
4703 pbn_b0_1_115200 },
4704
4705 { PCI_VENDOR_ID_AMCC,
4706 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4707 PCI_ANY_ID,
4708 PCI_ANY_ID,
4709 0,
4710 0,
4711 pbn_b1_8_115200 },
4712
4713 { PCI_VENDOR_ID_ADDIDATA,
4714 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4715 PCI_ANY_ID,
4716 PCI_ANY_ID,
4717 0,
4718 0,
4719 pbn_b0_4_115200 },
4720
4721 { PCI_VENDOR_ID_ADDIDATA,
4722 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4723 PCI_ANY_ID,
4724 PCI_ANY_ID,
4725 0,
4726 0,
4727 pbn_b0_2_115200 },
4728
4729 { PCI_VENDOR_ID_ADDIDATA,
4730 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4731 PCI_ANY_ID,
4732 PCI_ANY_ID,
4733 0,
4734 0,
4735 pbn_b0_1_115200 },
4736
4737 { PCI_VENDOR_ID_ADDIDATA,
4738 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4739 PCI_ANY_ID,
4740 PCI_ANY_ID,
4741 0,
4742 0,
4743 pbn_b0_4_115200 },
4744
4745 { PCI_VENDOR_ID_ADDIDATA,
4746 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4747 PCI_ANY_ID,
4748 PCI_ANY_ID,
4749 0,
4750 0,
4751 pbn_b0_2_115200 },
4752
4753 { PCI_VENDOR_ID_ADDIDATA,
4754 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4755 PCI_ANY_ID,
4756 PCI_ANY_ID,
4757 0,
4758 0,
4759 pbn_b0_1_115200 },
4760
4761 { PCI_VENDOR_ID_ADDIDATA,
4762 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4763 PCI_ANY_ID,
4764 PCI_ANY_ID,
4765 0,
4766 0,
4767 pbn_b0_8_115200 },
4768
4769 { PCI_VENDOR_ID_ADDIDATA,
4770 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4771 PCI_ANY_ID,
4772 PCI_ANY_ID,
4773 0,
4774 0,
4775 pbn_ADDIDATA_PCIe_4_3906250 },
4776
4777 { PCI_VENDOR_ID_ADDIDATA,
4778 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4779 PCI_ANY_ID,
4780 PCI_ANY_ID,
4781 0,
4782 0,
4783 pbn_ADDIDATA_PCIe_2_3906250 },
4784
4785 { PCI_VENDOR_ID_ADDIDATA,
4786 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4787 PCI_ANY_ID,
4788 PCI_ANY_ID,
4789 0,
4790 0,
4791 pbn_ADDIDATA_PCIe_1_3906250 },
4792
4793 { PCI_VENDOR_ID_ADDIDATA,
4794 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4795 PCI_ANY_ID,
4796 PCI_ANY_ID,
4797 0,
4798 0,
4799 pbn_ADDIDATA_PCIe_8_3906250 },
4800
4801 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4802 PCI_VENDOR_ID_IBM, 0x0299,
4803 0, 0, pbn_b0_bt_2_115200 },
4804
4805 /*
4806 * other NetMos 9835 devices are most likely handled by the
4807 * parport_serial driver, check drivers/parport/parport_serial.c
4808 * before adding them here.
4809 */
4810
4811 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4812 0xA000, 0x1000,
4813 0, 0, pbn_b0_1_115200 },
4814
4815 /* the 9901 is a rebranded 9912 */
4816 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4817 0xA000, 0x1000,
4818 0, 0, pbn_b0_1_115200 },
4819
4820 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4821 0xA000, 0x1000,
4822 0, 0, pbn_b0_1_115200 },
4823
4824 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4825 0xA000, 0x1000,
4826 0, 0, pbn_b0_1_115200 },
4827
4828 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4829 0xA000, 0x1000,
4830 0, 0, pbn_b0_1_115200 },
4831
4832 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4833 0xA000, 0x3002,
4834 0, 0, pbn_NETMOS9900_2s_115200 },
4835
4836 /*
4837 * Best Connectivity and Rosewill PCI Multi I/O cards
4838 */
4839
4840 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4841 0xA000, 0x1000,
4842 0, 0, pbn_b0_1_115200 },
4843
4844 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4845 0xA000, 0x3002,
4846 0, 0, pbn_b0_bt_2_115200 },
4847
4848 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4849 0xA000, 0x3004,
4850 0, 0, pbn_b0_bt_4_115200 },
4851 /* Intel CE4100 */
4852 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_ce4100_1_115200 },
4855
4856 /*
4857 * Cronyx Omega PCI
4858 */
4859 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_omegapci },
4862
4863 /*
4864 * Broadcom TruManage
4865 */
4866 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_brcm_trumanage },
4869
4870 /*
4871 * AgeStar as-prs2-009
4872 */
4873 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4874 PCI_ANY_ID, PCI_ANY_ID,
4875 0, 0, pbn_b0_bt_2_115200 },
4876
4877 /*
4878 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4879 * so not listed here.
4880 */
4881 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4882 PCI_ANY_ID, PCI_ANY_ID,
4883 0, 0, pbn_b0_bt_4_115200 },
4884
4885 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4886 PCI_ANY_ID, PCI_ANY_ID,
4887 0, 0, pbn_b0_bt_2_115200 },
4888
4889 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
4890 PCI_ANY_ID, PCI_ANY_ID,
4891 0, 0, pbn_b0_bt_2_115200 },
4892
4893 /*
4894 * Commtech, Inc. Fastcom adapters
4895 */
4896 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4897 PCI_ANY_ID, PCI_ANY_ID,
4898 0,
4899 0, pbn_b0_2_1152000_200 },
4900 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4901 PCI_ANY_ID, PCI_ANY_ID,
4902 0,
4903 0, pbn_b0_4_1152000_200 },
4904 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4905 PCI_ANY_ID, PCI_ANY_ID,
4906 0,
4907 0, pbn_b0_4_1152000_200 },
4908 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4909 PCI_ANY_ID, PCI_ANY_ID,
4910 0,
4911 0, pbn_b0_8_1152000_200 },
4912 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4913 PCI_ANY_ID, PCI_ANY_ID,
4914 0,
4915 0, pbn_exar_XR17V352 },
4916 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4917 PCI_ANY_ID, PCI_ANY_ID,
4918 0,
4919 0, pbn_exar_XR17V354 },
4920 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4921 PCI_ANY_ID, PCI_ANY_ID,
4922 0,
4923 0, pbn_exar_XR17V358 },
4924
4925 /*
4926 * These entries match devices with class COMMUNICATION_SERIAL,
4927 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4928 */
4929 { PCI_ANY_ID, PCI_ANY_ID,
4930 PCI_ANY_ID, PCI_ANY_ID,
4931 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4932 0xffff00, pbn_default },
4933 { PCI_ANY_ID, PCI_ANY_ID,
4934 PCI_ANY_ID, PCI_ANY_ID,
4935 PCI_CLASS_COMMUNICATION_MODEM << 8,
4936 0xffff00, pbn_default },
4937 { PCI_ANY_ID, PCI_ANY_ID,
4938 PCI_ANY_ID, PCI_ANY_ID,
4939 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4940 0xffff00, pbn_default },
4941 { 0, }
4942 };
4943
4944 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4945 pci_channel_state_t state)
4946 {
4947 struct serial_private *priv = pci_get_drvdata(dev);
4948
4949 if (state == pci_channel_io_perm_failure)
4950 return PCI_ERS_RESULT_DISCONNECT;
4951
4952 if (priv)
4953 pciserial_suspend_ports(priv);
4954
4955 pci_disable_device(dev);
4956
4957 return PCI_ERS_RESULT_NEED_RESET;
4958 }
4959
4960 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4961 {
4962 int rc;
4963
4964 rc = pci_enable_device(dev);
4965
4966 if (rc)
4967 return PCI_ERS_RESULT_DISCONNECT;
4968
4969 pci_restore_state(dev);
4970 pci_save_state(dev);
4971
4972 return PCI_ERS_RESULT_RECOVERED;
4973 }
4974
4975 static void serial8250_io_resume(struct pci_dev *dev)
4976 {
4977 struct serial_private *priv = pci_get_drvdata(dev);
4978
4979 if (priv)
4980 pciserial_resume_ports(priv);
4981 }
4982
4983 static const struct pci_error_handlers serial8250_err_handler = {
4984 .error_detected = serial8250_io_error_detected,
4985 .slot_reset = serial8250_io_slot_reset,
4986 .resume = serial8250_io_resume,
4987 };
4988
4989 static struct pci_driver serial_pci_driver = {
4990 .name = "serial",
4991 .probe = pciserial_init_one,
4992 .remove = pciserial_remove_one,
4993 #ifdef CONFIG_PM
4994 .suspend = pciserial_suspend_one,
4995 .resume = pciserial_resume_one,
4996 #endif
4997 .id_table = serial_pci_tbl,
4998 .err_handler = &serial8250_err_handler,
4999 };
5000
5001 module_pci_driver(serial_pci_driver);
5002
5003 MODULE_LICENSE("GPL");
5004 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5005 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux with added FPC-III support