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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / tty / serial / omap-serial.c
blob816d1a23f9d0ef725318afbf01448aa587a3371c
1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
36 #include <linux/io.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
42 #include <linux/gpio.h>
43 #include <linux/of_gpio.h>
44 #include <linux/platform_data/serial-omap.h>
45
46 #include <dt-bindings/gpio/gpio.h>
47
48 #define OMAP_MAX_HSUART_PORTS 6
49
50 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
51
52 #define OMAP_UART_REV_42 0x0402
53 #define OMAP_UART_REV_46 0x0406
54 #define OMAP_UART_REV_52 0x0502
55 #define OMAP_UART_REV_63 0x0603
56
57 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
58
59 /* Feature flags */
60 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
61
62 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
63 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
64
65 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
66
67 /* SCR register bitmasks */
68 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
69 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
70 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
71
72 /* FCR register bitmasks */
73 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
74 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
75
76 /* MVR register bitmasks */
77 #define OMAP_UART_MVR_SCHEME_SHIFT 30
78
79 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
80 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
81 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
82
83 #define OMAP_UART_MVR_MAJ_MASK 0x700
84 #define OMAP_UART_MVR_MAJ_SHIFT 8
85 #define OMAP_UART_MVR_MIN_MASK 0x3f
86
87 #define OMAP_UART_DMA_CH_FREE -1
88
89 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
90 #define OMAP_MODE13X_SPEED 230400
91
92 /* WER = 0x7F
93 * Enable module level wakeup in WER reg
94 */
95 #define OMAP_UART_WER_MOD_WKUP 0X7F
96
97 /* Enable XON/XOFF flow control on output */
98 #define OMAP_UART_SW_TX 0x08
99
100 /* Enable XON/XOFF flow control on input */
101 #define OMAP_UART_SW_RX 0x02
102
103 #define OMAP_UART_SW_CLR 0xF0
104
105 #define OMAP_UART_TCR_TRIG 0x0F
106
107 struct uart_omap_dma {
108 u8 uart_dma_tx;
109 u8 uart_dma_rx;
110 int rx_dma_channel;
111 int tx_dma_channel;
112 dma_addr_t rx_buf_dma_phys;
113 dma_addr_t tx_buf_dma_phys;
114 unsigned int uart_base;
115 /*
116 * Buffer for rx dma.It is not required for tx because the buffer
117 * comes from port structure.
118 */
119 unsigned char *rx_buf;
120 unsigned int prev_rx_dma_pos;
121 int tx_buf_size;
122 int tx_dma_used;
123 int rx_dma_used;
124 spinlock_t tx_lock;
125 spinlock_t rx_lock;
126 /* timer to poll activity on rx dma */
127 struct timer_list rx_timer;
128 unsigned int rx_buf_size;
129 unsigned int rx_poll_rate;
130 unsigned int rx_timeout;
131 };
132
133 struct uart_omap_port {
134 struct uart_port port;
135 struct uart_omap_dma uart_dma;
136 struct device *dev;
137
138 unsigned char ier;
139 unsigned char lcr;
140 unsigned char mcr;
141 unsigned char fcr;
142 unsigned char efr;
143 unsigned char dll;
144 unsigned char dlh;
145 unsigned char mdr1;
146 unsigned char scr;
147 unsigned char wer;
148
149 int use_dma;
150 /*
151 * Some bits in registers are cleared on a read, so they must
152 * be saved whenever the register is read but the bits will not
153 * be immediately processed.
154 */
155 unsigned int lsr_break_flag;
156 unsigned char msr_saved_flags;
157 char name[20];
158 unsigned long port_activity;
159 int context_loss_cnt;
160 u32 errata;
161 u8 wakeups_enabled;
162 u32 features;
163
164 int DTR_gpio;
165 int DTR_inverted;
166 int DTR_active;
167
168 struct serial_rs485 rs485;
169 int rts_gpio;
170
171 struct pm_qos_request pm_qos_request;
172 u32 latency;
173 u32 calc_latency;
174 struct work_struct qos_work;
175 bool is_suspending;
176 };
177
178 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
179
180 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
181
182 /* Forward declaration of functions */
183 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
184
185 static struct workqueue_struct *serial_omap_uart_wq;
186
187 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
188 {
189 offset <<= up->port.regshift;
190 return readw(up->port.membase + offset);
191 }
192
193 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
194 {
195 offset <<= up->port.regshift;
196 writew(value, up->port.membase + offset);
197 }
198
199 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
200 {
201 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
202 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
203 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
204 serial_out(up, UART_FCR, 0);
205 }
206
207 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
208 {
209 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
210
211 if (!pdata || !pdata->get_context_loss_count)
212 return -EINVAL;
213
214 return pdata->get_context_loss_count(up->dev);
215 }
216
217 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
218 {
219 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
220
221 if (!pdata || !pdata->enable_wakeup)
222 return;
223
224 pdata->enable_wakeup(up->dev, enable);
225 }
226
227 /*
228 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
229 * @port: uart port info
230 * @baud: baudrate for which mode needs to be determined
231 *
232 * Returns true if baud rate is MODE16X and false if MODE13X
233 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
234 * and Error Rates" determines modes not for all common baud rates.
235 * E.g. for 1000000 baud rate mode must be 16x, but according to that
236 * table it's determined as 13x.
237 */
238 static bool
239 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
240 {
241 unsigned int n13 = port->uartclk / (13 * baud);
242 unsigned int n16 = port->uartclk / (16 * baud);
243 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
244 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
245 if(baudAbsDiff13 < 0)
246 baudAbsDiff13 = -baudAbsDiff13;
247 if(baudAbsDiff16 < 0)
248 baudAbsDiff16 = -baudAbsDiff16;
249
250 return (baudAbsDiff13 > baudAbsDiff16);
251 }
252
253 /*
254 * serial_omap_get_divisor - calculate divisor value
255 * @port: uart port info
256 * @baud: baudrate for which divisor needs to be calculated.
257 */
258 static unsigned int
259 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
260 {
261 unsigned int divisor;
262
263 if (!serial_omap_baud_is_mode16(port, baud))
264 divisor = 13;
265 else
266 divisor = 16;
267 return port->uartclk/(baud * divisor);
268 }
269
270 static void serial_omap_enable_ms(struct uart_port *port)
271 {
272 struct uart_omap_port *up = to_uart_omap_port(port);
273
274 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
275
276 pm_runtime_get_sync(up->dev);
277 up->ier |= UART_IER_MSI;
278 serial_out(up, UART_IER, up->ier);
279 pm_runtime_mark_last_busy(up->dev);
280 pm_runtime_put_autosuspend(up->dev);
281 }
282
283 static void serial_omap_stop_tx(struct uart_port *port)
284 {
285 struct uart_omap_port *up = to_uart_omap_port(port);
286 struct circ_buf *xmit = &up->port.state->xmit;
287 int res;
288
289 pm_runtime_get_sync(up->dev);
290
291 /* handle rs485 */
292 if (up->rs485.flags & SER_RS485_ENABLED) {
293 /* do nothing if current tx not yet completed */
294 res = serial_in(up, UART_LSR) & UART_LSR_TEMT;
295 if (!res)
296 return;
297
298 /* if there's no more data to send, turn off rts */
299 if (uart_circ_empty(xmit)) {
300 /* if rts not already disabled */
301 res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
302 if (gpio_get_value(up->rts_gpio) != res) {
303 if (up->rs485.delay_rts_after_send > 0) {
304 mdelay(up->rs485.delay_rts_after_send);
305 }
306 gpio_set_value(up->rts_gpio, res);
307 }
308 }
309 }
310
311 if (up->ier & UART_IER_THRI) {
312 up->ier &= ~UART_IER_THRI;
313 serial_out(up, UART_IER, up->ier);
314 }
315
316 if ((up->rs485.flags & SER_RS485_ENABLED) &&
317 !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
318 up->ier = UART_IER_RLSI | UART_IER_RDI;
319 serial_out(up, UART_IER, up->ier);
320 }
321
322 pm_runtime_mark_last_busy(up->dev);
323 pm_runtime_put_autosuspend(up->dev);
324 }
325
326 static void serial_omap_stop_rx(struct uart_port *port)
327 {
328 struct uart_omap_port *up = to_uart_omap_port(port);
329
330 pm_runtime_get_sync(up->dev);
331 up->ier &= ~UART_IER_RLSI;
332 up->port.read_status_mask &= ~UART_LSR_DR;
333 serial_out(up, UART_IER, up->ier);
334 pm_runtime_mark_last_busy(up->dev);
335 pm_runtime_put_autosuspend(up->dev);
336 }
337
338 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
339 {
340 struct circ_buf *xmit = &up->port.state->xmit;
341 int count;
342
343 if (up->port.x_char) {
344 serial_out(up, UART_TX, up->port.x_char);
345 up->port.icount.tx++;
346 up->port.x_char = 0;
347 return;
348 }
349 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
350 serial_omap_stop_tx(&up->port);
351 return;
352 }
353 count = up->port.fifosize / 4;
354 do {
355 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
356 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
357 up->port.icount.tx++;
358 if (uart_circ_empty(xmit))
359 break;
360 } while (--count > 0);
361
362 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
363 spin_unlock(&up->port.lock);
364 uart_write_wakeup(&up->port);
365 spin_lock(&up->port.lock);
366 }
367
368 if (uart_circ_empty(xmit))
369 serial_omap_stop_tx(&up->port);
370 }
371
372 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
373 {
374 if (!(up->ier & UART_IER_THRI)) {
375 up->ier |= UART_IER_THRI;
376 serial_out(up, UART_IER, up->ier);
377 }
378 }
379
380 static void serial_omap_start_tx(struct uart_port *port)
381 {
382 struct uart_omap_port *up = to_uart_omap_port(port);
383 int res;
384
385 pm_runtime_get_sync(up->dev);
386
387 /* handle rs485 */
388 if (up->rs485.flags & SER_RS485_ENABLED) {
389 /* if rts not already enabled */
390 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
391 if (gpio_get_value(up->rts_gpio) != res) {
392 gpio_set_value(up->rts_gpio, res);
393 if (up->rs485.delay_rts_before_send > 0) {
394 mdelay(up->rs485.delay_rts_before_send);
395 }
396 }
397 }
398
399 if ((up->rs485.flags & SER_RS485_ENABLED) &&
400 !(up->rs485.flags & SER_RS485_RX_DURING_TX))
401 serial_omap_stop_rx(port);
402
403 serial_omap_enable_ier_thri(up);
404 pm_runtime_mark_last_busy(up->dev);
405 pm_runtime_put_autosuspend(up->dev);
406 }
407
408 static void serial_omap_throttle(struct uart_port *port)
409 {
410 struct uart_omap_port *up = to_uart_omap_port(port);
411 unsigned long flags;
412
413 pm_runtime_get_sync(up->dev);
414 spin_lock_irqsave(&up->port.lock, flags);
415 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
416 serial_out(up, UART_IER, up->ier);
417 spin_unlock_irqrestore(&up->port.lock, flags);
418 pm_runtime_mark_last_busy(up->dev);
419 pm_runtime_put_autosuspend(up->dev);
420 }
421
422 static void serial_omap_unthrottle(struct uart_port *port)
423 {
424 struct uart_omap_port *up = to_uart_omap_port(port);
425 unsigned long flags;
426
427 pm_runtime_get_sync(up->dev);
428 spin_lock_irqsave(&up->port.lock, flags);
429 up->ier |= UART_IER_RLSI | UART_IER_RDI;
430 serial_out(up, UART_IER, up->ier);
431 spin_unlock_irqrestore(&up->port.lock, flags);
432 pm_runtime_mark_last_busy(up->dev);
433 pm_runtime_put_autosuspend(up->dev);
434 }
435
436 static unsigned int check_modem_status(struct uart_omap_port *up)
437 {
438 unsigned int status;
439
440 status = serial_in(up, UART_MSR);
441 status |= up->msr_saved_flags;
442 up->msr_saved_flags = 0;
443 if ((status & UART_MSR_ANY_DELTA) == 0)
444 return status;
445
446 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
447 up->port.state != NULL) {
448 if (status & UART_MSR_TERI)
449 up->port.icount.rng++;
450 if (status & UART_MSR_DDSR)
451 up->port.icount.dsr++;
452 if (status & UART_MSR_DDCD)
453 uart_handle_dcd_change
454 (&up->port, status & UART_MSR_DCD);
455 if (status & UART_MSR_DCTS)
456 uart_handle_cts_change
457 (&up->port, status & UART_MSR_CTS);
458 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
459 }
460
461 return status;
462 }
463
464 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
465 {
466 unsigned int flag;
467 unsigned char ch = 0;
468
469 if (likely(lsr & UART_LSR_DR))
470 ch = serial_in(up, UART_RX);
471
472 up->port.icount.rx++;
473 flag = TTY_NORMAL;
474
475 if (lsr & UART_LSR_BI) {
476 flag = TTY_BREAK;
477 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
478 up->port.icount.brk++;
479 /*
480 * We do the SysRQ and SAK checking
481 * here because otherwise the break
482 * may get masked by ignore_status_mask
483 * or read_status_mask.
484 */
485 if (uart_handle_break(&up->port))
486 return;
487
488 }
489
490 if (lsr & UART_LSR_PE) {
491 flag = TTY_PARITY;
492 up->port.icount.parity++;
493 }
494
495 if (lsr & UART_LSR_FE) {
496 flag = TTY_FRAME;
497 up->port.icount.frame++;
498 }
499
500 if (lsr & UART_LSR_OE)
501 up->port.icount.overrun++;
502
503 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
504 if (up->port.line == up->port.cons->index) {
505 /* Recover the break flag from console xmit */
506 lsr |= up->lsr_break_flag;
507 }
508 #endif
509 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
510 }
511
512 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
513 {
514 unsigned char ch = 0;
515 unsigned int flag;
516
517 if (!(lsr & UART_LSR_DR))
518 return;
519
520 ch = serial_in(up, UART_RX);
521 flag = TTY_NORMAL;
522 up->port.icount.rx++;
523
524 if (uart_handle_sysrq_char(&up->port, ch))
525 return;
526
527 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
528 }
529
530 /**
531 * serial_omap_irq() - This handles the interrupt from one port
532 * @irq: uart port irq number
533 * @dev_id: uart port info
534 */
535 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
536 {
537 struct uart_omap_port *up = dev_id;
538 unsigned int iir, lsr;
539 unsigned int type;
540 irqreturn_t ret = IRQ_NONE;
541 int max_count = 256;
542
543 spin_lock(&up->port.lock);
544 pm_runtime_get_sync(up->dev);
545
546 do {
547 iir = serial_in(up, UART_IIR);
548 if (iir & UART_IIR_NO_INT)
549 break;
550
551 ret = IRQ_HANDLED;
552 lsr = serial_in(up, UART_LSR);
553
554 /* extract IRQ type from IIR register */
555 type = iir & 0x3e;
556
557 switch (type) {
558 case UART_IIR_MSI:
559 check_modem_status(up);
560 break;
561 case UART_IIR_THRI:
562 transmit_chars(up, lsr);
563 break;
564 case UART_IIR_RX_TIMEOUT:
565 /* FALLTHROUGH */
566 case UART_IIR_RDI:
567 serial_omap_rdi(up, lsr);
568 break;
569 case UART_IIR_RLSI:
570 serial_omap_rlsi(up, lsr);
571 break;
572 case UART_IIR_CTS_RTS_DSR:
573 /* simply try again */
574 break;
575 case UART_IIR_XOFF:
576 /* FALLTHROUGH */
577 default:
578 break;
579 }
580 } while (!(iir & UART_IIR_NO_INT) && max_count--);
581
582 spin_unlock(&up->port.lock);
583
584 tty_flip_buffer_push(&up->port.state->port);
585
586 pm_runtime_mark_last_busy(up->dev);
587 pm_runtime_put_autosuspend(up->dev);
588 up->port_activity = jiffies;
589
590 return ret;
591 }
592
593 static unsigned int serial_omap_tx_empty(struct uart_port *port)
594 {
595 struct uart_omap_port *up = to_uart_omap_port(port);
596 unsigned long flags = 0;
597 unsigned int ret = 0;
598
599 pm_runtime_get_sync(up->dev);
600 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
601 spin_lock_irqsave(&up->port.lock, flags);
602 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
603 spin_unlock_irqrestore(&up->port.lock, flags);
604 pm_runtime_mark_last_busy(up->dev);
605 pm_runtime_put_autosuspend(up->dev);
606 return ret;
607 }
608
609 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
610 {
611 struct uart_omap_port *up = to_uart_omap_port(port);
612 unsigned int status;
613 unsigned int ret = 0;
614
615 pm_runtime_get_sync(up->dev);
616 status = check_modem_status(up);
617 pm_runtime_mark_last_busy(up->dev);
618 pm_runtime_put_autosuspend(up->dev);
619
620 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
621
622 if (status & UART_MSR_DCD)
623 ret |= TIOCM_CAR;
624 if (status & UART_MSR_RI)
625 ret |= TIOCM_RNG;
626 if (status & UART_MSR_DSR)
627 ret |= TIOCM_DSR;
628 if (status & UART_MSR_CTS)
629 ret |= TIOCM_CTS;
630 return ret;
631 }
632
633 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
634 {
635 struct uart_omap_port *up = to_uart_omap_port(port);
636 unsigned char mcr = 0, old_mcr;
637
638 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
639 if (mctrl & TIOCM_RTS)
640 mcr |= UART_MCR_RTS;
641 if (mctrl & TIOCM_DTR)
642 mcr |= UART_MCR_DTR;
643 if (mctrl & TIOCM_OUT1)
644 mcr |= UART_MCR_OUT1;
645 if (mctrl & TIOCM_OUT2)
646 mcr |= UART_MCR_OUT2;
647 if (mctrl & TIOCM_LOOP)
648 mcr |= UART_MCR_LOOP;
649
650 pm_runtime_get_sync(up->dev);
651 old_mcr = serial_in(up, UART_MCR);
652 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
653 UART_MCR_DTR | UART_MCR_RTS);
654 up->mcr = old_mcr | mcr;
655 serial_out(up, UART_MCR, up->mcr);
656 pm_runtime_mark_last_busy(up->dev);
657 pm_runtime_put_autosuspend(up->dev);
658
659 if (gpio_is_valid(up->DTR_gpio) &&
660 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
661 up->DTR_active = !up->DTR_active;
662 if (gpio_cansleep(up->DTR_gpio))
663 schedule_work(&up->qos_work);
664 else
665 gpio_set_value(up->DTR_gpio,
666 up->DTR_active != up->DTR_inverted);
667 }
668 }
669
670 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
671 {
672 struct uart_omap_port *up = to_uart_omap_port(port);
673 unsigned long flags = 0;
674
675 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
676 pm_runtime_get_sync(up->dev);
677 spin_lock_irqsave(&up->port.lock, flags);
678 if (break_state == -1)
679 up->lcr |= UART_LCR_SBC;
680 else
681 up->lcr &= ~UART_LCR_SBC;
682 serial_out(up, UART_LCR, up->lcr);
683 spin_unlock_irqrestore(&up->port.lock, flags);
684 pm_runtime_mark_last_busy(up->dev);
685 pm_runtime_put_autosuspend(up->dev);
686 }
687
688 static int serial_omap_startup(struct uart_port *port)
689 {
690 struct uart_omap_port *up = to_uart_omap_port(port);
691 unsigned long flags = 0;
692 int retval;
693
694 /*
695 * Allocate the IRQ
696 */
697 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
698 up->name, up);
699 if (retval)
700 return retval;
701
702 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
703
704 pm_runtime_get_sync(up->dev);
705 /*
706 * Clear the FIFO buffers and disable them.
707 * (they will be reenabled in set_termios())
708 */
709 serial_omap_clear_fifos(up);
710 /* For Hardware flow control */
711 serial_out(up, UART_MCR, UART_MCR_RTS);
712
713 /*
714 * Clear the interrupt registers.
715 */
716 (void) serial_in(up, UART_LSR);
717 if (serial_in(up, UART_LSR) & UART_LSR_DR)
718 (void) serial_in(up, UART_RX);
719 (void) serial_in(up, UART_IIR);
720 (void) serial_in(up, UART_MSR);
721
722 /*
723 * Now, initialize the UART
724 */
725 serial_out(up, UART_LCR, UART_LCR_WLEN8);
726 spin_lock_irqsave(&up->port.lock, flags);
727 /*
728 * Most PC uarts need OUT2 raised to enable interrupts.
729 */
730 up->port.mctrl |= TIOCM_OUT2;
731 serial_omap_set_mctrl(&up->port, up->port.mctrl);
732 spin_unlock_irqrestore(&up->port.lock, flags);
733
734 up->msr_saved_flags = 0;
735 /*
736 * Finally, enable interrupts. Note: Modem status interrupts
737 * are set via set_termios(), which will be occurring imminently
738 * anyway, so we don't enable them here.
739 */
740 up->ier = UART_IER_RLSI | UART_IER_RDI;
741 serial_out(up, UART_IER, up->ier);
742
743 /* Enable module level wake up */
744 up->wer = OMAP_UART_WER_MOD_WKUP;
745 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
746 up->wer |= OMAP_UART_TX_WAKEUP_EN;
747
748 serial_out(up, UART_OMAP_WER, up->wer);
749
750 pm_runtime_mark_last_busy(up->dev);
751 pm_runtime_put_autosuspend(up->dev);
752 up->port_activity = jiffies;
753 return 0;
754 }
755
756 static void serial_omap_shutdown(struct uart_port *port)
757 {
758 struct uart_omap_port *up = to_uart_omap_port(port);
759 unsigned long flags = 0;
760
761 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
762
763 pm_runtime_get_sync(up->dev);
764 /*
765 * Disable interrupts from this port
766 */
767 up->ier = 0;
768 serial_out(up, UART_IER, 0);
769
770 spin_lock_irqsave(&up->port.lock, flags);
771 up->port.mctrl &= ~TIOCM_OUT2;
772 serial_omap_set_mctrl(&up->port, up->port.mctrl);
773 spin_unlock_irqrestore(&up->port.lock, flags);
774
775 /*
776 * Disable break condition and FIFOs
777 */
778 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
779 serial_omap_clear_fifos(up);
780
781 /*
782 * Read data port to reset things, and then free the irq
783 */
784 if (serial_in(up, UART_LSR) & UART_LSR_DR)
785 (void) serial_in(up, UART_RX);
786
787 pm_runtime_mark_last_busy(up->dev);
788 pm_runtime_put_autosuspend(up->dev);
789 free_irq(up->port.irq, up);
790 }
791
792 static void serial_omap_uart_qos_work(struct work_struct *work)
793 {
794 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
795 qos_work);
796
797 pm_qos_update_request(&up->pm_qos_request, up->latency);
798 if (gpio_is_valid(up->DTR_gpio))
799 gpio_set_value_cansleep(up->DTR_gpio,
800 up->DTR_active != up->DTR_inverted);
801 }
802
803 static void
804 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
805 struct ktermios *old)
806 {
807 struct uart_omap_port *up = to_uart_omap_port(port);
808 unsigned char cval = 0;
809 unsigned long flags = 0;
810 unsigned int baud, quot;
811
812 switch (termios->c_cflag & CSIZE) {
813 case CS5:
814 cval = UART_LCR_WLEN5;
815 break;
816 case CS6:
817 cval = UART_LCR_WLEN6;
818 break;
819 case CS7:
820 cval = UART_LCR_WLEN7;
821 break;
822 default:
823 case CS8:
824 cval = UART_LCR_WLEN8;
825 break;
826 }
827
828 if (termios->c_cflag & CSTOPB)
829 cval |= UART_LCR_STOP;
830 if (termios->c_cflag & PARENB)
831 cval |= UART_LCR_PARITY;
832 if (!(termios->c_cflag & PARODD))
833 cval |= UART_LCR_EPAR;
834 if (termios->c_cflag & CMSPAR)
835 cval |= UART_LCR_SPAR;
836
837 /*
838 * Ask the core to calculate the divisor for us.
839 */
840
841 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
842 quot = serial_omap_get_divisor(port, baud);
843
844 /* calculate wakeup latency constraint */
845 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
846 up->latency = up->calc_latency;
847 schedule_work(&up->qos_work);
848
849 up->dll = quot & 0xff;
850 up->dlh = quot >> 8;
851 up->mdr1 = UART_OMAP_MDR1_DISABLE;
852
853 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
854 UART_FCR_ENABLE_FIFO;
855
856 /*
857 * Ok, we're now changing the port state. Do it with
858 * interrupts disabled.
859 */
860 pm_runtime_get_sync(up->dev);
861 spin_lock_irqsave(&up->port.lock, flags);
862
863 /*
864 * Update the per-port timeout.
865 */
866 uart_update_timeout(port, termios->c_cflag, baud);
867
868 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
869 if (termios->c_iflag & INPCK)
870 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
871 if (termios->c_iflag & (BRKINT | PARMRK))
872 up->port.read_status_mask |= UART_LSR_BI;
873
874 /*
875 * Characters to ignore
876 */
877 up->port.ignore_status_mask = 0;
878 if (termios->c_iflag & IGNPAR)
879 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
880 if (termios->c_iflag & IGNBRK) {
881 up->port.ignore_status_mask |= UART_LSR_BI;
882 /*
883 * If we're ignoring parity and break indicators,
884 * ignore overruns too (for real raw support).
885 */
886 if (termios->c_iflag & IGNPAR)
887 up->port.ignore_status_mask |= UART_LSR_OE;
888 }
889
890 /*
891 * ignore all characters if CREAD is not set
892 */
893 if ((termios->c_cflag & CREAD) == 0)
894 up->port.ignore_status_mask |= UART_LSR_DR;
895
896 /*
897 * Modem status interrupts
898 */
899 up->ier &= ~UART_IER_MSI;
900 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
901 up->ier |= UART_IER_MSI;
902 serial_out(up, UART_IER, up->ier);
903 serial_out(up, UART_LCR, cval); /* reset DLAB */
904 up->lcr = cval;
905 up->scr = 0;
906
907 /* FIFOs and DMA Settings */
908
909 /* FCR can be changed only when the
910 * baud clock is not running
911 * DLL_REG and DLH_REG set to 0.
912 */
913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
914 serial_out(up, UART_DLL, 0);
915 serial_out(up, UART_DLM, 0);
916 serial_out(up, UART_LCR, 0);
917
918 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
919
920 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
921 up->efr &= ~UART_EFR_SCD;
922 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
923
924 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
925 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
926 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
927 /* FIFO ENABLE, DMA MODE */
928
929 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
930 /*
931 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
932 * sets Enables the granularity of 1 for TRIGGER RX
933 * level. Along with setting RX FIFO trigger level
934 * to 1 (as noted below, 16 characters) and TLR[3:0]
935 * to zero this will result RX FIFO threshold level
936 * to 1 character, instead of 16 as noted in comment
937 * below.
938 */
939
940 /* Set receive FIFO threshold to 16 characters and
941 * transmit FIFO threshold to 16 spaces
942 */
943 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
944 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
945 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
946 UART_FCR_ENABLE_FIFO;
947
948 serial_out(up, UART_FCR, up->fcr);
949 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
950
951 serial_out(up, UART_OMAP_SCR, up->scr);
952
953 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
954 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
955 serial_out(up, UART_MCR, up->mcr);
956 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
957 serial_out(up, UART_EFR, up->efr);
958 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
959
960 /* Protocol, Baud Rate, and Interrupt Settings */
961
962 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
963 serial_omap_mdr1_errataset(up, up->mdr1);
964 else
965 serial_out(up, UART_OMAP_MDR1, up->mdr1);
966
967 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
968 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
969
970 serial_out(up, UART_LCR, 0);
971 serial_out(up, UART_IER, 0);
972 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
973
974 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
975 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
976
977 serial_out(up, UART_LCR, 0);
978 serial_out(up, UART_IER, up->ier);
979 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
980
981 serial_out(up, UART_EFR, up->efr);
982 serial_out(up, UART_LCR, cval);
983
984 if (!serial_omap_baud_is_mode16(port, baud))
985 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
986 else
987 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
988
989 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
990 serial_omap_mdr1_errataset(up, up->mdr1);
991 else
992 serial_out(up, UART_OMAP_MDR1, up->mdr1);
993
994 /* Configure flow control */
995 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
996
997 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
998 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
999 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1000
1001 /* Enable access to TCR/TLR */
1002 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1003 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1004 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1005
1006 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1007
1008 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1009 /* Enable AUTORTS and AUTOCTS */
1010 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1011
1012 /* Ensure MCR RTS is asserted */
1013 up->mcr |= UART_MCR_RTS;
1014 } else {
1015 /* Disable AUTORTS and AUTOCTS */
1016 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1017 }
1018
1019 if (up->port.flags & UPF_SOFT_FLOW) {
1020 /* clear SW control mode bits */
1021 up->efr &= OMAP_UART_SW_CLR;
1022
1023 /*
1024 * IXON Flag:
1025 * Enable XON/XOFF flow control on input.
1026 * Receiver compares XON1, XOFF1.
1027 */
1028 if (termios->c_iflag & IXON)
1029 up->efr |= OMAP_UART_SW_RX;
1030
1031 /*
1032 * IXOFF Flag:
1033 * Enable XON/XOFF flow control on output.
1034 * Transmit XON1, XOFF1
1035 */
1036 if (termios->c_iflag & IXOFF)
1037 up->efr |= OMAP_UART_SW_TX;
1038
1039 /*
1040 * IXANY Flag:
1041 * Enable any character to restart output.
1042 * Operation resumes after receiving any
1043 * character after recognition of the XOFF character
1044 */
1045 if (termios->c_iflag & IXANY)
1046 up->mcr |= UART_MCR_XONANY;
1047 else
1048 up->mcr &= ~UART_MCR_XONANY;
1049 }
1050 serial_out(up, UART_MCR, up->mcr);
1051 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1052 serial_out(up, UART_EFR, up->efr);
1053 serial_out(up, UART_LCR, up->lcr);
1054
1055 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1056
1057 spin_unlock_irqrestore(&up->port.lock, flags);
1058 pm_runtime_mark_last_busy(up->dev);
1059 pm_runtime_put_autosuspend(up->dev);
1060 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1061 }
1062
1063 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
1064 {
1065 struct uart_omap_port *up = to_uart_omap_port(port);
1066
1067 serial_omap_enable_wakeup(up, state);
1068
1069 return 0;
1070 }
1071
1072 static void
1073 serial_omap_pm(struct uart_port *port, unsigned int state,
1074 unsigned int oldstate)
1075 {
1076 struct uart_omap_port *up = to_uart_omap_port(port);
1077 unsigned char efr;
1078
1079 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1080
1081 pm_runtime_get_sync(up->dev);
1082 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1083 efr = serial_in(up, UART_EFR);
1084 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1085 serial_out(up, UART_LCR, 0);
1086
1087 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1088 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1089 serial_out(up, UART_EFR, efr);
1090 serial_out(up, UART_LCR, 0);
1091
1092 if (!device_may_wakeup(up->dev)) {
1093 if (!state)
1094 pm_runtime_forbid(up->dev);
1095 else
1096 pm_runtime_allow(up->dev);
1097 }
1098
1099 pm_runtime_mark_last_busy(up->dev);
1100 pm_runtime_put_autosuspend(up->dev);
1101 }
1102
1103 static void serial_omap_release_port(struct uart_port *port)
1104 {
1105 dev_dbg(port->dev, "serial_omap_release_port+\n");
1106 }
1107
1108 static int serial_omap_request_port(struct uart_port *port)
1109 {
1110 dev_dbg(port->dev, "serial_omap_request_port+\n");
1111 return 0;
1112 }
1113
1114 static void serial_omap_config_port(struct uart_port *port, int flags)
1115 {
1116 struct uart_omap_port *up = to_uart_omap_port(port);
1117
1118 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1119 up->port.line);
1120 up->port.type = PORT_OMAP;
1121 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1122 }
1123
1124 static int
1125 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1126 {
1127 /* we don't want the core code to modify any port params */
1128 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1129 return -EINVAL;
1130 }
1131
1132 static const char *
1133 serial_omap_type(struct uart_port *port)
1134 {
1135 struct uart_omap_port *up = to_uart_omap_port(port);
1136
1137 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1138 return up->name;
1139 }
1140
1141 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1142
1143 static inline void wait_for_xmitr(struct uart_omap_port *up)
1144 {
1145 unsigned int status, tmout = 10000;
1146
1147 /* Wait up to 10ms for the character(s) to be sent. */
1148 do {
1149 status = serial_in(up, UART_LSR);
1150
1151 if (status & UART_LSR_BI)
1152 up->lsr_break_flag = UART_LSR_BI;
1153
1154 if (--tmout == 0)
1155 break;
1156 udelay(1);
1157 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1158
1159 /* Wait up to 1s for flow control if necessary */
1160 if (up->port.flags & UPF_CONS_FLOW) {
1161 tmout = 1000000;
1162 for (tmout = 1000000; tmout; tmout--) {
1163 unsigned int msr = serial_in(up, UART_MSR);
1164
1165 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1166 if (msr & UART_MSR_CTS)
1167 break;
1168
1169 udelay(1);
1170 }
1171 }
1172 }
1173
1174 #ifdef CONFIG_CONSOLE_POLL
1175
1176 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1177 {
1178 struct uart_omap_port *up = to_uart_omap_port(port);
1179
1180 pm_runtime_get_sync(up->dev);
1181 wait_for_xmitr(up);
1182 serial_out(up, UART_TX, ch);
1183 pm_runtime_mark_last_busy(up->dev);
1184 pm_runtime_put_autosuspend(up->dev);
1185 }
1186
1187 static int serial_omap_poll_get_char(struct uart_port *port)
1188 {
1189 struct uart_omap_port *up = to_uart_omap_port(port);
1190 unsigned int status;
1191
1192 pm_runtime_get_sync(up->dev);
1193 status = serial_in(up, UART_LSR);
1194 if (!(status & UART_LSR_DR)) {
1195 status = NO_POLL_CHAR;
1196 goto out;
1197 }
1198
1199 status = serial_in(up, UART_RX);
1200
1201 out:
1202 pm_runtime_mark_last_busy(up->dev);
1203 pm_runtime_put_autosuspend(up->dev);
1204
1205 return status;
1206 }
1207
1208 #endif /* CONFIG_CONSOLE_POLL */
1209
1210 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1211
1212 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1213
1214 static struct uart_driver serial_omap_reg;
1215
1216 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1217 {
1218 struct uart_omap_port *up = to_uart_omap_port(port);
1219
1220 wait_for_xmitr(up);
1221 serial_out(up, UART_TX, ch);
1222 }
1223
1224 static void
1225 serial_omap_console_write(struct console *co, const char *s,
1226 unsigned int count)
1227 {
1228 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1229 unsigned long flags;
1230 unsigned int ier;
1231 int locked = 1;
1232
1233 pm_runtime_get_sync(up->dev);
1234
1235 local_irq_save(flags);
1236 if (up->port.sysrq)
1237 locked = 0;
1238 else if (oops_in_progress)
1239 locked = spin_trylock(&up->port.lock);
1240 else
1241 spin_lock(&up->port.lock);
1242
1243 /*
1244 * First save the IER then disable the interrupts
1245 */
1246 ier = serial_in(up, UART_IER);
1247 serial_out(up, UART_IER, 0);
1248
1249 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1250
1251 /*
1252 * Finally, wait for transmitter to become empty
1253 * and restore the IER
1254 */
1255 wait_for_xmitr(up);
1256 serial_out(up, UART_IER, ier);
1257 /*
1258 * The receive handling will happen properly because the
1259 * receive ready bit will still be set; it is not cleared
1260 * on read. However, modem control will not, we must
1261 * call it if we have saved something in the saved flags
1262 * while processing with interrupts off.
1263 */
1264 if (up->msr_saved_flags)
1265 check_modem_status(up);
1266
1267 pm_runtime_mark_last_busy(up->dev);
1268 pm_runtime_put_autosuspend(up->dev);
1269 if (locked)
1270 spin_unlock(&up->port.lock);
1271 local_irq_restore(flags);
1272 }
1273
1274 static int __init
1275 serial_omap_console_setup(struct console *co, char *options)
1276 {
1277 struct uart_omap_port *up;
1278 int baud = 115200;
1279 int bits = 8;
1280 int parity = 'n';
1281 int flow = 'n';
1282
1283 if (serial_omap_console_ports[co->index] == NULL)
1284 return -ENODEV;
1285 up = serial_omap_console_ports[co->index];
1286
1287 if (options)
1288 uart_parse_options(options, &baud, &parity, &bits, &flow);
1289
1290 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1291 }
1292
1293 static struct console serial_omap_console = {
1294 .name = OMAP_SERIAL_NAME,
1295 .write = serial_omap_console_write,
1296 .device = uart_console_device,
1297 .setup = serial_omap_console_setup,
1298 .flags = CON_PRINTBUFFER,
1299 .index = -1,
1300 .data = &serial_omap_reg,
1301 };
1302
1303 static void serial_omap_add_console_port(struct uart_omap_port *up)
1304 {
1305 serial_omap_console_ports[up->port.line] = up;
1306 }
1307
1308 #define OMAP_CONSOLE (&serial_omap_console)
1309
1310 #else
1311
1312 #define OMAP_CONSOLE NULL
1313
1314 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1315 {}
1316
1317 #endif
1318
1319 /* Enable or disable the rs485 support */
1320 static void
1321 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1322 {
1323 struct uart_omap_port *up = to_uart_omap_port(port);
1324 unsigned long flags;
1325 unsigned int mode;
1326 int val;
1327
1328 pm_runtime_get_sync(up->dev);
1329 spin_lock_irqsave(&up->port.lock, flags);
1330
1331 /* Disable interrupts from this port */
1332 mode = up->ier;
1333 up->ier = 0;
1334 serial_out(up, UART_IER, 0);
1335
1336 /* store new config */
1337 up->rs485 = *rs485conf;
1338
1339 /*
1340 * Just as a precaution, only allow rs485
1341 * to be enabled if the gpio pin is valid
1342 */
1343 if (gpio_is_valid(up->rts_gpio)) {
1344 /* enable / disable rts */
1345 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1346 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1347 val = (up->rs485.flags & val) ? 1 : 0;
1348 gpio_set_value(up->rts_gpio, val);
1349 } else
1350 up->rs485.flags &= ~SER_RS485_ENABLED;
1351
1352 /* Enable interrupts */
1353 up->ier = mode;
1354 serial_out(up, UART_IER, up->ier);
1355
1356 spin_unlock_irqrestore(&up->port.lock, flags);
1357 pm_runtime_mark_last_busy(up->dev);
1358 pm_runtime_put_autosuspend(up->dev);
1359 }
1360
1361 static int
1362 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1363 {
1364 struct serial_rs485 rs485conf;
1365
1366 switch (cmd) {
1367 case TIOCSRS485:
1368 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1369 sizeof(rs485conf)))
1370 return -EFAULT;
1371
1372 serial_omap_config_rs485(port, &rs485conf);
1373 break;
1374
1375 case TIOCGRS485:
1376 if (copy_to_user((struct serial_rs485 *) arg,
1377 &(to_uart_omap_port(port)->rs485),
1378 sizeof(rs485conf)))
1379 return -EFAULT;
1380 break;
1381
1382 default:
1383 return -ENOIOCTLCMD;
1384 }
1385 return 0;
1386 }
1387
1388
1389 static struct uart_ops serial_omap_pops = {
1390 .tx_empty = serial_omap_tx_empty,
1391 .set_mctrl = serial_omap_set_mctrl,
1392 .get_mctrl = serial_omap_get_mctrl,
1393 .stop_tx = serial_omap_stop_tx,
1394 .start_tx = serial_omap_start_tx,
1395 .throttle = serial_omap_throttle,
1396 .unthrottle = serial_omap_unthrottle,
1397 .stop_rx = serial_omap_stop_rx,
1398 .enable_ms = serial_omap_enable_ms,
1399 .break_ctl = serial_omap_break_ctl,
1400 .startup = serial_omap_startup,
1401 .shutdown = serial_omap_shutdown,
1402 .set_termios = serial_omap_set_termios,
1403 .pm = serial_omap_pm,
1404 .set_wake = serial_omap_set_wake,
1405 .type = serial_omap_type,
1406 .release_port = serial_omap_release_port,
1407 .request_port = serial_omap_request_port,
1408 .config_port = serial_omap_config_port,
1409 .verify_port = serial_omap_verify_port,
1410 .ioctl = serial_omap_ioctl,
1411 #ifdef CONFIG_CONSOLE_POLL
1412 .poll_put_char = serial_omap_poll_put_char,
1413 .poll_get_char = serial_omap_poll_get_char,
1414 #endif
1415 };
1416
1417 static struct uart_driver serial_omap_reg = {
1418 .owner = THIS_MODULE,
1419 .driver_name = "OMAP-SERIAL",
1420 .dev_name = OMAP_SERIAL_NAME,
1421 .nr = OMAP_MAX_HSUART_PORTS,
1422 .cons = OMAP_CONSOLE,
1423 };
1424
1425 #ifdef CONFIG_PM_SLEEP
1426 static int serial_omap_prepare(struct device *dev)
1427 {
1428 struct uart_omap_port *up = dev_get_drvdata(dev);
1429
1430 up->is_suspending = true;
1431
1432 return 0;
1433 }
1434
1435 static void serial_omap_complete(struct device *dev)
1436 {
1437 struct uart_omap_port *up = dev_get_drvdata(dev);
1438
1439 up->is_suspending = false;
1440 }
1441
1442 static int serial_omap_suspend(struct device *dev)
1443 {
1444 struct uart_omap_port *up = dev_get_drvdata(dev);
1445
1446 uart_suspend_port(&serial_omap_reg, &up->port);
1447 flush_work(&up->qos_work);
1448
1449 return 0;
1450 }
1451
1452 static int serial_omap_resume(struct device *dev)
1453 {
1454 struct uart_omap_port *up = dev_get_drvdata(dev);
1455
1456 uart_resume_port(&serial_omap_reg, &up->port);
1457
1458 return 0;
1459 }
1460 #else
1461 #define serial_omap_prepare NULL
1462 #define serial_omap_complete NULL
1463 #endif /* CONFIG_PM_SLEEP */
1464
1465 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1466 {
1467 u32 mvr, scheme;
1468 u16 revision, major, minor;
1469
1470 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1471
1472 /* Check revision register scheme */
1473 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1474
1475 switch (scheme) {
1476 case 0: /* Legacy Scheme: OMAP2/3 */
1477 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1478 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1479 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1480 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1481 break;
1482 case 1:
1483 /* New Scheme: OMAP4+ */
1484 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1485 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1486 OMAP_UART_MVR_MAJ_SHIFT;
1487 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1488 break;
1489 default:
1490 dev_warn(up->dev,
1491 "Unknown %s revision, defaulting to highest\n",
1492 up->name);
1493 /* highest possible revision */
1494 major = 0xff;
1495 minor = 0xff;
1496 }
1497
1498 /* normalize revision for the driver */
1499 revision = UART_BUILD_REVISION(major, minor);
1500
1501 switch (revision) {
1502 case OMAP_UART_REV_46:
1503 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1504 UART_ERRATA_i291_DMA_FORCEIDLE);
1505 break;
1506 case OMAP_UART_REV_52:
1507 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1508 UART_ERRATA_i291_DMA_FORCEIDLE);
1509 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1510 break;
1511 case OMAP_UART_REV_63:
1512 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1513 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1514 break;
1515 default:
1516 break;
1517 }
1518 }
1519
1520 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1521 {
1522 struct omap_uart_port_info *omap_up_info;
1523
1524 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1525 if (!omap_up_info)
1526 return NULL; /* out of memory */
1527
1528 of_property_read_u32(dev->of_node, "clock-frequency",
1529 &omap_up_info->uartclk);
1530 return omap_up_info;
1531 }
1532
1533 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1534 struct device_node *np)
1535 {
1536 struct serial_rs485 *rs485conf = &up->rs485;
1537 u32 rs485_delay[2];
1538 enum of_gpio_flags flags;
1539 int ret;
1540
1541 rs485conf->flags = 0;
1542 up->rts_gpio = -EINVAL;
1543
1544 if (!np)
1545 return 0;
1546
1547 if (of_property_read_bool(np, "rs485-rts-active-high"))
1548 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1549 else
1550 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1551
1552 /* check for tx enable gpio */
1553 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1554 if (gpio_is_valid(up->rts_gpio)) {
1555 ret = gpio_request(up->rts_gpio, "omap-serial");
1556 if (ret < 0)
1557 return ret;
1558 ret = gpio_direction_output(up->rts_gpio,
1559 flags & SER_RS485_RTS_AFTER_SEND);
1560 if (ret < 0)
1561 return ret;
1562 } else
1563 up->rts_gpio = -EINVAL;
1564
1565 if (of_property_read_u32_array(np, "rs485-rts-delay",
1566 rs485_delay, 2) == 0) {
1567 rs485conf->delay_rts_before_send = rs485_delay[0];
1568 rs485conf->delay_rts_after_send = rs485_delay[1];
1569 }
1570
1571 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1572 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1573
1574 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1575 rs485conf->flags |= SER_RS485_ENABLED;
1576
1577 return 0;
1578 }
1579
1580 static int serial_omap_probe(struct platform_device *pdev)
1581 {
1582 struct uart_omap_port *up;
1583 struct resource *mem, *irq;
1584 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1585 int ret;
1586
1587 if (pdev->dev.of_node) {
1588 omap_up_info = of_get_uart_port_info(&pdev->dev);
1589 pdev->dev.platform_data = omap_up_info;
1590 }
1591
1592 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1593 if (!mem) {
1594 dev_err(&pdev->dev, "no mem resource?\n");
1595 return -ENODEV;
1596 }
1597
1598 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1599 if (!irq) {
1600 dev_err(&pdev->dev, "no irq resource?\n");
1601 return -ENODEV;
1602 }
1603
1604 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1605 pdev->dev.driver->name)) {
1606 dev_err(&pdev->dev, "memory region already claimed\n");
1607 return -EBUSY;
1608 }
1609
1610 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1611 omap_up_info->DTR_present) {
1612 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1613 if (ret < 0)
1614 return ret;
1615 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1616 omap_up_info->DTR_inverted);
1617 if (ret < 0)
1618 return ret;
1619 }
1620
1621 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1622 if (!up)
1623 return -ENOMEM;
1624
1625 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1626 omap_up_info->DTR_present) {
1627 up->DTR_gpio = omap_up_info->DTR_gpio;
1628 up->DTR_inverted = omap_up_info->DTR_inverted;
1629 } else
1630 up->DTR_gpio = -EINVAL;
1631 up->DTR_active = 0;
1632
1633 up->dev = &pdev->dev;
1634 up->port.dev = &pdev->dev;
1635 up->port.type = PORT_OMAP;
1636 up->port.iotype = UPIO_MEM;
1637 up->port.irq = irq->start;
1638
1639 up->port.regshift = 2;
1640 up->port.fifosize = 64;
1641 up->port.ops = &serial_omap_pops;
1642
1643 if (pdev->dev.of_node)
1644 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1645 else
1646 up->port.line = pdev->id;
1647
1648 if (up->port.line < 0) {
1649 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1650 up->port.line);
1651 ret = -ENODEV;
1652 goto err_port_line;
1653 }
1654
1655 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1656 if (ret < 0)
1657 goto err_rs485;
1658
1659 sprintf(up->name, "OMAP UART%d", up->port.line);
1660 up->port.mapbase = mem->start;
1661 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1662 resource_size(mem));
1663 if (!up->port.membase) {
1664 dev_err(&pdev->dev, "can't ioremap UART\n");
1665 ret = -ENOMEM;
1666 goto err_ioremap;
1667 }
1668
1669 up->port.flags = omap_up_info->flags;
1670 up->port.uartclk = omap_up_info->uartclk;
1671 if (!up->port.uartclk) {
1672 up->port.uartclk = DEFAULT_CLK_SPEED;
1673 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1674 "%d\n", DEFAULT_CLK_SPEED);
1675 }
1676
1677 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1678 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1679 pm_qos_add_request(&up->pm_qos_request,
1680 PM_QOS_CPU_DMA_LATENCY, up->latency);
1681 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1682 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1683
1684 platform_set_drvdata(pdev, up);
1685 if (omap_up_info->autosuspend_timeout == 0)
1686 omap_up_info->autosuspend_timeout = -1;
1687 device_init_wakeup(up->dev, true);
1688 pm_runtime_use_autosuspend(&pdev->dev);
1689 pm_runtime_set_autosuspend_delay(&pdev->dev,
1690 omap_up_info->autosuspend_timeout);
1691
1692 pm_runtime_irq_safe(&pdev->dev);
1693 pm_runtime_enable(&pdev->dev);
1694
1695 pm_runtime_get_sync(&pdev->dev);
1696
1697 omap_serial_fill_features_erratas(up);
1698
1699 ui[up->port.line] = up;
1700 serial_omap_add_console_port(up);
1701
1702 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1703 if (ret != 0)
1704 goto err_add_port;
1705
1706 pm_runtime_mark_last_busy(up->dev);
1707 pm_runtime_put_autosuspend(up->dev);
1708 return 0;
1709
1710 err_add_port:
1711 pm_runtime_put(&pdev->dev);
1712 pm_runtime_disable(&pdev->dev);
1713 err_ioremap:
1714 err_rs485:
1715 err_port_line:
1716 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1717 pdev->id, __func__, ret);
1718 return ret;
1719 }
1720
1721 static int serial_omap_remove(struct platform_device *dev)
1722 {
1723 struct uart_omap_port *up = platform_get_drvdata(dev);
1724
1725 pm_runtime_put_sync(up->dev);
1726 pm_runtime_disable(up->dev);
1727 uart_remove_one_port(&serial_omap_reg, &up->port);
1728 pm_qos_remove_request(&up->pm_qos_request);
1729
1730 return 0;
1731 }
1732
1733 /*
1734 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1735 * The access to uart register after MDR1 Access
1736 * causes UART to corrupt data.
1737 *
1738 * Need a delay =
1739 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1740 * give 10 times as much
1741 */
1742 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1743 {
1744 u8 timeout = 255;
1745
1746 serial_out(up, UART_OMAP_MDR1, mdr1);
1747 udelay(2);
1748 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1749 UART_FCR_CLEAR_RCVR);
1750 /*
1751 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1752 * TX_FIFO_E bit is 1.
1753 */
1754 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1755 (UART_LSR_THRE | UART_LSR_DR))) {
1756 timeout--;
1757 if (!timeout) {
1758 /* Should *never* happen. we warn and carry on */
1759 dev_crit(up->dev, "Errata i202: timedout %x\n",
1760 serial_in(up, UART_LSR));
1761 break;
1762 }
1763 udelay(1);
1764 }
1765 }
1766
1767 #ifdef CONFIG_PM_RUNTIME
1768 static void serial_omap_restore_context(struct uart_omap_port *up)
1769 {
1770 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1771 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1772 else
1773 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1774
1775 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1776 serial_out(up, UART_EFR, UART_EFR_ECB);
1777 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1778 serial_out(up, UART_IER, 0x0);
1779 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1780 serial_out(up, UART_DLL, up->dll);
1781 serial_out(up, UART_DLM, up->dlh);
1782 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1783 serial_out(up, UART_IER, up->ier);
1784 serial_out(up, UART_FCR, up->fcr);
1785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1786 serial_out(up, UART_MCR, up->mcr);
1787 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1788 serial_out(up, UART_OMAP_SCR, up->scr);
1789 serial_out(up, UART_EFR, up->efr);
1790 serial_out(up, UART_LCR, up->lcr);
1791 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1792 serial_omap_mdr1_errataset(up, up->mdr1);
1793 else
1794 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1795 serial_out(up, UART_OMAP_WER, up->wer);
1796 }
1797
1798 static int serial_omap_runtime_suspend(struct device *dev)
1799 {
1800 struct uart_omap_port *up = dev_get_drvdata(dev);
1801
1802 if (!up)
1803 return -EINVAL;
1804
1805 /*
1806 * When using 'no_console_suspend', the console UART must not be
1807 * suspended. Since driver suspend is managed by runtime suspend,
1808 * preventing runtime suspend (by returning error) will keep device
1809 * active during suspend.
1810 */
1811 if (up->is_suspending && !console_suspend_enabled &&
1812 uart_console(&up->port))
1813 return -EBUSY;
1814
1815 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1816
1817 if (device_may_wakeup(dev)) {
1818 if (!up->wakeups_enabled) {
1819 serial_omap_enable_wakeup(up, true);
1820 up->wakeups_enabled = true;
1821 }
1822 } else {
1823 if (up->wakeups_enabled) {
1824 serial_omap_enable_wakeup(up, false);
1825 up->wakeups_enabled = false;
1826 }
1827 }
1828
1829 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1830 schedule_work(&up->qos_work);
1831
1832 return 0;
1833 }
1834
1835 static int serial_omap_runtime_resume(struct device *dev)
1836 {
1837 struct uart_omap_port *up = dev_get_drvdata(dev);
1838
1839 int loss_cnt = serial_omap_get_context_loss_count(up);
1840
1841 if (loss_cnt < 0) {
1842 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1843 loss_cnt);
1844 serial_omap_restore_context(up);
1845 } else if (up->context_loss_cnt != loss_cnt) {
1846 serial_omap_restore_context(up);
1847 }
1848 up->latency = up->calc_latency;
1849 schedule_work(&up->qos_work);
1850
1851 return 0;
1852 }
1853 #endif
1854
1855 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1856 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1857 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1858 serial_omap_runtime_resume, NULL)
1859 .prepare = serial_omap_prepare,
1860 .complete = serial_omap_complete,
1861 };
1862
1863 #if defined(CONFIG_OF)
1864 static const struct of_device_id omap_serial_of_match[] = {
1865 { .compatible = "ti,omap2-uart" },
1866 { .compatible = "ti,omap3-uart" },
1867 { .compatible = "ti,omap4-uart" },
1868 {},
1869 };
1870 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1871 #endif
1872
1873 static struct platform_driver serial_omap_driver = {
1874 .probe = serial_omap_probe,
1875 .remove = serial_omap_remove,
1876 .driver = {
1877 .name = DRIVER_NAME,
1878 .pm = &serial_omap_dev_pm_ops,
1879 .of_match_table = of_match_ptr(omap_serial_of_match),
1880 },
1881 };
1882
1883 static int __init serial_omap_init(void)
1884 {
1885 int ret;
1886
1887 ret = uart_register_driver(&serial_omap_reg);
1888 if (ret != 0)
1889 return ret;
1890 ret = platform_driver_register(&serial_omap_driver);
1891 if (ret != 0)
1892 uart_unregister_driver(&serial_omap_reg);
1893 return ret;
1894 }
1895
1896 static void __exit serial_omap_exit(void)
1897 {
1898 platform_driver_unregister(&serial_omap_driver);
1899 uart_unregister_driver(&serial_omap_reg);
1900 }
1901
1902 module_init(serial_omap_init);
1903 module_exit(serial_omap_exit);
1904
1905 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1906 MODULE_LICENSE("GPL");
1907 MODULE_AUTHOR("Texas Instruments Inc");
Linux with added FPC-III support