?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blobf3dfa19a1cb86eb4c8dd0b47ea8f23b8bab5f0e8
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46 #include <linux/of.h>
47
48 #include <asm/irq.h>
49
50 #ifdef CONFIG_SAMSUNG_CLOCK
51 #include <plat/clock.h>
52 #endif
53
54 #include "samsung.h"
55
56 /* UART name and device definitions */
57
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
61
62 /* macros to change one thing to another */
63
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
66
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
69
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71 {
72 return container_of(port, struct s3c24xx_uart_port, port);
73 }
74
75 /* translate a port to the device name */
76
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78 {
79 return to_platform_device(port->dev)->name;
80 }
81
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83 {
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
85 }
86
87 /*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93 {
94 return to_ourport(port)->info->type == PORT_S3C6400;
95 }
96
97 static void s3c24xx_serial_rx_enable(struct uart_port *port)
98 {
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118 }
119
120 static void s3c24xx_serial_rx_disable(struct uart_port *port)
121 {
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133 }
134
135 static void s3c24xx_serial_stop_tx(struct uart_port *port)
136 {
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149 }
150
151 static void s3c24xx_serial_start_tx(struct uart_port *port)
152 {
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
165 }
166 }
167
168 static void s3c24xx_serial_stop_rx(struct uart_port *port)
169 {
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
180 }
181 }
182
183 static void s3c24xx_serial_enable_ms(struct uart_port *port)
184 {
185 }
186
187 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188 {
189 return to_ourport(port)->info;
190 }
191
192 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193 {
194 struct s3c24xx_uart_port *ourport;
195
196 if (port->dev == NULL)
197 return NULL;
198
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
201 }
202
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205 {
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212 }
213
214
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
217
218 static irqreturn_t
219 s3c24xx_serial_rx_chars(int irq, void *dev_id)
220 {
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
224 unsigned long flags;
225 int max_count = 64;
226
227 spin_lock_irqsave(&port->lock, flags);
228
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 spin_unlock_irqrestore(&port->lock,
253 flags);
254 goto out;
255 }
256 continue;
257 }
258 }
259
260 /* insert the character into the buffer */
261
262 flag = TTY_NORMAL;
263 port->icount.rx++;
264
265 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
266 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
267 ch, uerstat);
268
269 /* check for break */
270 if (uerstat & S3C2410_UERSTAT_BREAK) {
271 dbg("break!\n");
272 port->icount.brk++;
273 if (uart_handle_break(port))
274 goto ignore_char;
275 }
276
277 if (uerstat & S3C2410_UERSTAT_FRAME)
278 port->icount.frame++;
279 if (uerstat & S3C2410_UERSTAT_OVERRUN)
280 port->icount.overrun++;
281
282 uerstat &= port->read_status_mask;
283
284 if (uerstat & S3C2410_UERSTAT_BREAK)
285 flag = TTY_BREAK;
286 else if (uerstat & S3C2410_UERSTAT_PARITY)
287 flag = TTY_PARITY;
288 else if (uerstat & (S3C2410_UERSTAT_FRAME |
289 S3C2410_UERSTAT_OVERRUN))
290 flag = TTY_FRAME;
291 }
292
293 if (uart_handle_sysrq_char(port, ch))
294 goto ignore_char;
295
296 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
297 ch, flag);
298
299 ignore_char:
300 continue;
301 }
302
303 spin_unlock_irqrestore(&port->lock, flags);
304 tty_flip_buffer_push(&port->state->port);
305
306 out:
307 return IRQ_HANDLED;
308 }
309
310 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
311 {
312 struct s3c24xx_uart_port *ourport = id;
313 struct uart_port *port = &ourport->port;
314 struct circ_buf *xmit = &port->state->xmit;
315 unsigned long flags;
316 int count = 256;
317
318 spin_lock_irqsave(&port->lock, flags);
319
320 if (port->x_char) {
321 wr_regb(port, S3C2410_UTXH, port->x_char);
322 port->icount.tx++;
323 port->x_char = 0;
324 goto out;
325 }
326
327 /* if there isn't anything more to transmit, or the uart is now
328 * stopped, disable the uart and exit
329 */
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
332 s3c24xx_serial_stop_tx(port);
333 goto out;
334 }
335
336 /* try and drain the buffer... */
337
338 while (!uart_circ_empty(xmit) && count-- > 0) {
339 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
340 break;
341
342 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344 port->icount.tx++;
345 }
346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
348 spin_unlock(&port->lock);
349 uart_write_wakeup(port);
350 spin_lock(&port->lock);
351 }
352
353 if (uart_circ_empty(xmit))
354 s3c24xx_serial_stop_tx(port);
355
356 out:
357 spin_unlock_irqrestore(&port->lock, flags);
358 return IRQ_HANDLED;
359 }
360
361 /* interrupt handler for s3c64xx and later SoC's.*/
362 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
363 {
364 struct s3c24xx_uart_port *ourport = id;
365 struct uart_port *port = &ourport->port;
366 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
367 irqreturn_t ret = IRQ_HANDLED;
368
369 if (pend & S3C64XX_UINTM_RXD_MSK) {
370 ret = s3c24xx_serial_rx_chars(irq, id);
371 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
372 }
373 if (pend & S3C64XX_UINTM_TXD_MSK) {
374 ret = s3c24xx_serial_tx_chars(irq, id);
375 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
376 }
377 return ret;
378 }
379
380 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
381 {
382 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
383 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
384 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
385
386 if (ufcon & S3C2410_UFCON_FIFOMODE) {
387 if ((ufstat & info->tx_fifomask) != 0 ||
388 (ufstat & info->tx_fifofull))
389 return 0;
390
391 return 1;
392 }
393
394 return s3c24xx_serial_txempty_nofifo(port);
395 }
396
397 /* no modem control lines */
398 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
399 {
400 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
401
402 if (umstat & S3C2410_UMSTAT_CTS)
403 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
404 else
405 return TIOCM_CAR | TIOCM_DSR;
406 }
407
408 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
409 {
410 /* todo - possibly remove AFC and do manual CTS */
411 }
412
413 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
414 {
415 unsigned long flags;
416 unsigned int ucon;
417
418 spin_lock_irqsave(&port->lock, flags);
419
420 ucon = rd_regl(port, S3C2410_UCON);
421
422 if (break_state)
423 ucon |= S3C2410_UCON_SBREAK;
424 else
425 ucon &= ~S3C2410_UCON_SBREAK;
426
427 wr_regl(port, S3C2410_UCON, ucon);
428
429 spin_unlock_irqrestore(&port->lock, flags);
430 }
431
432 static void s3c24xx_serial_shutdown(struct uart_port *port)
433 {
434 struct s3c24xx_uart_port *ourport = to_ourport(port);
435
436 if (ourport->tx_claimed) {
437 if (!s3c24xx_serial_has_interrupt_mask(port))
438 free_irq(ourport->tx_irq, ourport);
439 tx_enabled(port) = 0;
440 ourport->tx_claimed = 0;
441 }
442
443 if (ourport->rx_claimed) {
444 if (!s3c24xx_serial_has_interrupt_mask(port))
445 free_irq(ourport->rx_irq, ourport);
446 ourport->rx_claimed = 0;
447 rx_enabled(port) = 0;
448 }
449
450 /* Clear pending interrupts and mask all interrupts */
451 if (s3c24xx_serial_has_interrupt_mask(port)) {
452 free_irq(port->irq, ourport);
453
454 wr_regl(port, S3C64XX_UINTP, 0xf);
455 wr_regl(port, S3C64XX_UINTM, 0xf);
456 }
457 }
458
459 static int s3c24xx_serial_startup(struct uart_port *port)
460 {
461 struct s3c24xx_uart_port *ourport = to_ourport(port);
462 int ret;
463
464 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
465 port->mapbase, port->membase);
466
467 rx_enabled(port) = 1;
468
469 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
470 s3c24xx_serial_portname(port), ourport);
471
472 if (ret != 0) {
473 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
474 return ret;
475 }
476
477 ourport->rx_claimed = 1;
478
479 dbg("requesting tx irq...\n");
480
481 tx_enabled(port) = 1;
482
483 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
484 s3c24xx_serial_portname(port), ourport);
485
486 if (ret) {
487 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
488 goto err;
489 }
490
491 ourport->tx_claimed = 1;
492
493 dbg("s3c24xx_serial_startup ok\n");
494
495 /* the port reset code should have done the correct
496 * register setup for the port controls */
497
498 return ret;
499
500 err:
501 s3c24xx_serial_shutdown(port);
502 return ret;
503 }
504
505 static int s3c64xx_serial_startup(struct uart_port *port)
506 {
507 struct s3c24xx_uart_port *ourport = to_ourport(port);
508 int ret;
509
510 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
511 port->mapbase, port->membase);
512
513 wr_regl(port, S3C64XX_UINTM, 0xf);
514
515 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
516 s3c24xx_serial_portname(port), ourport);
517 if (ret) {
518 dev_err(port->dev, "cannot get irq %d\n", port->irq);
519 return ret;
520 }
521
522 /* For compatibility with s3c24xx Soc's */
523 rx_enabled(port) = 1;
524 ourport->rx_claimed = 1;
525 tx_enabled(port) = 0;
526 ourport->tx_claimed = 1;
527
528 /* Enable Rx Interrupt */
529 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
530 dbg("s3c64xx_serial_startup ok\n");
531 return ret;
532 }
533
534 /* power power management control */
535
536 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
537 unsigned int old)
538 {
539 struct s3c24xx_uart_port *ourport = to_ourport(port);
540
541 ourport->pm_level = level;
542
543 switch (level) {
544 case 3:
545 if (!IS_ERR(ourport->baudclk))
546 clk_disable_unprepare(ourport->baudclk);
547
548 clk_disable_unprepare(ourport->clk);
549 break;
550
551 case 0:
552 clk_prepare_enable(ourport->clk);
553
554 if (!IS_ERR(ourport->baudclk))
555 clk_prepare_enable(ourport->baudclk);
556
557 break;
558 default:
559 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
560 }
561 }
562
563 /* baud rate calculation
564 *
565 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
566 * of different sources, including the peripheral clock ("pclk") and an
567 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
568 * with a programmable extra divisor.
569 *
570 * The following code goes through the clock sources, and calculates the
571 * baud clocks (and the resultant actual baud rates) and then tries to
572 * pick the closest one and select that.
573 *
574 */
575
576 #define MAX_CLK_NAME_LENGTH 15
577
578 static inline int s3c24xx_serial_getsource(struct uart_port *port)
579 {
580 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
581 unsigned int ucon;
582
583 if (info->num_clks == 1)
584 return 0;
585
586 ucon = rd_regl(port, S3C2410_UCON);
587 ucon &= info->clksel_mask;
588 return ucon >> info->clksel_shift;
589 }
590
591 static void s3c24xx_serial_setsource(struct uart_port *port,
592 unsigned int clk_sel)
593 {
594 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
595 unsigned int ucon;
596
597 if (info->num_clks == 1)
598 return;
599
600 ucon = rd_regl(port, S3C2410_UCON);
601 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
602 return;
603
604 ucon &= ~info->clksel_mask;
605 ucon |= clk_sel << info->clksel_shift;
606 wr_regl(port, S3C2410_UCON, ucon);
607 }
608
609 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
610 unsigned int req_baud, struct clk **best_clk,
611 unsigned int *clk_num)
612 {
613 struct s3c24xx_uart_info *info = ourport->info;
614 struct clk *clk;
615 unsigned long rate;
616 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
617 char clkname[MAX_CLK_NAME_LENGTH];
618 int calc_deviation, deviation = (1 << 30) - 1;
619
620 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
621 ourport->info->def_clk_sel;
622 for (cnt = 0; cnt < info->num_clks; cnt++) {
623 if (!(clk_sel & (1 << cnt)))
624 continue;
625
626 sprintf(clkname, "clk_uart_baud%d", cnt);
627 clk = clk_get(ourport->port.dev, clkname);
628 if (IS_ERR(clk))
629 continue;
630
631 rate = clk_get_rate(clk);
632 if (!rate)
633 continue;
634
635 if (ourport->info->has_divslot) {
636 unsigned long div = rate / req_baud;
637
638 /* The UDIVSLOT register on the newer UARTs allows us to
639 * get a divisor adjustment of 1/16th on the baud clock.
640 *
641 * We don't keep the UDIVSLOT value (the 16ths we
642 * calculated by not multiplying the baud by 16) as it
643 * is easy enough to recalculate.
644 */
645
646 quot = div / 16;
647 baud = rate / div;
648 } else {
649 quot = (rate + (8 * req_baud)) / (16 * req_baud);
650 baud = rate / (quot * 16);
651 }
652 quot--;
653
654 calc_deviation = req_baud - baud;
655 if (calc_deviation < 0)
656 calc_deviation = -calc_deviation;
657
658 if (calc_deviation < deviation) {
659 *best_clk = clk;
660 best_quot = quot;
661 *clk_num = cnt;
662 deviation = calc_deviation;
663 }
664 }
665
666 return best_quot;
667 }
668
669 /* udivslot_table[]
670 *
671 * This table takes the fractional value of the baud divisor and gives
672 * the recommended setting for the UDIVSLOT register.
673 */
674 static u16 udivslot_table[16] = {
675 [0] = 0x0000,
676 [1] = 0x0080,
677 [2] = 0x0808,
678 [3] = 0x0888,
679 [4] = 0x2222,
680 [5] = 0x4924,
681 [6] = 0x4A52,
682 [7] = 0x54AA,
683 [8] = 0x5555,
684 [9] = 0xD555,
685 [10] = 0xD5D5,
686 [11] = 0xDDD5,
687 [12] = 0xDDDD,
688 [13] = 0xDFDD,
689 [14] = 0xDFDF,
690 [15] = 0xFFDF,
691 };
692
693 static void s3c24xx_serial_set_termios(struct uart_port *port,
694 struct ktermios *termios,
695 struct ktermios *old)
696 {
697 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
698 struct s3c24xx_uart_port *ourport = to_ourport(port);
699 struct clk *clk = ERR_PTR(-EINVAL);
700 unsigned long flags;
701 unsigned int baud, quot, clk_sel = 0;
702 unsigned int ulcon;
703 unsigned int umcon;
704 unsigned int udivslot = 0;
705
706 /*
707 * We don't support modem control lines.
708 */
709 termios->c_cflag &= ~(HUPCL | CMSPAR);
710 termios->c_cflag |= CLOCAL;
711
712 /*
713 * Ask the core to calculate the divisor for us.
714 */
715
716 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
717 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
718 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
719 quot = port->custom_divisor;
720 if (IS_ERR(clk))
721 return;
722
723 /* check to see if we need to change clock source */
724
725 if (ourport->baudclk != clk) {
726 s3c24xx_serial_setsource(port, clk_sel);
727
728 if (!IS_ERR(ourport->baudclk)) {
729 clk_disable_unprepare(ourport->baudclk);
730 ourport->baudclk = ERR_PTR(-EINVAL);
731 }
732
733 clk_prepare_enable(clk);
734
735 ourport->baudclk = clk;
736 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
737 }
738
739 if (ourport->info->has_divslot) {
740 unsigned int div = ourport->baudclk_rate / baud;
741
742 if (cfg->has_fracval) {
743 udivslot = (div & 15);
744 dbg("fracval = %04x\n", udivslot);
745 } else {
746 udivslot = udivslot_table[div & 15];
747 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
748 }
749 }
750
751 switch (termios->c_cflag & CSIZE) {
752 case CS5:
753 dbg("config: 5bits/char\n");
754 ulcon = S3C2410_LCON_CS5;
755 break;
756 case CS6:
757 dbg("config: 6bits/char\n");
758 ulcon = S3C2410_LCON_CS6;
759 break;
760 case CS7:
761 dbg("config: 7bits/char\n");
762 ulcon = S3C2410_LCON_CS7;
763 break;
764 case CS8:
765 default:
766 dbg("config: 8bits/char\n");
767 ulcon = S3C2410_LCON_CS8;
768 break;
769 }
770
771 /* preserve original lcon IR settings */
772 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
773
774 if (termios->c_cflag & CSTOPB)
775 ulcon |= S3C2410_LCON_STOPB;
776
777 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
778
779 if (termios->c_cflag & PARENB) {
780 if (termios->c_cflag & PARODD)
781 ulcon |= S3C2410_LCON_PODD;
782 else
783 ulcon |= S3C2410_LCON_PEVEN;
784 } else {
785 ulcon |= S3C2410_LCON_PNONE;
786 }
787
788 spin_lock_irqsave(&port->lock, flags);
789
790 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
791 ulcon, quot, udivslot);
792
793 wr_regl(port, S3C2410_ULCON, ulcon);
794 wr_regl(port, S3C2410_UBRDIV, quot);
795 wr_regl(port, S3C2410_UMCON, umcon);
796
797 if (ourport->info->has_divslot)
798 wr_regl(port, S3C2443_DIVSLOT, udivslot);
799
800 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
801 rd_regl(port, S3C2410_ULCON),
802 rd_regl(port, S3C2410_UCON),
803 rd_regl(port, S3C2410_UFCON));
804
805 /*
806 * Update the per-port timeout.
807 */
808 uart_update_timeout(port, termios->c_cflag, baud);
809
810 /*
811 * Which character status flags are we interested in?
812 */
813 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
814 if (termios->c_iflag & INPCK)
815 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
816
817 /*
818 * Which character status flags should we ignore?
819 */
820 port->ignore_status_mask = 0;
821 if (termios->c_iflag & IGNPAR)
822 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
823 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
824 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
825
826 /*
827 * Ignore all characters if CREAD is not set.
828 */
829 if ((termios->c_cflag & CREAD) == 0)
830 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
831
832 spin_unlock_irqrestore(&port->lock, flags);
833 }
834
835 static const char *s3c24xx_serial_type(struct uart_port *port)
836 {
837 switch (port->type) {
838 case PORT_S3C2410:
839 return "S3C2410";
840 case PORT_S3C2440:
841 return "S3C2440";
842 case PORT_S3C2412:
843 return "S3C2412";
844 case PORT_S3C6400:
845 return "S3C6400/10";
846 default:
847 return NULL;
848 }
849 }
850
851 #define MAP_SIZE (0x100)
852
853 static void s3c24xx_serial_release_port(struct uart_port *port)
854 {
855 release_mem_region(port->mapbase, MAP_SIZE);
856 }
857
858 static int s3c24xx_serial_request_port(struct uart_port *port)
859 {
860 const char *name = s3c24xx_serial_portname(port);
861 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
862 }
863
864 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
865 {
866 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
867
868 if (flags & UART_CONFIG_TYPE &&
869 s3c24xx_serial_request_port(port) == 0)
870 port->type = info->type;
871 }
872
873 /*
874 * verify the new serial_struct (for TIOCSSERIAL).
875 */
876 static int
877 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
878 {
879 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
880
881 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
882 return -EINVAL;
883
884 return 0;
885 }
886
887
888 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
889
890 static struct console s3c24xx_serial_console;
891
892 static int __init s3c24xx_serial_console_init(void)
893 {
894 register_console(&s3c24xx_serial_console);
895 return 0;
896 }
897 console_initcall(s3c24xx_serial_console_init);
898
899 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
900 #else
901 #define S3C24XX_SERIAL_CONSOLE NULL
902 #endif
903
904 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
905 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
906 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
907 unsigned char c);
908 #endif
909
910 static struct uart_ops s3c24xx_serial_ops = {
911 .pm = s3c24xx_serial_pm,
912 .tx_empty = s3c24xx_serial_tx_empty,
913 .get_mctrl = s3c24xx_serial_get_mctrl,
914 .set_mctrl = s3c24xx_serial_set_mctrl,
915 .stop_tx = s3c24xx_serial_stop_tx,
916 .start_tx = s3c24xx_serial_start_tx,
917 .stop_rx = s3c24xx_serial_stop_rx,
918 .enable_ms = s3c24xx_serial_enable_ms,
919 .break_ctl = s3c24xx_serial_break_ctl,
920 .startup = s3c24xx_serial_startup,
921 .shutdown = s3c24xx_serial_shutdown,
922 .set_termios = s3c24xx_serial_set_termios,
923 .type = s3c24xx_serial_type,
924 .release_port = s3c24xx_serial_release_port,
925 .request_port = s3c24xx_serial_request_port,
926 .config_port = s3c24xx_serial_config_port,
927 .verify_port = s3c24xx_serial_verify_port,
928 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
929 .poll_get_char = s3c24xx_serial_get_poll_char,
930 .poll_put_char = s3c24xx_serial_put_poll_char,
931 #endif
932 };
933
934 static struct uart_driver s3c24xx_uart_drv = {
935 .owner = THIS_MODULE,
936 .driver_name = "s3c2410_serial",
937 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
938 .cons = S3C24XX_SERIAL_CONSOLE,
939 .dev_name = S3C24XX_SERIAL_NAME,
940 .major = S3C24XX_SERIAL_MAJOR,
941 .minor = S3C24XX_SERIAL_MINOR,
942 };
943
944 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
945 [0] = {
946 .port = {
947 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
948 .iotype = UPIO_MEM,
949 .uartclk = 0,
950 .fifosize = 16,
951 .ops = &s3c24xx_serial_ops,
952 .flags = UPF_BOOT_AUTOCONF,
953 .line = 0,
954 }
955 },
956 [1] = {
957 .port = {
958 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
959 .iotype = UPIO_MEM,
960 .uartclk = 0,
961 .fifosize = 16,
962 .ops = &s3c24xx_serial_ops,
963 .flags = UPF_BOOT_AUTOCONF,
964 .line = 1,
965 }
966 },
967 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
968
969 [2] = {
970 .port = {
971 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
972 .iotype = UPIO_MEM,
973 .uartclk = 0,
974 .fifosize = 16,
975 .ops = &s3c24xx_serial_ops,
976 .flags = UPF_BOOT_AUTOCONF,
977 .line = 2,
978 }
979 },
980 #endif
981 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
982 [3] = {
983 .port = {
984 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
985 .iotype = UPIO_MEM,
986 .uartclk = 0,
987 .fifosize = 16,
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
990 .line = 3,
991 }
992 }
993 #endif
994 };
995
996 /* s3c24xx_serial_resetport
997 *
998 * reset the fifos and other the settings.
999 */
1000
1001 static void s3c24xx_serial_resetport(struct uart_port *port,
1002 struct s3c2410_uartcfg *cfg)
1003 {
1004 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1005 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1006 unsigned int ucon_mask;
1007
1008 ucon_mask = info->clksel_mask;
1009 if (info->type == PORT_S3C2440)
1010 ucon_mask |= S3C2440_UCON0_DIVMASK;
1011
1012 ucon &= ucon_mask;
1013 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1014
1015 /* reset both fifos */
1016 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1017 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1018
1019 /* some delay is required after fifo reset */
1020 udelay(1);
1021 }
1022
1023
1024 #ifdef CONFIG_CPU_FREQ
1025
1026 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1027 unsigned long val, void *data)
1028 {
1029 struct s3c24xx_uart_port *port;
1030 struct uart_port *uport;
1031
1032 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1033 uport = &port->port;
1034
1035 /* check to see if port is enabled */
1036
1037 if (port->pm_level != 0)
1038 return 0;
1039
1040 /* try and work out if the baudrate is changing, we can detect
1041 * a change in rate, but we do not have support for detecting
1042 * a disturbance in the clock-rate over the change.
1043 */
1044
1045 if (IS_ERR(port->baudclk))
1046 goto exit;
1047
1048 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1049 goto exit;
1050
1051 if (val == CPUFREQ_PRECHANGE) {
1052 /* we should really shut the port down whilst the
1053 * frequency change is in progress. */
1054
1055 } else if (val == CPUFREQ_POSTCHANGE) {
1056 struct ktermios *termios;
1057 struct tty_struct *tty;
1058
1059 if (uport->state == NULL)
1060 goto exit;
1061
1062 tty = uport->state->port.tty;
1063
1064 if (tty == NULL)
1065 goto exit;
1066
1067 termios = &tty->termios;
1068
1069 if (termios == NULL) {
1070 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1071 goto exit;
1072 }
1073
1074 s3c24xx_serial_set_termios(uport, termios, NULL);
1075 }
1076
1077 exit:
1078 return 0;
1079 }
1080
1081 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1082 {
1083 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1084
1085 return cpufreq_register_notifier(&port->freq_transition,
1086 CPUFREQ_TRANSITION_NOTIFIER);
1087 }
1088
1089 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1090 {
1091 cpufreq_unregister_notifier(&port->freq_transition,
1092 CPUFREQ_TRANSITION_NOTIFIER);
1093 }
1094
1095 #else
1096 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1097 {
1098 return 0;
1099 }
1100
1101 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1102 {
1103 }
1104 #endif
1105
1106 /* s3c24xx_serial_init_port
1107 *
1108 * initialise a single serial port from the platform device given
1109 */
1110
1111 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1112 struct platform_device *platdev)
1113 {
1114 struct uart_port *port = &ourport->port;
1115 struct s3c2410_uartcfg *cfg = ourport->cfg;
1116 struct resource *res;
1117 int ret;
1118
1119 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1120
1121 if (platdev == NULL)
1122 return -ENODEV;
1123
1124 if (port->mapbase != 0)
1125 return 0;
1126
1127 /* setup info for port */
1128 port->dev = &platdev->dev;
1129
1130 /* Startup sequence is different for s3c64xx and higher SoC's */
1131 if (s3c24xx_serial_has_interrupt_mask(port))
1132 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1133
1134 port->uartclk = 1;
1135
1136 if (cfg->uart_flags & UPF_CONS_FLOW) {
1137 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1138 port->flags |= UPF_CONS_FLOW;
1139 }
1140
1141 /* sort our the physical and virtual addresses for each UART */
1142
1143 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1144 if (res == NULL) {
1145 dev_err(port->dev, "failed to find memory resource for uart\n");
1146 return -EINVAL;
1147 }
1148
1149 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1150
1151 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1152 if (!port->membase) {
1153 dev_err(port->dev, "failed to remap controller address\n");
1154 return -EBUSY;
1155 }
1156
1157 port->mapbase = res->start;
1158 ret = platform_get_irq(platdev, 0);
1159 if (ret < 0)
1160 port->irq = 0;
1161 else {
1162 port->irq = ret;
1163 ourport->rx_irq = ret;
1164 ourport->tx_irq = ret + 1;
1165 }
1166
1167 ret = platform_get_irq(platdev, 1);
1168 if (ret > 0)
1169 ourport->tx_irq = ret;
1170
1171 ourport->clk = clk_get(&platdev->dev, "uart");
1172 if (IS_ERR(ourport->clk)) {
1173 pr_err("%s: Controller clock not found\n",
1174 dev_name(&platdev->dev));
1175 return PTR_ERR(ourport->clk);
1176 }
1177
1178 ret = clk_prepare_enable(ourport->clk);
1179 if (ret) {
1180 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1181 clk_put(ourport->clk);
1182 return ret;
1183 }
1184
1185 /* Keep all interrupts masked and cleared */
1186 if (s3c24xx_serial_has_interrupt_mask(port)) {
1187 wr_regl(port, S3C64XX_UINTM, 0xf);
1188 wr_regl(port, S3C64XX_UINTP, 0xf);
1189 wr_regl(port, S3C64XX_UINTSP, 0xf);
1190 }
1191
1192 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1193 port->mapbase, port->membase, port->irq,
1194 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1195
1196 /* reset the fifos (and setup the uart) */
1197 s3c24xx_serial_resetport(port, cfg);
1198 clk_disable_unprepare(ourport->clk);
1199 return 0;
1200 }
1201
1202 #ifdef CONFIG_SAMSUNG_CLOCK
1203 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1204 struct device_attribute *attr,
1205 char *buf)
1206 {
1207 struct uart_port *port = s3c24xx_dev_to_port(dev);
1208 struct s3c24xx_uart_port *ourport = to_ourport(port);
1209
1210 if (IS_ERR(ourport->baudclk))
1211 return -EINVAL;
1212
1213 return snprintf(buf, PAGE_SIZE, "* %s\n",
1214 ourport->baudclk->name ?: "(null)");
1215 }
1216
1217 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1218 #endif
1219
1220 /* Device driver serial port probe */
1221
1222 static const struct of_device_id s3c24xx_uart_dt_match[];
1223 static int probe_index;
1224
1225 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1226 struct platform_device *pdev)
1227 {
1228 #ifdef CONFIG_OF
1229 if (pdev->dev.of_node) {
1230 const struct of_device_id *match;
1231 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1232 return (struct s3c24xx_serial_drv_data *)match->data;
1233 }
1234 #endif
1235 return (struct s3c24xx_serial_drv_data *)
1236 platform_get_device_id(pdev)->driver_data;
1237 }
1238
1239 static int s3c24xx_serial_probe(struct platform_device *pdev)
1240 {
1241 struct s3c24xx_uart_port *ourport;
1242 int ret;
1243
1244 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1245
1246 ourport = &s3c24xx_serial_ports[probe_index];
1247
1248 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1249 if (!ourport->drv_data) {
1250 dev_err(&pdev->dev, "could not find driver data\n");
1251 return -ENODEV;
1252 }
1253
1254 ourport->baudclk = ERR_PTR(-EINVAL);
1255 ourport->info = ourport->drv_data->info;
1256 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1257 (struct s3c2410_uartcfg *)dev_get_platdata(&pdev->dev) :
1258 ourport->drv_data->def_cfg;
1259
1260 ourport->port.fifosize = (ourport->info->fifosize) ?
1261 ourport->info->fifosize :
1262 ourport->drv_data->fifosize[probe_index];
1263
1264 probe_index++;
1265
1266 dbg("%s: initialising port %p...\n", __func__, ourport);
1267
1268 ret = s3c24xx_serial_init_port(ourport, pdev);
1269 if (ret < 0)
1270 goto probe_err;
1271
1272 dbg("%s: adding port\n", __func__);
1273 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1274 platform_set_drvdata(pdev, &ourport->port);
1275
1276 #ifdef CONFIG_SAMSUNG_CLOCK
1277 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1278 if (ret < 0)
1279 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1280 #endif
1281
1282 ret = s3c24xx_serial_cpufreq_register(ourport);
1283 if (ret < 0)
1284 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1285
1286 return 0;
1287
1288 probe_err:
1289 return ret;
1290 }
1291
1292 static int s3c24xx_serial_remove(struct platform_device *dev)
1293 {
1294 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1295
1296 if (port) {
1297 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1298 #ifdef CONFIG_SAMSUNG_CLOCK
1299 device_remove_file(&dev->dev, &dev_attr_clock_source);
1300 #endif
1301 uart_remove_one_port(&s3c24xx_uart_drv, port);
1302 }
1303
1304 return 0;
1305 }
1306
1307 /* UART power management code */
1308 #ifdef CONFIG_PM_SLEEP
1309 static int s3c24xx_serial_suspend(struct device *dev)
1310 {
1311 struct uart_port *port = s3c24xx_dev_to_port(dev);
1312
1313 if (port)
1314 uart_suspend_port(&s3c24xx_uart_drv, port);
1315
1316 return 0;
1317 }
1318
1319 static int s3c24xx_serial_resume(struct device *dev)
1320 {
1321 struct uart_port *port = s3c24xx_dev_to_port(dev);
1322 struct s3c24xx_uart_port *ourport = to_ourport(port);
1323
1324 if (port) {
1325 clk_prepare_enable(ourport->clk);
1326 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1327 clk_disable_unprepare(ourport->clk);
1328
1329 uart_resume_port(&s3c24xx_uart_drv, port);
1330 }
1331
1332 return 0;
1333 }
1334
1335 static int s3c24xx_serial_resume_noirq(struct device *dev)
1336 {
1337 struct uart_port *port = s3c24xx_dev_to_port(dev);
1338
1339 if (port) {
1340 /* restore IRQ mask */
1341 if (s3c24xx_serial_has_interrupt_mask(port)) {
1342 unsigned int uintm = 0xf;
1343 if (tx_enabled(port))
1344 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1345 if (rx_enabled(port))
1346 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1347 wr_regl(port, S3C64XX_UINTM, uintm);
1348 }
1349 }
1350
1351 return 0;
1352 }
1353
1354 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1355 .suspend = s3c24xx_serial_suspend,
1356 .resume = s3c24xx_serial_resume,
1357 .resume_noirq = s3c24xx_serial_resume_noirq,
1358 };
1359 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1360
1361 #else /* !CONFIG_PM_SLEEP */
1362
1363 #define SERIAL_SAMSUNG_PM_OPS NULL
1364 #endif /* CONFIG_PM_SLEEP */
1365
1366 /* Console code */
1367
1368 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1369
1370 static struct uart_port *cons_uart;
1371
1372 static int
1373 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1374 {
1375 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1376 unsigned long ufstat, utrstat;
1377
1378 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1379 /* fifo mode - check amount of data in fifo registers... */
1380
1381 ufstat = rd_regl(port, S3C2410_UFSTAT);
1382 return (ufstat & info->tx_fifofull) ? 0 : 1;
1383 }
1384
1385 /* in non-fifo mode, we go and use the tx buffer empty */
1386
1387 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1388 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1389 }
1390
1391 static bool
1392 s3c24xx_port_configured(unsigned int ucon)
1393 {
1394 /* consider the serial port configured if the tx/rx mode set */
1395 return (ucon & 0xf) != 0;
1396 }
1397
1398 #ifdef CONFIG_CONSOLE_POLL
1399 /*
1400 * Console polling routines for writing and reading from the uart while
1401 * in an interrupt or debug context.
1402 */
1403
1404 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1405 {
1406 struct s3c24xx_uart_port *ourport = to_ourport(port);
1407 unsigned int ufstat;
1408
1409 ufstat = rd_regl(port, S3C2410_UFSTAT);
1410 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1411 return NO_POLL_CHAR;
1412
1413 return rd_regb(port, S3C2410_URXH);
1414 }
1415
1416 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1417 unsigned char c)
1418 {
1419 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1420 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1421
1422 /* not possible to xmit on unconfigured port */
1423 if (!s3c24xx_port_configured(ucon))
1424 return;
1425
1426 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1427 cpu_relax();
1428 wr_regb(cons_uart, S3C2410_UTXH, c);
1429 }
1430
1431 #endif /* CONFIG_CONSOLE_POLL */
1432
1433 static void
1434 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1435 {
1436 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1437 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1438
1439 /* not possible to xmit on unconfigured port */
1440 if (!s3c24xx_port_configured(ucon))
1441 return;
1442
1443 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1444 barrier();
1445 wr_regb(cons_uart, S3C2410_UTXH, ch);
1446 }
1447
1448 static void
1449 s3c24xx_serial_console_write(struct console *co, const char *s,
1450 unsigned int count)
1451 {
1452 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1453 }
1454
1455 static void __init
1456 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1457 int *parity, int *bits)
1458 {
1459 struct clk *clk;
1460 unsigned int ulcon;
1461 unsigned int ucon;
1462 unsigned int ubrdiv;
1463 unsigned long rate;
1464 unsigned int clk_sel;
1465 char clk_name[MAX_CLK_NAME_LENGTH];
1466
1467 ulcon = rd_regl(port, S3C2410_ULCON);
1468 ucon = rd_regl(port, S3C2410_UCON);
1469 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1470
1471 dbg("s3c24xx_serial_get_options: port=%p\n"
1472 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1473 port, ulcon, ucon, ubrdiv);
1474
1475 if (s3c24xx_port_configured(ucon)) {
1476 switch (ulcon & S3C2410_LCON_CSMASK) {
1477 case S3C2410_LCON_CS5:
1478 *bits = 5;
1479 break;
1480 case S3C2410_LCON_CS6:
1481 *bits = 6;
1482 break;
1483 case S3C2410_LCON_CS7:
1484 *bits = 7;
1485 break;
1486 default:
1487 case S3C2410_LCON_CS8:
1488 *bits = 8;
1489 break;
1490 }
1491
1492 switch (ulcon & S3C2410_LCON_PMASK) {
1493 case S3C2410_LCON_PEVEN:
1494 *parity = 'e';
1495 break;
1496
1497 case S3C2410_LCON_PODD:
1498 *parity = 'o';
1499 break;
1500
1501 case S3C2410_LCON_PNONE:
1502 default:
1503 *parity = 'n';
1504 }
1505
1506 /* now calculate the baud rate */
1507
1508 clk_sel = s3c24xx_serial_getsource(port);
1509 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1510
1511 clk = clk_get(port->dev, clk_name);
1512 if (!IS_ERR(clk))
1513 rate = clk_get_rate(clk);
1514 else
1515 rate = 1;
1516
1517 *baud = rate / (16 * (ubrdiv + 1));
1518 dbg("calculated baud %d\n", *baud);
1519 }
1520
1521 }
1522
1523 static int __init
1524 s3c24xx_serial_console_setup(struct console *co, char *options)
1525 {
1526 struct uart_port *port;
1527 int baud = 9600;
1528 int bits = 8;
1529 int parity = 'n';
1530 int flow = 'n';
1531
1532 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1533 co, co->index, options);
1534
1535 /* is this a valid port */
1536
1537 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1538 co->index = 0;
1539
1540 port = &s3c24xx_serial_ports[co->index].port;
1541
1542 /* is the port configured? */
1543
1544 if (port->mapbase == 0x0)
1545 return -ENODEV;
1546
1547 cons_uart = port;
1548
1549 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1550
1551 /*
1552 * Check whether an invalid uart number has been specified, and
1553 * if so, search for the first available port that does have
1554 * console support.
1555 */
1556 if (options)
1557 uart_parse_options(options, &baud, &parity, &bits, &flow);
1558 else
1559 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1560
1561 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1562
1563 return uart_set_options(port, co, baud, parity, bits, flow);
1564 }
1565
1566 static struct console s3c24xx_serial_console = {
1567 .name = S3C24XX_SERIAL_NAME,
1568 .device = uart_console_device,
1569 .flags = CON_PRINTBUFFER,
1570 .index = -1,
1571 .write = s3c24xx_serial_console_write,
1572 .setup = s3c24xx_serial_console_setup,
1573 .data = &s3c24xx_uart_drv,
1574 };
1575 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1576
1577 #ifdef CONFIG_CPU_S3C2410
1578 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1579 .info = &(struct s3c24xx_uart_info) {
1580 .name = "Samsung S3C2410 UART",
1581 .type = PORT_S3C2410,
1582 .fifosize = 16,
1583 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1584 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1585 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1586 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1587 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1588 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1589 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1590 .num_clks = 2,
1591 .clksel_mask = S3C2410_UCON_CLKMASK,
1592 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1593 },
1594 .def_cfg = &(struct s3c2410_uartcfg) {
1595 .ucon = S3C2410_UCON_DEFAULT,
1596 .ufcon = S3C2410_UFCON_DEFAULT,
1597 },
1598 };
1599 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1600 #else
1601 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1602 #endif
1603
1604 #ifdef CONFIG_CPU_S3C2412
1605 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1606 .info = &(struct s3c24xx_uart_info) {
1607 .name = "Samsung S3C2412 UART",
1608 .type = PORT_S3C2412,
1609 .fifosize = 64,
1610 .has_divslot = 1,
1611 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1612 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1613 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1614 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1615 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1616 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1617 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1618 .num_clks = 4,
1619 .clksel_mask = S3C2412_UCON_CLKMASK,
1620 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1621 },
1622 .def_cfg = &(struct s3c2410_uartcfg) {
1623 .ucon = S3C2410_UCON_DEFAULT,
1624 .ufcon = S3C2410_UFCON_DEFAULT,
1625 },
1626 };
1627 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1628 #else
1629 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1630 #endif
1631
1632 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1633 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1634 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1635 .info = &(struct s3c24xx_uart_info) {
1636 .name = "Samsung S3C2440 UART",
1637 .type = PORT_S3C2440,
1638 .fifosize = 64,
1639 .has_divslot = 1,
1640 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1641 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1642 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1643 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1644 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1645 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1646 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1647 .num_clks = 4,
1648 .clksel_mask = S3C2412_UCON_CLKMASK,
1649 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1650 },
1651 .def_cfg = &(struct s3c2410_uartcfg) {
1652 .ucon = S3C2410_UCON_DEFAULT,
1653 .ufcon = S3C2410_UFCON_DEFAULT,
1654 },
1655 };
1656 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1657 #else
1658 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1659 #endif
1660
1661 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1662 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1663 defined(CONFIG_CPU_S5PC100)
1664 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1665 .info = &(struct s3c24xx_uart_info) {
1666 .name = "Samsung S3C6400 UART",
1667 .type = PORT_S3C6400,
1668 .fifosize = 64,
1669 .has_divslot = 1,
1670 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1671 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1672 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1673 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1674 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1675 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1676 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1677 .num_clks = 4,
1678 .clksel_mask = S3C6400_UCON_CLKMASK,
1679 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1680 },
1681 .def_cfg = &(struct s3c2410_uartcfg) {
1682 .ucon = S3C2410_UCON_DEFAULT,
1683 .ufcon = S3C2410_UFCON_DEFAULT,
1684 },
1685 };
1686 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1687 #else
1688 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1689 #endif
1690
1691 #ifdef CONFIG_CPU_S5PV210
1692 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1693 .info = &(struct s3c24xx_uart_info) {
1694 .name = "Samsung S5PV210 UART",
1695 .type = PORT_S3C6400,
1696 .has_divslot = 1,
1697 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1698 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1699 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1700 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1701 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1702 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1703 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1704 .num_clks = 2,
1705 .clksel_mask = S5PV210_UCON_CLKMASK,
1706 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1707 },
1708 .def_cfg = &(struct s3c2410_uartcfg) {
1709 .ucon = S5PV210_UCON_DEFAULT,
1710 .ufcon = S5PV210_UFCON_DEFAULT,
1711 },
1712 .fifosize = { 256, 64, 16, 16 },
1713 };
1714 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1715 #else
1716 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1717 #endif
1718
1719 #if defined(CONFIG_ARCH_EXYNOS)
1720 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1721 .info = &(struct s3c24xx_uart_info) {
1722 .name = "Samsung Exynos4 UART",
1723 .type = PORT_S3C6400,
1724 .has_divslot = 1,
1725 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1726 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1727 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1728 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1729 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1730 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1731 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1732 .num_clks = 1,
1733 .clksel_mask = 0,
1734 .clksel_shift = 0,
1735 },
1736 .def_cfg = &(struct s3c2410_uartcfg) {
1737 .ucon = S5PV210_UCON_DEFAULT,
1738 .ufcon = S5PV210_UFCON_DEFAULT,
1739 .has_fracval = 1,
1740 },
1741 .fifosize = { 256, 64, 16, 16 },
1742 };
1743 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1744 #else
1745 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1746 #endif
1747
1748 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1749 {
1750 .name = "s3c2410-uart",
1751 .driver_data = S3C2410_SERIAL_DRV_DATA,
1752 }, {
1753 .name = "s3c2412-uart",
1754 .driver_data = S3C2412_SERIAL_DRV_DATA,
1755 }, {
1756 .name = "s3c2440-uart",
1757 .driver_data = S3C2440_SERIAL_DRV_DATA,
1758 }, {
1759 .name = "s3c6400-uart",
1760 .driver_data = S3C6400_SERIAL_DRV_DATA,
1761 }, {
1762 .name = "s5pv210-uart",
1763 .driver_data = S5PV210_SERIAL_DRV_DATA,
1764 }, {
1765 .name = "exynos4210-uart",
1766 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1767 },
1768 { },
1769 };
1770 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1771
1772 #ifdef CONFIG_OF
1773 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1774 { .compatible = "samsung,s3c2410-uart",
1775 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1776 { .compatible = "samsung,s3c2412-uart",
1777 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1778 { .compatible = "samsung,s3c2440-uart",
1779 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1780 { .compatible = "samsung,s3c6400-uart",
1781 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1782 { .compatible = "samsung,s5pv210-uart",
1783 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1784 { .compatible = "samsung,exynos4210-uart",
1785 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1786 {},
1787 };
1788 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1789 #endif
1790
1791 static struct platform_driver samsung_serial_driver = {
1792 .probe = s3c24xx_serial_probe,
1793 .remove = s3c24xx_serial_remove,
1794 .id_table = s3c24xx_serial_driver_ids,
1795 .driver = {
1796 .name = "samsung-uart",
1797 .owner = THIS_MODULE,
1798 .pm = SERIAL_SAMSUNG_PM_OPS,
1799 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1800 },
1801 };
1802
1803 /* module initialisation code */
1804
1805 static int __init s3c24xx_serial_modinit(void)
1806 {
1807 int ret;
1808
1809 ret = uart_register_driver(&s3c24xx_uart_drv);
1810 if (ret < 0) {
1811 pr_err("Failed to register Samsung UART driver\n");
1812 return ret;
1813 }
1814
1815 ret = platform_driver_register(&samsung_serial_driver);
1816 if (ret < 0) {
1817 pr_err("Failed to register platform driver\n");
1818 uart_unregister_driver(&s3c24xx_uart_drv);
1819 }
1820
1821 return ret;
1822 }
1823
1824 static void __exit s3c24xx_serial_modexit(void)
1825 {
1826 platform_driver_unregister(&samsung_serial_driver);
1827 uart_unregister_driver(&s3c24xx_uart_drv);
1828 }
1829
1830 module_init(s3c24xx_serial_modinit);
1831 module_exit(s3c24xx_serial_modexit);
1832
1833 MODULE_ALIAS("platform:samsung-uart");
1834 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1835 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1836 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support