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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / drivers / usb / dwc3 / gadget.c
blobc37da0c9a076070823006c542e519941b8df879c
1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32
33 #include "core.h"
34 #include "gadget.h"
35 #include "io.h"
36
37 /**
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 *
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
44 * is passed
45 */
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47 {
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68 }
69
70 /**
71 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
72 * @dwc: pointer to our context structure
73 * @state: the state to put link into
74 *
75 * Caller should take care of locking. This function will
76 * return 0 on success or -ETIMEDOUT.
77 */
78 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
79 {
80 int retries = 10000;
81 u32 reg;
82
83 /*
84 * Wait until device controller is ready. Only applies to 1.94a and
85 * later RTL.
86 */
87 if (dwc->revision >= DWC3_REVISION_194A) {
88 while (--retries) {
89 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
90 if (reg & DWC3_DSTS_DCNRD)
91 udelay(5);
92 else
93 break;
94 }
95
96 if (retries <= 0)
97 return -ETIMEDOUT;
98 }
99
100 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
101 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
102
103 /* set requested state */
104 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
105 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
106
107 /*
108 * The following code is racy when called from dwc3_gadget_wakeup,
109 * and is not needed, at least on newer versions
110 */
111 if (dwc->revision >= DWC3_REVISION_194A)
112 return 0;
113
114 /* wait for a change in DSTS */
115 retries = 10000;
116 while (--retries) {
117 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
118
119 if (DWC3_DSTS_USBLNKST(reg) == state)
120 return 0;
121
122 udelay(5);
123 }
124
125 dev_vdbg(dwc->dev, "link state change request timed out\n");
126
127 return -ETIMEDOUT;
128 }
129
130 /**
131 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
132 * @dwc: pointer to our context structure
133 *
134 * This function will a best effort FIFO allocation in order
135 * to improve FIFO usage and throughput, while still allowing
136 * us to enable as many endpoints as possible.
137 *
138 * Keep in mind that this operation will be highly dependent
139 * on the configured size for RAM1 - which contains TxFifo -,
140 * the amount of endpoints enabled on coreConsultant tool, and
141 * the width of the Master Bus.
142 *
143 * In the ideal world, we would always be able to satisfy the
144 * following equation:
145 *
146 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
147 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
148 *
149 * Unfortunately, due to many variables that's not always the case.
150 */
151 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
152 {
153 int last_fifo_depth = 0;
154 int ram1_depth;
155 int fifo_size;
156 int mdwidth;
157 int num;
158
159 if (!dwc->needs_fifo_resize)
160 return 0;
161
162 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
163 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
164
165 /* MDWIDTH is represented in bits, we need it in bytes */
166 mdwidth >>= 3;
167
168 /*
169 * FIXME For now we will only allocate 1 wMaxPacketSize space
170 * for each enabled endpoint, later patches will come to
171 * improve this algorithm so that we better use the internal
172 * FIFO space
173 */
174 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
175 struct dwc3_ep *dep = dwc->eps[num];
176 int fifo_number = dep->number >> 1;
177 int mult = 1;
178 int tmp;
179
180 if (!(dep->number & 1))
181 continue;
182
183 if (!(dep->flags & DWC3_EP_ENABLED))
184 continue;
185
186 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
187 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
188 mult = 3;
189
190 /*
191 * REVISIT: the following assumes we will always have enough
192 * space available on the FIFO RAM for all possible use cases.
193 * Make sure that's true somehow and change FIFO allocation
194 * accordingly.
195 *
196 * If we have Bulk or Isochronous endpoints, we want
197 * them to be able to be very, very fast. So we're giving
198 * those endpoints a fifo_size which is enough for 3 full
199 * packets
200 */
201 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
202 tmp += mdwidth;
203
204 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
205
206 fifo_size |= (last_fifo_depth << 16);
207
208 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
209 dep->name, last_fifo_depth, fifo_size & 0xffff);
210
211 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
212 fifo_size);
213
214 last_fifo_depth += (fifo_size & 0xffff);
215 }
216
217 return 0;
218 }
219
220 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
221 int status)
222 {
223 struct dwc3 *dwc = dep->dwc;
224 int i;
225
226 if (req->queued) {
227 i = 0;
228 do {
229 dep->busy_slot++;
230 /*
231 * Skip LINK TRB. We can't use req->trb and check for
232 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
233 * just completed (not the LINK TRB).
234 */
235 if (((dep->busy_slot & DWC3_TRB_MASK) ==
236 DWC3_TRB_NUM- 1) &&
237 usb_endpoint_xfer_isoc(dep->endpoint.desc))
238 dep->busy_slot++;
239 } while(++i < req->request.num_mapped_sgs);
240 req->queued = false;
241 }
242 list_del(&req->list);
243 req->trb = NULL;
244
245 if (req->request.status == -EINPROGRESS)
246 req->request.status = status;
247
248 if (dwc->ep0_bounced && dep->number == 0)
249 dwc->ep0_bounced = false;
250 else
251 usb_gadget_unmap_request(&dwc->gadget, &req->request,
252 req->direction);
253
254 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
255 req, dep->name, req->request.actual,
256 req->request.length, status);
257
258 spin_unlock(&dwc->lock);
259 req->request.complete(&dep->endpoint, &req->request);
260 spin_lock(&dwc->lock);
261 }
262
263 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
264 {
265 switch (cmd) {
266 case DWC3_DEPCMD_DEPSTARTCFG:
267 return "Start New Configuration";
268 case DWC3_DEPCMD_ENDTRANSFER:
269 return "End Transfer";
270 case DWC3_DEPCMD_UPDATETRANSFER:
271 return "Update Transfer";
272 case DWC3_DEPCMD_STARTTRANSFER:
273 return "Start Transfer";
274 case DWC3_DEPCMD_CLEARSTALL:
275 return "Clear Stall";
276 case DWC3_DEPCMD_SETSTALL:
277 return "Set Stall";
278 case DWC3_DEPCMD_GETEPSTATE:
279 return "Get Endpoint State";
280 case DWC3_DEPCMD_SETTRANSFRESOURCE:
281 return "Set Endpoint Transfer Resource";
282 case DWC3_DEPCMD_SETEPCONFIG:
283 return "Set Endpoint Configuration";
284 default:
285 return "UNKNOWN command";
286 }
287 }
288
289 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
290 {
291 u32 timeout = 500;
292 u32 reg;
293
294 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
295 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
296
297 do {
298 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
299 if (!(reg & DWC3_DGCMD_CMDACT)) {
300 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
301 DWC3_DGCMD_STATUS(reg));
302 return 0;
303 }
304
305 /*
306 * We can't sleep here, because it's also called from
307 * interrupt context.
308 */
309 timeout--;
310 if (!timeout)
311 return -ETIMEDOUT;
312 udelay(1);
313 } while (1);
314 }
315
316 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
317 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
318 {
319 struct dwc3_ep *dep = dwc->eps[ep];
320 u32 timeout = 500;
321 u32 reg;
322
323 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
324 dep->name,
325 dwc3_gadget_ep_cmd_string(cmd), params->param0,
326 params->param1, params->param2);
327
328 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
329 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
330 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
331
332 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
333 do {
334 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
335 if (!(reg & DWC3_DEPCMD_CMDACT)) {
336 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
337 DWC3_DEPCMD_STATUS(reg));
338 return 0;
339 }
340
341 /*
342 * We can't sleep here, because it is also called from
343 * interrupt context.
344 */
345 timeout--;
346 if (!timeout)
347 return -ETIMEDOUT;
348
349 udelay(1);
350 } while (1);
351 }
352
353 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
354 struct dwc3_trb *trb)
355 {
356 u32 offset = (char *) trb - (char *) dep->trb_pool;
357
358 return dep->trb_pool_dma + offset;
359 }
360
361 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
362 {
363 struct dwc3 *dwc = dep->dwc;
364
365 if (dep->trb_pool)
366 return 0;
367
368 if (dep->number == 0 || dep->number == 1)
369 return 0;
370
371 dep->trb_pool = dma_alloc_coherent(dwc->dev,
372 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
373 &dep->trb_pool_dma, GFP_KERNEL);
374 if (!dep->trb_pool) {
375 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
376 dep->name);
377 return -ENOMEM;
378 }
379
380 return 0;
381 }
382
383 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
384 {
385 struct dwc3 *dwc = dep->dwc;
386
387 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 dep->trb_pool, dep->trb_pool_dma);
389
390 dep->trb_pool = NULL;
391 dep->trb_pool_dma = 0;
392 }
393
394 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
395 {
396 struct dwc3_gadget_ep_cmd_params params;
397 u32 cmd;
398
399 memset(&params, 0x00, sizeof(params));
400
401 if (dep->number != 1) {
402 cmd = DWC3_DEPCMD_DEPSTARTCFG;
403 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
404 if (dep->number > 1) {
405 if (dwc->start_config_issued)
406 return 0;
407 dwc->start_config_issued = true;
408 cmd |= DWC3_DEPCMD_PARAM(2);
409 }
410
411 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
412 }
413
414 return 0;
415 }
416
417 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
418 const struct usb_endpoint_descriptor *desc,
419 const struct usb_ss_ep_comp_descriptor *comp_desc,
420 bool ignore)
421 {
422 struct dwc3_gadget_ep_cmd_params params;
423
424 memset(&params, 0x00, sizeof(params));
425
426 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
427 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
428
429 /* Burst size is only needed in SuperSpeed mode */
430 if (dwc->gadget.speed == USB_SPEED_SUPER) {
431 u32 burst = dep->endpoint.maxburst - 1;
432
433 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
434 }
435
436 if (ignore)
437 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
438
439 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
440 | DWC3_DEPCFG_XFER_NOT_READY_EN;
441
442 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
443 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
444 | DWC3_DEPCFG_STREAM_EVENT_EN;
445 dep->stream_capable = true;
446 }
447
448 if (usb_endpoint_xfer_isoc(desc))
449 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
450
451 /*
452 * We are doing 1:1 mapping for endpoints, meaning
453 * Physical Endpoints 2 maps to Logical Endpoint 2 and
454 * so on. We consider the direction bit as part of the physical
455 * endpoint number. So USB endpoint 0x81 is 0x03.
456 */
457 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
458
459 /*
460 * We must use the lower 16 TX FIFOs even though
461 * HW might have more
462 */
463 if (dep->direction)
464 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
465
466 if (desc->bInterval) {
467 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
468 dep->interval = 1 << (desc->bInterval - 1);
469 }
470
471 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
472 DWC3_DEPCMD_SETEPCONFIG, &params);
473 }
474
475 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
476 {
477 struct dwc3_gadget_ep_cmd_params params;
478
479 memset(&params, 0x00, sizeof(params));
480
481 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
482
483 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
484 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
485 }
486
487 /**
488 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
489 * @dep: endpoint to be initialized
490 * @desc: USB Endpoint Descriptor
491 *
492 * Caller should take care of locking
493 */
494 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
495 const struct usb_endpoint_descriptor *desc,
496 const struct usb_ss_ep_comp_descriptor *comp_desc,
497 bool ignore)
498 {
499 struct dwc3 *dwc = dep->dwc;
500 u32 reg;
501 int ret = -ENOMEM;
502
503 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
504
505 if (!(dep->flags & DWC3_EP_ENABLED)) {
506 ret = dwc3_gadget_start_config(dwc, dep);
507 if (ret)
508 return ret;
509 }
510
511 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
512 if (ret)
513 return ret;
514
515 if (!(dep->flags & DWC3_EP_ENABLED)) {
516 struct dwc3_trb *trb_st_hw;
517 struct dwc3_trb *trb_link;
518
519 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
520 if (ret)
521 return ret;
522
523 dep->endpoint.desc = desc;
524 dep->comp_desc = comp_desc;
525 dep->type = usb_endpoint_type(desc);
526 dep->flags |= DWC3_EP_ENABLED;
527
528 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
529 reg |= DWC3_DALEPENA_EP(dep->number);
530 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
531
532 if (!usb_endpoint_xfer_isoc(desc))
533 return 0;
534
535 memset(&trb_link, 0, sizeof(trb_link));
536
537 /* Link TRB for ISOC. The HWO bit is never reset */
538 trb_st_hw = &dep->trb_pool[0];
539
540 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
541
542 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
543 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
544 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
545 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
546 }
547
548 return 0;
549 }
550
551 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
552 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
553 {
554 struct dwc3_request *req;
555
556 if (!list_empty(&dep->req_queued)) {
557 dwc3_stop_active_transfer(dwc, dep->number);
558
559 /* - giveback all requests to gadget driver */
560 while (!list_empty(&dep->req_queued)) {
561 req = next_request(&dep->req_queued);
562
563 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
564 }
565 }
566
567 while (!list_empty(&dep->request_list)) {
568 req = next_request(&dep->request_list);
569
570 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
571 }
572 }
573
574 /**
575 * __dwc3_gadget_ep_disable - Disables a HW endpoint
576 * @dep: the endpoint to disable
577 *
578 * This function also removes requests which are currently processed ny the
579 * hardware and those which are not yet scheduled.
580 * Caller should take care of locking.
581 */
582 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
583 {
584 struct dwc3 *dwc = dep->dwc;
585 u32 reg;
586
587 dwc3_remove_requests(dwc, dep);
588
589 /* make sure HW endpoint isn't stalled */
590 if (dep->flags & DWC3_EP_STALL)
591 __dwc3_gadget_ep_set_halt(dep, 0);
592
593 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
594 reg &= ~DWC3_DALEPENA_EP(dep->number);
595 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
596
597 dep->stream_capable = false;
598 dep->endpoint.desc = NULL;
599 dep->comp_desc = NULL;
600 dep->type = 0;
601 dep->flags = 0;
602
603 return 0;
604 }
605
606 /* -------------------------------------------------------------------------- */
607
608 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
609 const struct usb_endpoint_descriptor *desc)
610 {
611 return -EINVAL;
612 }
613
614 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
615 {
616 return -EINVAL;
617 }
618
619 /* -------------------------------------------------------------------------- */
620
621 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
622 const struct usb_endpoint_descriptor *desc)
623 {
624 struct dwc3_ep *dep;
625 struct dwc3 *dwc;
626 unsigned long flags;
627 int ret;
628
629 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
630 pr_debug("dwc3: invalid parameters\n");
631 return -EINVAL;
632 }
633
634 if (!desc->wMaxPacketSize) {
635 pr_debug("dwc3: missing wMaxPacketSize\n");
636 return -EINVAL;
637 }
638
639 dep = to_dwc3_ep(ep);
640 dwc = dep->dwc;
641
642 if (dep->flags & DWC3_EP_ENABLED) {
643 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
644 dep->name);
645 return 0;
646 }
647
648 switch (usb_endpoint_type(desc)) {
649 case USB_ENDPOINT_XFER_CONTROL:
650 strlcat(dep->name, "-control", sizeof(dep->name));
651 break;
652 case USB_ENDPOINT_XFER_ISOC:
653 strlcat(dep->name, "-isoc", sizeof(dep->name));
654 break;
655 case USB_ENDPOINT_XFER_BULK:
656 strlcat(dep->name, "-bulk", sizeof(dep->name));
657 break;
658 case USB_ENDPOINT_XFER_INT:
659 strlcat(dep->name, "-int", sizeof(dep->name));
660 break;
661 default:
662 dev_err(dwc->dev, "invalid endpoint transfer type\n");
663 }
664
665 spin_lock_irqsave(&dwc->lock, flags);
666 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
667 spin_unlock_irqrestore(&dwc->lock, flags);
668
669 return ret;
670 }
671
672 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
673 {
674 struct dwc3_ep *dep;
675 struct dwc3 *dwc;
676 unsigned long flags;
677 int ret;
678
679 if (!ep) {
680 pr_debug("dwc3: invalid parameters\n");
681 return -EINVAL;
682 }
683
684 dep = to_dwc3_ep(ep);
685 dwc = dep->dwc;
686
687 if (!(dep->flags & DWC3_EP_ENABLED)) {
688 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
689 dep->name);
690 return 0;
691 }
692
693 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
694 dep->number >> 1,
695 (dep->number & 1) ? "in" : "out");
696
697 spin_lock_irqsave(&dwc->lock, flags);
698 ret = __dwc3_gadget_ep_disable(dep);
699 spin_unlock_irqrestore(&dwc->lock, flags);
700
701 return ret;
702 }
703
704 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
705 gfp_t gfp_flags)
706 {
707 struct dwc3_request *req;
708 struct dwc3_ep *dep = to_dwc3_ep(ep);
709 struct dwc3 *dwc = dep->dwc;
710
711 req = kzalloc(sizeof(*req), gfp_flags);
712 if (!req) {
713 dev_err(dwc->dev, "not enough memory\n");
714 return NULL;
715 }
716
717 req->epnum = dep->number;
718 req->dep = dep;
719
720 return &req->request;
721 }
722
723 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
724 struct usb_request *request)
725 {
726 struct dwc3_request *req = to_dwc3_request(request);
727
728 kfree(req);
729 }
730
731 /**
732 * dwc3_prepare_one_trb - setup one TRB from one request
733 * @dep: endpoint for which this request is prepared
734 * @req: dwc3_request pointer
735 */
736 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
737 struct dwc3_request *req, dma_addr_t dma,
738 unsigned length, unsigned last, unsigned chain, unsigned node)
739 {
740 struct dwc3 *dwc = dep->dwc;
741 struct dwc3_trb *trb;
742
743 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
744 dep->name, req, (unsigned long long) dma,
745 length, last ? " last" : "",
746 chain ? " chain" : "");
747
748 /* Skip the LINK-TRB on ISOC */
749 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
750 usb_endpoint_xfer_isoc(dep->endpoint.desc))
751 dep->free_slot++;
752
753 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
754
755 if (!req->trb) {
756 dwc3_gadget_move_request_queued(req);
757 req->trb = trb;
758 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
759 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
760 }
761
762 dep->free_slot++;
763
764 trb->size = DWC3_TRB_SIZE_LENGTH(length);
765 trb->bpl = lower_32_bits(dma);
766 trb->bph = upper_32_bits(dma);
767
768 switch (usb_endpoint_type(dep->endpoint.desc)) {
769 case USB_ENDPOINT_XFER_CONTROL:
770 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
771 break;
772
773 case USB_ENDPOINT_XFER_ISOC:
774 if (!node)
775 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
776 else
777 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
778
779 if (!req->request.no_interrupt && !chain)
780 trb->ctrl |= DWC3_TRB_CTRL_IOC;
781 break;
782
783 case USB_ENDPOINT_XFER_BULK:
784 case USB_ENDPOINT_XFER_INT:
785 trb->ctrl = DWC3_TRBCTL_NORMAL;
786 break;
787 default:
788 /*
789 * This is only possible with faulty memory because we
790 * checked it already :)
791 */
792 BUG();
793 }
794
795 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
796 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
797 trb->ctrl |= DWC3_TRB_CTRL_CSP;
798 } else if (last) {
799 trb->ctrl |= DWC3_TRB_CTRL_LST;
800 }
801
802 if (chain)
803 trb->ctrl |= DWC3_TRB_CTRL_CHN;
804
805 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
806 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
807
808 trb->ctrl |= DWC3_TRB_CTRL_HWO;
809 }
810
811 /*
812 * dwc3_prepare_trbs - setup TRBs from requests
813 * @dep: endpoint for which requests are being prepared
814 * @starting: true if the endpoint is idle and no requests are queued.
815 *
816 * The function goes through the requests list and sets up TRBs for the
817 * transfers. The function returns once there are no more TRBs available or
818 * it runs out of requests.
819 */
820 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
821 {
822 struct dwc3_request *req, *n;
823 u32 trbs_left;
824 u32 max;
825 unsigned int last_one = 0;
826
827 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
828
829 /* the first request must not be queued */
830 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
831
832 /* Can't wrap around on a non-isoc EP since there's no link TRB */
833 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
834 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
835 if (trbs_left > max)
836 trbs_left = max;
837 }
838
839 /*
840 * If busy & slot are equal than it is either full or empty. If we are
841 * starting to process requests then we are empty. Otherwise we are
842 * full and don't do anything
843 */
844 if (!trbs_left) {
845 if (!starting)
846 return;
847 trbs_left = DWC3_TRB_NUM;
848 /*
849 * In case we start from scratch, we queue the ISOC requests
850 * starting from slot 1. This is done because we use ring
851 * buffer and have no LST bit to stop us. Instead, we place
852 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
853 * after the first request so we start at slot 1 and have
854 * 7 requests proceed before we hit the first IOC.
855 * Other transfer types don't use the ring buffer and are
856 * processed from the first TRB until the last one. Since we
857 * don't wrap around we have to start at the beginning.
858 */
859 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
860 dep->busy_slot = 1;
861 dep->free_slot = 1;
862 } else {
863 dep->busy_slot = 0;
864 dep->free_slot = 0;
865 }
866 }
867
868 /* The last TRB is a link TRB, not used for xfer */
869 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
870 return;
871
872 list_for_each_entry_safe(req, n, &dep->request_list, list) {
873 unsigned length;
874 dma_addr_t dma;
875 last_one = false;
876
877 if (req->request.num_mapped_sgs > 0) {
878 struct usb_request *request = &req->request;
879 struct scatterlist *sg = request->sg;
880 struct scatterlist *s;
881 int i;
882
883 for_each_sg(sg, s, request->num_mapped_sgs, i) {
884 unsigned chain = true;
885
886 length = sg_dma_len(s);
887 dma = sg_dma_address(s);
888
889 if (i == (request->num_mapped_sgs - 1) ||
890 sg_is_last(s)) {
891 if (list_is_last(&req->list,
892 &dep->request_list))
893 last_one = true;
894 chain = false;
895 }
896
897 trbs_left--;
898 if (!trbs_left)
899 last_one = true;
900
901 if (last_one)
902 chain = false;
903
904 dwc3_prepare_one_trb(dep, req, dma, length,
905 last_one, chain, i);
906
907 if (last_one)
908 break;
909 }
910 } else {
911 dma = req->request.dma;
912 length = req->request.length;
913 trbs_left--;
914
915 if (!trbs_left)
916 last_one = 1;
917
918 /* Is this the last request? */
919 if (list_is_last(&req->list, &dep->request_list))
920 last_one = 1;
921
922 dwc3_prepare_one_trb(dep, req, dma, length,
923 last_one, false, 0);
924
925 if (last_one)
926 break;
927 }
928 }
929 }
930
931 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
932 int start_new)
933 {
934 struct dwc3_gadget_ep_cmd_params params;
935 struct dwc3_request *req;
936 struct dwc3 *dwc = dep->dwc;
937 int ret;
938 u32 cmd;
939
940 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
941 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
942 return -EBUSY;
943 }
944 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
945
946 /*
947 * If we are getting here after a short-out-packet we don't enqueue any
948 * new requests as we try to set the IOC bit only on the last request.
949 */
950 if (start_new) {
951 if (list_empty(&dep->req_queued))
952 dwc3_prepare_trbs(dep, start_new);
953
954 /* req points to the first request which will be sent */
955 req = next_request(&dep->req_queued);
956 } else {
957 dwc3_prepare_trbs(dep, start_new);
958
959 /*
960 * req points to the first request where HWO changed from 0 to 1
961 */
962 req = next_request(&dep->req_queued);
963 }
964 if (!req) {
965 dep->flags |= DWC3_EP_PENDING_REQUEST;
966 return 0;
967 }
968
969 memset(&params, 0, sizeof(params));
970
971 if (start_new) {
972 params.param0 = upper_32_bits(req->trb_dma);
973 params.param1 = lower_32_bits(req->trb_dma);
974 cmd = DWC3_DEPCMD_STARTTRANSFER;
975 } else {
976 cmd = DWC3_DEPCMD_UPDATETRANSFER;
977 }
978
979 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
980 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
981 if (ret < 0) {
982 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
983
984 /*
985 * FIXME we need to iterate over the list of requests
986 * here and stop, unmap, free and del each of the linked
987 * requests instead of what we do now.
988 */
989 usb_gadget_unmap_request(&dwc->gadget, &req->request,
990 req->direction);
991 list_del(&req->list);
992 return ret;
993 }
994
995 dep->flags |= DWC3_EP_BUSY;
996
997 if (start_new) {
998 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
999 dep->number);
1000 WARN_ON_ONCE(!dep->resource_index);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1007 struct dwc3_ep *dep, u32 cur_uf)
1008 {
1009 u32 uf;
1010
1011 if (list_empty(&dep->request_list)) {
1012 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1013 dep->name);
1014 dep->flags |= DWC3_EP_PENDING_REQUEST;
1015 return;
1016 }
1017
1018 /* 4 micro frames in the future */
1019 uf = cur_uf + dep->interval * 4;
1020
1021 __dwc3_gadget_kick_transfer(dep, uf, 1);
1022 }
1023
1024 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1025 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1026 {
1027 u32 cur_uf, mask;
1028
1029 mask = ~(dep->interval - 1);
1030 cur_uf = event->parameters & mask;
1031
1032 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1033 }
1034
1035 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1036 {
1037 struct dwc3 *dwc = dep->dwc;
1038 int ret;
1039
1040 req->request.actual = 0;
1041 req->request.status = -EINPROGRESS;
1042 req->direction = dep->direction;
1043 req->epnum = dep->number;
1044
1045 /*
1046 * We only add to our list of requests now and
1047 * start consuming the list once we get XferNotReady
1048 * IRQ.
1049 *
1050 * That way, we avoid doing anything that we don't need
1051 * to do now and defer it until the point we receive a
1052 * particular token from the Host side.
1053 *
1054 * This will also avoid Host cancelling URBs due to too
1055 * many NAKs.
1056 */
1057 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1058 dep->direction);
1059 if (ret)
1060 return ret;
1061
1062 list_add_tail(&req->list, &dep->request_list);
1063
1064 /*
1065 * There are a few special cases:
1066 *
1067 * 1. XferNotReady with empty list of requests. We need to kick the
1068 * transfer here in that situation, otherwise we will be NAKing
1069 * forever. If we get XferNotReady before gadget driver has a
1070 * chance to queue a request, we will ACK the IRQ but won't be
1071 * able to receive the data until the next request is queued.
1072 * The following code is handling exactly that.
1073 *
1074 */
1075 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1076 /*
1077 * If xfernotready is already elapsed and it is a case
1078 * of isoc transfer, then issue END TRANSFER, so that
1079 * you can receive xfernotready again and can have
1080 * notion of current microframe.
1081 */
1082 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1083 if (list_empty(&dep->req_queued)) {
1084 dwc3_stop_active_transfer(dwc, dep->number);
1085 dep->flags = DWC3_EP_ENABLED;
1086 }
1087 return 0;
1088 }
1089
1090 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1091 if (ret && ret != -EBUSY)
1092 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1093 dep->name);
1094 return ret;
1095 }
1096
1097 /*
1098 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1099 * kick the transfer here after queuing a request, otherwise the
1100 * core may not see the modified TRB(s).
1101 */
1102 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1103 (dep->flags & DWC3_EP_BUSY) &&
1104 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1105 WARN_ON_ONCE(!dep->resource_index);
1106 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1107 false);
1108 if (ret && ret != -EBUSY)
1109 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1110 dep->name);
1111 return ret;
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1118 gfp_t gfp_flags)
1119 {
1120 struct dwc3_request *req = to_dwc3_request(request);
1121 struct dwc3_ep *dep = to_dwc3_ep(ep);
1122 struct dwc3 *dwc = dep->dwc;
1123
1124 unsigned long flags;
1125
1126 int ret;
1127
1128 if (!dep->endpoint.desc) {
1129 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1130 request, ep->name);
1131 return -ESHUTDOWN;
1132 }
1133
1134 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1135 request, ep->name, request->length);
1136
1137 spin_lock_irqsave(&dwc->lock, flags);
1138 ret = __dwc3_gadget_ep_queue(dep, req);
1139 spin_unlock_irqrestore(&dwc->lock, flags);
1140
1141 return ret;
1142 }
1143
1144 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1145 struct usb_request *request)
1146 {
1147 struct dwc3_request *req = to_dwc3_request(request);
1148 struct dwc3_request *r = NULL;
1149
1150 struct dwc3_ep *dep = to_dwc3_ep(ep);
1151 struct dwc3 *dwc = dep->dwc;
1152
1153 unsigned long flags;
1154 int ret = 0;
1155
1156 spin_lock_irqsave(&dwc->lock, flags);
1157
1158 list_for_each_entry(r, &dep->request_list, list) {
1159 if (r == req)
1160 break;
1161 }
1162
1163 if (r != req) {
1164 list_for_each_entry(r, &dep->req_queued, list) {
1165 if (r == req)
1166 break;
1167 }
1168 if (r == req) {
1169 /* wait until it is processed */
1170 dwc3_stop_active_transfer(dwc, dep->number);
1171 goto out1;
1172 }
1173 dev_err(dwc->dev, "request %p was not queued to %s\n",
1174 request, ep->name);
1175 ret = -EINVAL;
1176 goto out0;
1177 }
1178
1179 out1:
1180 /* giveback the request */
1181 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1182
1183 out0:
1184 spin_unlock_irqrestore(&dwc->lock, flags);
1185
1186 return ret;
1187 }
1188
1189 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1190 {
1191 struct dwc3_gadget_ep_cmd_params params;
1192 struct dwc3 *dwc = dep->dwc;
1193 int ret;
1194
1195 memset(&params, 0x00, sizeof(params));
1196
1197 if (value) {
1198 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1199 DWC3_DEPCMD_SETSTALL, &params);
1200 if (ret)
1201 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1202 value ? "set" : "clear",
1203 dep->name);
1204 else
1205 dep->flags |= DWC3_EP_STALL;
1206 } else {
1207 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1208 DWC3_DEPCMD_CLEARSTALL, &params);
1209 if (ret)
1210 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1211 value ? "set" : "clear",
1212 dep->name);
1213 else
1214 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1215 }
1216
1217 return ret;
1218 }
1219
1220 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1221 {
1222 struct dwc3_ep *dep = to_dwc3_ep(ep);
1223 struct dwc3 *dwc = dep->dwc;
1224
1225 unsigned long flags;
1226
1227 int ret;
1228
1229 spin_lock_irqsave(&dwc->lock, flags);
1230
1231 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1232 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1233 ret = -EINVAL;
1234 goto out;
1235 }
1236
1237 ret = __dwc3_gadget_ep_set_halt(dep, value);
1238 out:
1239 spin_unlock_irqrestore(&dwc->lock, flags);
1240
1241 return ret;
1242 }
1243
1244 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1245 {
1246 struct dwc3_ep *dep = to_dwc3_ep(ep);
1247 struct dwc3 *dwc = dep->dwc;
1248 unsigned long flags;
1249
1250 spin_lock_irqsave(&dwc->lock, flags);
1251 dep->flags |= DWC3_EP_WEDGE;
1252 spin_unlock_irqrestore(&dwc->lock, flags);
1253
1254 if (dep->number == 0 || dep->number == 1)
1255 return dwc3_gadget_ep0_set_halt(ep, 1);
1256 else
1257 return dwc3_gadget_ep_set_halt(ep, 1);
1258 }
1259
1260 /* -------------------------------------------------------------------------- */
1261
1262 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1263 .bLength = USB_DT_ENDPOINT_SIZE,
1264 .bDescriptorType = USB_DT_ENDPOINT,
1265 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1266 };
1267
1268 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1269 .enable = dwc3_gadget_ep0_enable,
1270 .disable = dwc3_gadget_ep0_disable,
1271 .alloc_request = dwc3_gadget_ep_alloc_request,
1272 .free_request = dwc3_gadget_ep_free_request,
1273 .queue = dwc3_gadget_ep0_queue,
1274 .dequeue = dwc3_gadget_ep_dequeue,
1275 .set_halt = dwc3_gadget_ep0_set_halt,
1276 .set_wedge = dwc3_gadget_ep_set_wedge,
1277 };
1278
1279 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1280 .enable = dwc3_gadget_ep_enable,
1281 .disable = dwc3_gadget_ep_disable,
1282 .alloc_request = dwc3_gadget_ep_alloc_request,
1283 .free_request = dwc3_gadget_ep_free_request,
1284 .queue = dwc3_gadget_ep_queue,
1285 .dequeue = dwc3_gadget_ep_dequeue,
1286 .set_halt = dwc3_gadget_ep_set_halt,
1287 .set_wedge = dwc3_gadget_ep_set_wedge,
1288 };
1289
1290 /* -------------------------------------------------------------------------- */
1291
1292 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1293 {
1294 struct dwc3 *dwc = gadget_to_dwc(g);
1295 u32 reg;
1296
1297 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1298 return DWC3_DSTS_SOFFN(reg);
1299 }
1300
1301 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1302 {
1303 struct dwc3 *dwc = gadget_to_dwc(g);
1304
1305 unsigned long timeout;
1306 unsigned long flags;
1307
1308 u32 reg;
1309
1310 int ret = 0;
1311
1312 u8 link_state;
1313 u8 speed;
1314
1315 spin_lock_irqsave(&dwc->lock, flags);
1316
1317 /*
1318 * According to the Databook Remote wakeup request should
1319 * be issued only when the device is in early suspend state.
1320 *
1321 * We can check that via USB Link State bits in DSTS register.
1322 */
1323 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1324
1325 speed = reg & DWC3_DSTS_CONNECTSPD;
1326 if (speed == DWC3_DSTS_SUPERSPEED) {
1327 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1328 ret = -EINVAL;
1329 goto out;
1330 }
1331
1332 link_state = DWC3_DSTS_USBLNKST(reg);
1333
1334 switch (link_state) {
1335 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1336 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1337 break;
1338 default:
1339 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1340 link_state);
1341 ret = -EINVAL;
1342 goto out;
1343 }
1344
1345 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1346 if (ret < 0) {
1347 dev_err(dwc->dev, "failed to put link in Recovery\n");
1348 goto out;
1349 }
1350
1351 /* Recent versions do this automatically */
1352 if (dwc->revision < DWC3_REVISION_194A) {
1353 /* write zeroes to Link Change Request */
1354 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1355 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1356 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1357 }
1358
1359 /* poll until Link State changes to ON */
1360 timeout = jiffies + msecs_to_jiffies(100);
1361
1362 while (!time_after(jiffies, timeout)) {
1363 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1364
1365 /* in HS, means ON */
1366 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1367 break;
1368 }
1369
1370 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1371 dev_err(dwc->dev, "failed to send remote wakeup\n");
1372 ret = -EINVAL;
1373 }
1374
1375 out:
1376 spin_unlock_irqrestore(&dwc->lock, flags);
1377
1378 return ret;
1379 }
1380
1381 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1382 int is_selfpowered)
1383 {
1384 struct dwc3 *dwc = gadget_to_dwc(g);
1385 unsigned long flags;
1386
1387 spin_lock_irqsave(&dwc->lock, flags);
1388 dwc->is_selfpowered = !!is_selfpowered;
1389 spin_unlock_irqrestore(&dwc->lock, flags);
1390
1391 return 0;
1392 }
1393
1394 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1395 {
1396 u32 reg;
1397 u32 timeout = 500;
1398
1399 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1400 if (is_on) {
1401 if (dwc->revision <= DWC3_REVISION_187A) {
1402 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1403 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1404 }
1405
1406 if (dwc->revision >= DWC3_REVISION_194A)
1407 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1408 reg |= DWC3_DCTL_RUN_STOP;
1409 dwc->pullups_connected = true;
1410 } else {
1411 reg &= ~DWC3_DCTL_RUN_STOP;
1412 dwc->pullups_connected = false;
1413 }
1414
1415 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1416
1417 do {
1418 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1419 if (is_on) {
1420 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1421 break;
1422 } else {
1423 if (reg & DWC3_DSTS_DEVCTRLHLT)
1424 break;
1425 }
1426 timeout--;
1427 if (!timeout)
1428 return -ETIMEDOUT;
1429 udelay(1);
1430 } while (1);
1431
1432 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1433 dwc->gadget_driver
1434 ? dwc->gadget_driver->function : "no-function",
1435 is_on ? "connect" : "disconnect");
1436
1437 return 0;
1438 }
1439
1440 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1441 {
1442 struct dwc3 *dwc = gadget_to_dwc(g);
1443 unsigned long flags;
1444 int ret;
1445
1446 is_on = !!is_on;
1447
1448 spin_lock_irqsave(&dwc->lock, flags);
1449 ret = dwc3_gadget_run_stop(dwc, is_on);
1450 spin_unlock_irqrestore(&dwc->lock, flags);
1451
1452 return ret;
1453 }
1454
1455 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1456 {
1457 u32 reg;
1458
1459 /* Enable all but Start and End of Frame IRQs */
1460 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1461 DWC3_DEVTEN_EVNTOVERFLOWEN |
1462 DWC3_DEVTEN_CMDCMPLTEN |
1463 DWC3_DEVTEN_ERRTICERREN |
1464 DWC3_DEVTEN_WKUPEVTEN |
1465 DWC3_DEVTEN_ULSTCNGEN |
1466 DWC3_DEVTEN_CONNECTDONEEN |
1467 DWC3_DEVTEN_USBRSTEN |
1468 DWC3_DEVTEN_DISCONNEVTEN);
1469
1470 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1471 }
1472
1473 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1474 {
1475 /* mask all interrupts */
1476 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1477 }
1478
1479 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1480 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1481
1482 static int dwc3_gadget_start(struct usb_gadget *g,
1483 struct usb_gadget_driver *driver)
1484 {
1485 struct dwc3 *dwc = gadget_to_dwc(g);
1486 struct dwc3_ep *dep;
1487 unsigned long flags;
1488 int ret = 0;
1489 int irq;
1490 u32 reg;
1491
1492 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1493 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1494 IRQF_SHARED, "dwc3", dwc);
1495 if (ret) {
1496 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1497 irq, ret);
1498 goto err0;
1499 }
1500
1501 spin_lock_irqsave(&dwc->lock, flags);
1502
1503 if (dwc->gadget_driver) {
1504 dev_err(dwc->dev, "%s is already bound to %s\n",
1505 dwc->gadget.name,
1506 dwc->gadget_driver->driver.name);
1507 ret = -EBUSY;
1508 goto err1;
1509 }
1510
1511 dwc->gadget_driver = driver;
1512
1513 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1514 reg &= ~(DWC3_DCFG_SPEED_MASK);
1515
1516 /**
1517 * WORKAROUND: DWC3 revision < 2.20a have an issue
1518 * which would cause metastability state on Run/Stop
1519 * bit if we try to force the IP to USB2-only mode.
1520 *
1521 * Because of that, we cannot configure the IP to any
1522 * speed other than the SuperSpeed
1523 *
1524 * Refers to:
1525 *
1526 * STAR#9000525659: Clock Domain Crossing on DCTL in
1527 * USB 2.0 Mode
1528 */
1529 if (dwc->revision < DWC3_REVISION_220A) {
1530 reg |= DWC3_DCFG_SUPERSPEED;
1531 } else {
1532 switch (dwc->maximum_speed) {
1533 case USB_SPEED_LOW:
1534 reg |= DWC3_DSTS_LOWSPEED;
1535 break;
1536 case USB_SPEED_FULL:
1537 reg |= DWC3_DSTS_FULLSPEED1;
1538 break;
1539 case USB_SPEED_HIGH:
1540 reg |= DWC3_DSTS_HIGHSPEED;
1541 break;
1542 case USB_SPEED_SUPER: /* FALLTHROUGH */
1543 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1544 default:
1545 reg |= DWC3_DSTS_SUPERSPEED;
1546 }
1547 }
1548 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1549
1550 dwc->start_config_issued = false;
1551
1552 /* Start with SuperSpeed Default */
1553 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1554
1555 dep = dwc->eps[0];
1556 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1557 if (ret) {
1558 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1559 goto err2;
1560 }
1561
1562 dep = dwc->eps[1];
1563 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1564 if (ret) {
1565 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1566 goto err3;
1567 }
1568
1569 /* begin to receive SETUP packets */
1570 dwc->ep0state = EP0_SETUP_PHASE;
1571 dwc3_ep0_out_start(dwc);
1572
1573 dwc3_gadget_enable_irq(dwc);
1574
1575 spin_unlock_irqrestore(&dwc->lock, flags);
1576
1577 return 0;
1578
1579 err3:
1580 __dwc3_gadget_ep_disable(dwc->eps[0]);
1581
1582 err2:
1583 dwc->gadget_driver = NULL;
1584
1585 err1:
1586 spin_unlock_irqrestore(&dwc->lock, flags);
1587
1588 free_irq(irq, dwc);
1589
1590 err0:
1591 return ret;
1592 }
1593
1594 static int dwc3_gadget_stop(struct usb_gadget *g,
1595 struct usb_gadget_driver *driver)
1596 {
1597 struct dwc3 *dwc = gadget_to_dwc(g);
1598 unsigned long flags;
1599 int irq;
1600
1601 spin_lock_irqsave(&dwc->lock, flags);
1602
1603 dwc3_gadget_disable_irq(dwc);
1604 __dwc3_gadget_ep_disable(dwc->eps[0]);
1605 __dwc3_gadget_ep_disable(dwc->eps[1]);
1606
1607 dwc->gadget_driver = NULL;
1608
1609 spin_unlock_irqrestore(&dwc->lock, flags);
1610
1611 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1612 free_irq(irq, dwc);
1613
1614 return 0;
1615 }
1616
1617 static const struct usb_gadget_ops dwc3_gadget_ops = {
1618 .get_frame = dwc3_gadget_get_frame,
1619 .wakeup = dwc3_gadget_wakeup,
1620 .set_selfpowered = dwc3_gadget_set_selfpowered,
1621 .pullup = dwc3_gadget_pullup,
1622 .udc_start = dwc3_gadget_start,
1623 .udc_stop = dwc3_gadget_stop,
1624 };
1625
1626 /* -------------------------------------------------------------------------- */
1627
1628 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1629 u8 num, u32 direction)
1630 {
1631 struct dwc3_ep *dep;
1632 u8 i;
1633
1634 for (i = 0; i < num; i++) {
1635 u8 epnum = (i << 1) | (!!direction);
1636
1637 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1638 if (!dep) {
1639 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1640 epnum);
1641 return -ENOMEM;
1642 }
1643
1644 dep->dwc = dwc;
1645 dep->number = epnum;
1646 dep->direction = !!direction;
1647 dwc->eps[epnum] = dep;
1648
1649 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1650 (epnum & 1) ? "in" : "out");
1651
1652 dep->endpoint.name = dep->name;
1653
1654 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1655
1656 if (epnum == 0 || epnum == 1) {
1657 dep->endpoint.maxpacket = 512;
1658 dep->endpoint.maxburst = 1;
1659 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1660 if (!epnum)
1661 dwc->gadget.ep0 = &dep->endpoint;
1662 } else {
1663 int ret;
1664
1665 dep->endpoint.maxpacket = 1024;
1666 dep->endpoint.max_streams = 15;
1667 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1668 list_add_tail(&dep->endpoint.ep_list,
1669 &dwc->gadget.ep_list);
1670
1671 ret = dwc3_alloc_trb_pool(dep);
1672 if (ret)
1673 return ret;
1674 }
1675
1676 INIT_LIST_HEAD(&dep->request_list);
1677 INIT_LIST_HEAD(&dep->req_queued);
1678 }
1679
1680 return 0;
1681 }
1682
1683 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1684 {
1685 int ret;
1686
1687 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1688
1689 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1690 if (ret < 0) {
1691 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1692 return ret;
1693 }
1694
1695 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1696 if (ret < 0) {
1697 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1698 return ret;
1699 }
1700
1701 return 0;
1702 }
1703
1704 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1705 {
1706 struct dwc3_ep *dep;
1707 u8 epnum;
1708
1709 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1710 dep = dwc->eps[epnum];
1711 if (!dep)
1712 continue;
1713 /*
1714 * Physical endpoints 0 and 1 are special; they form the
1715 * bi-directional USB endpoint 0.
1716 *
1717 * For those two physical endpoints, we don't allocate a TRB
1718 * pool nor do we add them the endpoints list. Due to that, we
1719 * shouldn't do these two operations otherwise we would end up
1720 * with all sorts of bugs when removing dwc3.ko.
1721 */
1722 if (epnum != 0 && epnum != 1) {
1723 dwc3_free_trb_pool(dep);
1724 list_del(&dep->endpoint.ep_list);
1725 }
1726
1727 kfree(dep);
1728 }
1729 }
1730
1731 /* -------------------------------------------------------------------------- */
1732
1733 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1734 struct dwc3_request *req, struct dwc3_trb *trb,
1735 const struct dwc3_event_depevt *event, int status)
1736 {
1737 unsigned int count;
1738 unsigned int s_pkt = 0;
1739 unsigned int trb_status;
1740
1741 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1742 /*
1743 * We continue despite the error. There is not much we
1744 * can do. If we don't clean it up we loop forever. If
1745 * we skip the TRB then it gets overwritten after a
1746 * while since we use them in a ring buffer. A BUG()
1747 * would help. Lets hope that if this occurs, someone
1748 * fixes the root cause instead of looking away :)
1749 */
1750 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1751 dep->name, trb);
1752 count = trb->size & DWC3_TRB_SIZE_MASK;
1753
1754 if (dep->direction) {
1755 if (count) {
1756 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1757 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1758 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1759 dep->name);
1760 /*
1761 * If missed isoc occurred and there is
1762 * no request queued then issue END
1763 * TRANSFER, so that core generates
1764 * next xfernotready and we will issue
1765 * a fresh START TRANSFER.
1766 * If there are still queued request
1767 * then wait, do not issue either END
1768 * or UPDATE TRANSFER, just attach next
1769 * request in request_list during
1770 * giveback.If any future queued request
1771 * is successfully transferred then we
1772 * will issue UPDATE TRANSFER for all
1773 * request in the request_list.
1774 */
1775 dep->flags |= DWC3_EP_MISSED_ISOC;
1776 } else {
1777 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1778 dep->name);
1779 status = -ECONNRESET;
1780 }
1781 } else {
1782 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1783 }
1784 } else {
1785 if (count && (event->status & DEPEVT_STATUS_SHORT))
1786 s_pkt = 1;
1787 }
1788
1789 /*
1790 * We assume here we will always receive the entire data block
1791 * which we should receive. Meaning, if we program RX to
1792 * receive 4K but we receive only 2K, we assume that's all we
1793 * should receive and we simply bounce the request back to the
1794 * gadget driver for further processing.
1795 */
1796 req->request.actual += req->request.length - count;
1797 if (s_pkt)
1798 return 1;
1799 if ((event->status & DEPEVT_STATUS_LST) &&
1800 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1801 DWC3_TRB_CTRL_HWO)))
1802 return 1;
1803 if ((event->status & DEPEVT_STATUS_IOC) &&
1804 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1805 return 1;
1806 return 0;
1807 }
1808
1809 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1810 const struct dwc3_event_depevt *event, int status)
1811 {
1812 struct dwc3_request *req;
1813 struct dwc3_trb *trb;
1814 unsigned int slot;
1815 unsigned int i;
1816 int ret;
1817
1818 do {
1819 req = next_request(&dep->req_queued);
1820 if (!req) {
1821 WARN_ON_ONCE(1);
1822 return 1;
1823 }
1824 i = 0;
1825 do {
1826 slot = req->start_slot + i;
1827 if ((slot == DWC3_TRB_NUM - 1) &&
1828 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1829 slot++;
1830 slot %= DWC3_TRB_NUM;
1831 trb = &dep->trb_pool[slot];
1832
1833 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1834 event, status);
1835 if (ret)
1836 break;
1837 }while (++i < req->request.num_mapped_sgs);
1838
1839 dwc3_gadget_giveback(dep, req, status);
1840
1841 if (ret)
1842 break;
1843 } while (1);
1844
1845 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1846 list_empty(&dep->req_queued)) {
1847 if (list_empty(&dep->request_list)) {
1848 /*
1849 * If there is no entry in request list then do
1850 * not issue END TRANSFER now. Just set PENDING
1851 * flag, so that END TRANSFER is issued when an
1852 * entry is added into request list.
1853 */
1854 dep->flags = DWC3_EP_PENDING_REQUEST;
1855 } else {
1856 dwc3_stop_active_transfer(dwc, dep->number);
1857 dep->flags = DWC3_EP_ENABLED;
1858 }
1859 return 1;
1860 }
1861
1862 if ((event->status & DEPEVT_STATUS_IOC) &&
1863 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1864 return 0;
1865 return 1;
1866 }
1867
1868 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1869 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1870 int start_new)
1871 {
1872 unsigned status = 0;
1873 int clean_busy;
1874
1875 if (event->status & DEPEVT_STATUS_BUSERR)
1876 status = -ECONNRESET;
1877
1878 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1879 if (clean_busy)
1880 dep->flags &= ~DWC3_EP_BUSY;
1881
1882 /*
1883 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1884 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1885 */
1886 if (dwc->revision < DWC3_REVISION_183A) {
1887 u32 reg;
1888 int i;
1889
1890 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1891 dep = dwc->eps[i];
1892
1893 if (!(dep->flags & DWC3_EP_ENABLED))
1894 continue;
1895
1896 if (!list_empty(&dep->req_queued))
1897 return;
1898 }
1899
1900 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1901 reg |= dwc->u1u2;
1902 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1903
1904 dwc->u1u2 = 0;
1905 }
1906 }
1907
1908 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1909 const struct dwc3_event_depevt *event)
1910 {
1911 struct dwc3_ep *dep;
1912 u8 epnum = event->endpoint_number;
1913
1914 dep = dwc->eps[epnum];
1915
1916 if (!(dep->flags & DWC3_EP_ENABLED))
1917 return;
1918
1919 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1920 dwc3_ep_event_string(event->endpoint_event));
1921
1922 if (epnum == 0 || epnum == 1) {
1923 dwc3_ep0_interrupt(dwc, event);
1924 return;
1925 }
1926
1927 switch (event->endpoint_event) {
1928 case DWC3_DEPEVT_XFERCOMPLETE:
1929 dep->resource_index = 0;
1930
1931 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1932 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1933 dep->name);
1934 return;
1935 }
1936
1937 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1938 break;
1939 case DWC3_DEPEVT_XFERINPROGRESS:
1940 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1941 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1942 dep->name);
1943 return;
1944 }
1945
1946 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1947 break;
1948 case DWC3_DEPEVT_XFERNOTREADY:
1949 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1950 dwc3_gadget_start_isoc(dwc, dep, event);
1951 } else {
1952 int ret;
1953
1954 dev_vdbg(dwc->dev, "%s: reason %s\n",
1955 dep->name, event->status &
1956 DEPEVT_STATUS_TRANSFER_ACTIVE
1957 ? "Transfer Active"
1958 : "Transfer Not Active");
1959
1960 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1961 if (!ret || ret == -EBUSY)
1962 return;
1963
1964 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1965 dep->name);
1966 }
1967
1968 break;
1969 case DWC3_DEPEVT_STREAMEVT:
1970 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1971 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1972 dep->name);
1973 return;
1974 }
1975
1976 switch (event->status) {
1977 case DEPEVT_STREAMEVT_FOUND:
1978 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1979 event->parameters);
1980
1981 break;
1982 case DEPEVT_STREAMEVT_NOTFOUND:
1983 /* FALLTHROUGH */
1984 default:
1985 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1986 }
1987 break;
1988 case DWC3_DEPEVT_RXTXFIFOEVT:
1989 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1990 break;
1991 case DWC3_DEPEVT_EPCMDCMPLT:
1992 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1993 break;
1994 }
1995 }
1996
1997 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1998 {
1999 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2000 spin_unlock(&dwc->lock);
2001 dwc->gadget_driver->disconnect(&dwc->gadget);
2002 spin_lock(&dwc->lock);
2003 }
2004 }
2005
2006 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2007 {
2008 struct dwc3_ep *dep;
2009 struct dwc3_gadget_ep_cmd_params params;
2010 u32 cmd;
2011 int ret;
2012
2013 dep = dwc->eps[epnum];
2014
2015 if (!dep->resource_index)
2016 return;
2017
2018 /*
2019 * NOTICE: We are violating what the Databook says about the
2020 * EndTransfer command. Ideally we would _always_ wait for the
2021 * EndTransfer Command Completion IRQ, but that's causing too
2022 * much trouble synchronizing between us and gadget driver.
2023 *
2024 * We have discussed this with the IP Provider and it was
2025 * suggested to giveback all requests here, but give HW some
2026 * extra time to synchronize with the interconnect. We're using
2027 * an arbitraty 100us delay for that.
2028 *
2029 * Note also that a similar handling was tested by Synopsys
2030 * (thanks a lot Paul) and nothing bad has come out of it.
2031 * In short, what we're doing is:
2032 *
2033 * - Issue EndTransfer WITH CMDIOC bit set
2034 * - Wait 100us
2035 */
2036
2037 cmd = DWC3_DEPCMD_ENDTRANSFER;
2038 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2039 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2040 memset(&params, 0, sizeof(params));
2041 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2042 WARN_ON_ONCE(ret);
2043 dep->resource_index = 0;
2044 dep->flags &= ~DWC3_EP_BUSY;
2045 udelay(100);
2046 }
2047
2048 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2049 {
2050 u32 epnum;
2051
2052 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2053 struct dwc3_ep *dep;
2054
2055 dep = dwc->eps[epnum];
2056 if (!dep)
2057 continue;
2058
2059 if (!(dep->flags & DWC3_EP_ENABLED))
2060 continue;
2061
2062 dwc3_remove_requests(dwc, dep);
2063 }
2064 }
2065
2066 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2067 {
2068 u32 epnum;
2069
2070 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2071 struct dwc3_ep *dep;
2072 struct dwc3_gadget_ep_cmd_params params;
2073 int ret;
2074
2075 dep = dwc->eps[epnum];
2076 if (!dep)
2077 continue;
2078
2079 if (!(dep->flags & DWC3_EP_STALL))
2080 continue;
2081
2082 dep->flags &= ~DWC3_EP_STALL;
2083
2084 memset(&params, 0, sizeof(params));
2085 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2086 DWC3_DEPCMD_CLEARSTALL, &params);
2087 WARN_ON_ONCE(ret);
2088 }
2089 }
2090
2091 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2092 {
2093 int reg;
2094
2095 dev_vdbg(dwc->dev, "%s\n", __func__);
2096
2097 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2098 reg &= ~DWC3_DCTL_INITU1ENA;
2099 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2100
2101 reg &= ~DWC3_DCTL_INITU2ENA;
2102 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2103
2104 dwc3_disconnect_gadget(dwc);
2105 dwc->start_config_issued = false;
2106
2107 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2108 dwc->setup_packet_pending = false;
2109 }
2110
2111 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2112 {
2113 u32 reg;
2114
2115 dev_vdbg(dwc->dev, "%s\n", __func__);
2116
2117 /*
2118 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2119 * would cause a missing Disconnect Event if there's a
2120 * pending Setup Packet in the FIFO.
2121 *
2122 * There's no suggested workaround on the official Bug
2123 * report, which states that "unless the driver/application
2124 * is doing any special handling of a disconnect event,
2125 * there is no functional issue".
2126 *
2127 * Unfortunately, it turns out that we _do_ some special
2128 * handling of a disconnect event, namely complete all
2129 * pending transfers, notify gadget driver of the
2130 * disconnection, and so on.
2131 *
2132 * Our suggested workaround is to follow the Disconnect
2133 * Event steps here, instead, based on a setup_packet_pending
2134 * flag. Such flag gets set whenever we have a XferNotReady
2135 * event on EP0 and gets cleared on XferComplete for the
2136 * same endpoint.
2137 *
2138 * Refers to:
2139 *
2140 * STAR#9000466709: RTL: Device : Disconnect event not
2141 * generated if setup packet pending in FIFO
2142 */
2143 if (dwc->revision < DWC3_REVISION_188A) {
2144 if (dwc->setup_packet_pending)
2145 dwc3_gadget_disconnect_interrupt(dwc);
2146 }
2147
2148 /* after reset -> Default State */
2149 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2150
2151 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2152 dwc3_disconnect_gadget(dwc);
2153
2154 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2155 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2156 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2157 dwc->test_mode = false;
2158
2159 dwc3_stop_active_transfers(dwc);
2160 dwc3_clear_stall_all_ep(dwc);
2161 dwc->start_config_issued = false;
2162
2163 /* Reset device address to zero */
2164 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2165 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2166 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2167 }
2168
2169 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2170 {
2171 u32 reg;
2172 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2173
2174 /*
2175 * We change the clock only at SS but I dunno why I would want to do
2176 * this. Maybe it becomes part of the power saving plan.
2177 */
2178
2179 if (speed != DWC3_DSTS_SUPERSPEED)
2180 return;
2181
2182 /*
2183 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2184 * each time on Connect Done.
2185 */
2186 if (!usb30_clock)
2187 return;
2188
2189 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2190 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2191 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2192 }
2193
2194 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2195 {
2196 struct dwc3_ep *dep;
2197 int ret;
2198 u32 reg;
2199 u8 speed;
2200
2201 dev_vdbg(dwc->dev, "%s\n", __func__);
2202
2203 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2204 speed = reg & DWC3_DSTS_CONNECTSPD;
2205 dwc->speed = speed;
2206
2207 dwc3_update_ram_clk_sel(dwc, speed);
2208
2209 switch (speed) {
2210 case DWC3_DCFG_SUPERSPEED:
2211 /*
2212 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2213 * would cause a missing USB3 Reset event.
2214 *
2215 * In such situations, we should force a USB3 Reset
2216 * event by calling our dwc3_gadget_reset_interrupt()
2217 * routine.
2218 *
2219 * Refers to:
2220 *
2221 * STAR#9000483510: RTL: SS : USB3 reset event may
2222 * not be generated always when the link enters poll
2223 */
2224 if (dwc->revision < DWC3_REVISION_190A)
2225 dwc3_gadget_reset_interrupt(dwc);
2226
2227 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2228 dwc->gadget.ep0->maxpacket = 512;
2229 dwc->gadget.speed = USB_SPEED_SUPER;
2230 break;
2231 case DWC3_DCFG_HIGHSPEED:
2232 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2233 dwc->gadget.ep0->maxpacket = 64;
2234 dwc->gadget.speed = USB_SPEED_HIGH;
2235 break;
2236 case DWC3_DCFG_FULLSPEED2:
2237 case DWC3_DCFG_FULLSPEED1:
2238 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2239 dwc->gadget.ep0->maxpacket = 64;
2240 dwc->gadget.speed = USB_SPEED_FULL;
2241 break;
2242 case DWC3_DCFG_LOWSPEED:
2243 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2244 dwc->gadget.ep0->maxpacket = 8;
2245 dwc->gadget.speed = USB_SPEED_LOW;
2246 break;
2247 }
2248
2249 /* Enable USB2 LPM Capability */
2250
2251 if ((dwc->revision > DWC3_REVISION_194A)
2252 && (speed != DWC3_DCFG_SUPERSPEED)) {
2253 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2254 reg |= DWC3_DCFG_LPM_CAP;
2255 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2256
2257 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2258 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2259
2260 /*
2261 * TODO: This should be configurable. For now using
2262 * maximum allowed HIRD threshold value of 0b1100
2263 */
2264 reg |= DWC3_DCTL_HIRD_THRES(12);
2265
2266 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2267 }
2268
2269 dep = dwc->eps[0];
2270 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2271 if (ret) {
2272 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2273 return;
2274 }
2275
2276 dep = dwc->eps[1];
2277 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2278 if (ret) {
2279 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2280 return;
2281 }
2282
2283 /*
2284 * Configure PHY via GUSB3PIPECTLn if required.
2285 *
2286 * Update GTXFIFOSIZn
2287 *
2288 * In both cases reset values should be sufficient.
2289 */
2290 }
2291
2292 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2293 {
2294 dev_vdbg(dwc->dev, "%s\n", __func__);
2295
2296 /*
2297 * TODO take core out of low power mode when that's
2298 * implemented.
2299 */
2300
2301 dwc->gadget_driver->resume(&dwc->gadget);
2302 }
2303
2304 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2305 unsigned int evtinfo)
2306 {
2307 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2308 unsigned int pwropt;
2309
2310 /*
2311 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2312 * Hibernation mode enabled which would show up when device detects
2313 * host-initiated U3 exit.
2314 *
2315 * In that case, device will generate a Link State Change Interrupt
2316 * from U3 to RESUME which is only necessary if Hibernation is
2317 * configured in.
2318 *
2319 * There are no functional changes due to such spurious event and we
2320 * just need to ignore it.
2321 *
2322 * Refers to:
2323 *
2324 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2325 * operational mode
2326 */
2327 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2328 if ((dwc->revision < DWC3_REVISION_250A) &&
2329 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2330 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2331 (next == DWC3_LINK_STATE_RESUME)) {
2332 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2333 return;
2334 }
2335 }
2336
2337 /*
2338 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2339 * on the link partner, the USB session might do multiple entry/exit
2340 * of low power states before a transfer takes place.
2341 *
2342 * Due to this problem, we might experience lower throughput. The
2343 * suggested workaround is to disable DCTL[12:9] bits if we're
2344 * transitioning from U1/U2 to U0 and enable those bits again
2345 * after a transfer completes and there are no pending transfers
2346 * on any of the enabled endpoints.
2347 *
2348 * This is the first half of that workaround.
2349 *
2350 * Refers to:
2351 *
2352 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2353 * core send LGO_Ux entering U0
2354 */
2355 if (dwc->revision < DWC3_REVISION_183A) {
2356 if (next == DWC3_LINK_STATE_U0) {
2357 u32 u1u2;
2358 u32 reg;
2359
2360 switch (dwc->link_state) {
2361 case DWC3_LINK_STATE_U1:
2362 case DWC3_LINK_STATE_U2:
2363 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2364 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2365 | DWC3_DCTL_ACCEPTU2ENA
2366 | DWC3_DCTL_INITU1ENA
2367 | DWC3_DCTL_ACCEPTU1ENA);
2368
2369 if (!dwc->u1u2)
2370 dwc->u1u2 = reg & u1u2;
2371
2372 reg &= ~u1u2;
2373
2374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2375 break;
2376 default:
2377 /* do nothing */
2378 break;
2379 }
2380 }
2381 }
2382
2383 dwc->link_state = next;
2384
2385 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2386 }
2387
2388 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2389 const struct dwc3_event_devt *event)
2390 {
2391 switch (event->type) {
2392 case DWC3_DEVICE_EVENT_DISCONNECT:
2393 dwc3_gadget_disconnect_interrupt(dwc);
2394 break;
2395 case DWC3_DEVICE_EVENT_RESET:
2396 dwc3_gadget_reset_interrupt(dwc);
2397 break;
2398 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2399 dwc3_gadget_conndone_interrupt(dwc);
2400 break;
2401 case DWC3_DEVICE_EVENT_WAKEUP:
2402 dwc3_gadget_wakeup_interrupt(dwc);
2403 break;
2404 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2405 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2406 break;
2407 case DWC3_DEVICE_EVENT_EOPF:
2408 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2409 break;
2410 case DWC3_DEVICE_EVENT_SOF:
2411 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2412 break;
2413 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2414 dev_vdbg(dwc->dev, "Erratic Error\n");
2415 break;
2416 case DWC3_DEVICE_EVENT_CMD_CMPL:
2417 dev_vdbg(dwc->dev, "Command Complete\n");
2418 break;
2419 case DWC3_DEVICE_EVENT_OVERFLOW:
2420 dev_vdbg(dwc->dev, "Overflow\n");
2421 break;
2422 default:
2423 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2424 }
2425 }
2426
2427 static void dwc3_process_event_entry(struct dwc3 *dwc,
2428 const union dwc3_event *event)
2429 {
2430 /* Endpoint IRQ, handle it and return early */
2431 if (event->type.is_devspec == 0) {
2432 /* depevt */
2433 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2434 }
2435
2436 switch (event->type.type) {
2437 case DWC3_EVENT_TYPE_DEV:
2438 dwc3_gadget_interrupt(dwc, &event->devt);
2439 break;
2440 /* REVISIT what to do with Carkit and I2C events ? */
2441 default:
2442 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2443 }
2444 }
2445
2446 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2447 {
2448 struct dwc3_event_buffer *evt;
2449 irqreturn_t ret = IRQ_NONE;
2450 int left;
2451 u32 reg;
2452
2453 evt = dwc->ev_buffs[buf];
2454 left = evt->count;
2455
2456 if (!(evt->flags & DWC3_EVENT_PENDING))
2457 return IRQ_NONE;
2458
2459 while (left > 0) {
2460 union dwc3_event event;
2461
2462 event.raw = *(u32 *) (evt->buf + evt->lpos);
2463
2464 dwc3_process_event_entry(dwc, &event);
2465
2466 /*
2467 * FIXME we wrap around correctly to the next entry as
2468 * almost all entries are 4 bytes in size. There is one
2469 * entry which has 12 bytes which is a regular entry
2470 * followed by 8 bytes data. ATM I don't know how
2471 * things are organized if we get next to the a
2472 * boundary so I worry about that once we try to handle
2473 * that.
2474 */
2475 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2476 left -= 4;
2477
2478 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2479 }
2480
2481 evt->count = 0;
2482 evt->flags &= ~DWC3_EVENT_PENDING;
2483 ret = IRQ_HANDLED;
2484
2485 /* Unmask interrupt */
2486 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2487 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2488 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2489
2490 return ret;
2491 }
2492
2493 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2494 {
2495 struct dwc3 *dwc = _dwc;
2496 unsigned long flags;
2497 irqreturn_t ret = IRQ_NONE;
2498 int i;
2499
2500 spin_lock_irqsave(&dwc->lock, flags);
2501
2502 for (i = 0; i < dwc->num_event_buffers; i++)
2503 ret |= dwc3_process_event_buf(dwc, i);
2504
2505 spin_unlock_irqrestore(&dwc->lock, flags);
2506
2507 return ret;
2508 }
2509
2510 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2511 {
2512 struct dwc3_event_buffer *evt;
2513 u32 count;
2514 u32 reg;
2515
2516 evt = dwc->ev_buffs[buf];
2517
2518 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2519 count &= DWC3_GEVNTCOUNT_MASK;
2520 if (!count)
2521 return IRQ_NONE;
2522
2523 evt->count = count;
2524 evt->flags |= DWC3_EVENT_PENDING;
2525
2526 /* Mask interrupt */
2527 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2528 reg |= DWC3_GEVNTSIZ_INTMASK;
2529 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2530
2531 return IRQ_WAKE_THREAD;
2532 }
2533
2534 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2535 {
2536 struct dwc3 *dwc = _dwc;
2537 int i;
2538 irqreturn_t ret = IRQ_NONE;
2539
2540 spin_lock(&dwc->lock);
2541
2542 for (i = 0; i < dwc->num_event_buffers; i++) {
2543 irqreturn_t status;
2544
2545 status = dwc3_check_event_buf(dwc, i);
2546 if (status == IRQ_WAKE_THREAD)
2547 ret = status;
2548 }
2549
2550 spin_unlock(&dwc->lock);
2551
2552 return ret;
2553 }
2554
2555 /**
2556 * dwc3_gadget_init - Initializes gadget related registers
2557 * @dwc: pointer to our controller context structure
2558 *
2559 * Returns 0 on success otherwise negative errno.
2560 */
2561 int dwc3_gadget_init(struct dwc3 *dwc)
2562 {
2563 int ret;
2564
2565 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2566 &dwc->ctrl_req_addr, GFP_KERNEL);
2567 if (!dwc->ctrl_req) {
2568 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2569 ret = -ENOMEM;
2570 goto err0;
2571 }
2572
2573 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2574 &dwc->ep0_trb_addr, GFP_KERNEL);
2575 if (!dwc->ep0_trb) {
2576 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2577 ret = -ENOMEM;
2578 goto err1;
2579 }
2580
2581 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2582 if (!dwc->setup_buf) {
2583 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2584 ret = -ENOMEM;
2585 goto err2;
2586 }
2587
2588 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2589 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2590 GFP_KERNEL);
2591 if (!dwc->ep0_bounce) {
2592 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2593 ret = -ENOMEM;
2594 goto err3;
2595 }
2596
2597 dwc->gadget.ops = &dwc3_gadget_ops;
2598 dwc->gadget.max_speed = USB_SPEED_SUPER;
2599 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2600 dwc->gadget.sg_supported = true;
2601 dwc->gadget.name = "dwc3-gadget";
2602
2603 /*
2604 * REVISIT: Here we should clear all pending IRQs to be
2605 * sure we're starting from a well known location.
2606 */
2607
2608 ret = dwc3_gadget_init_endpoints(dwc);
2609 if (ret)
2610 goto err4;
2611
2612 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2613 if (ret) {
2614 dev_err(dwc->dev, "failed to register udc\n");
2615 goto err4;
2616 }
2617
2618 return 0;
2619
2620 err4:
2621 dwc3_gadget_free_endpoints(dwc);
2622 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2623 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2624
2625 err3:
2626 kfree(dwc->setup_buf);
2627
2628 err2:
2629 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2630 dwc->ep0_trb, dwc->ep0_trb_addr);
2631
2632 err1:
2633 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2634 dwc->ctrl_req, dwc->ctrl_req_addr);
2635
2636 err0:
2637 return ret;
2638 }
2639
2640 /* -------------------------------------------------------------------------- */
2641
2642 void dwc3_gadget_exit(struct dwc3 *dwc)
2643 {
2644 usb_del_gadget_udc(&dwc->gadget);
2645
2646 dwc3_gadget_free_endpoints(dwc);
2647
2648 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2649 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2650
2651 kfree(dwc->setup_buf);
2652
2653 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2654 dwc->ep0_trb, dwc->ep0_trb_addr);
2655
2656 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2657 dwc->ctrl_req, dwc->ctrl_req_addr);
2658 }
2659
2660 int dwc3_gadget_prepare(struct dwc3 *dwc)
2661 {
2662 if (dwc->pullups_connected)
2663 dwc3_gadget_disable_irq(dwc);
2664
2665 return 0;
2666 }
2667
2668 void dwc3_gadget_complete(struct dwc3 *dwc)
2669 {
2670 if (dwc->pullups_connected) {
2671 dwc3_gadget_enable_irq(dwc);
2672 dwc3_gadget_run_stop(dwc, true);
2673 }
2674 }
2675
2676 int dwc3_gadget_suspend(struct dwc3 *dwc)
2677 {
2678 __dwc3_gadget_ep_disable(dwc->eps[0]);
2679 __dwc3_gadget_ep_disable(dwc->eps[1]);
2680
2681 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2682
2683 return 0;
2684 }
2685
2686 int dwc3_gadget_resume(struct dwc3 *dwc)
2687 {
2688 struct dwc3_ep *dep;
2689 int ret;
2690
2691 /* Start with SuperSpeed Default */
2692 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2693
2694 dep = dwc->eps[0];
2695 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2696 if (ret)
2697 goto err0;
2698
2699 dep = dwc->eps[1];
2700 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2701 if (ret)
2702 goto err1;
2703
2704 /* begin to receive SETUP packets */
2705 dwc->ep0state = EP0_SETUP_PHASE;
2706 dwc3_ep0_out_start(dwc);
2707
2708 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2709
2710 return 0;
2711
2712 err1:
2713 __dwc3_gadget_ep_disable(dwc->eps[0]);
2714
2715 err0:
2716 return ret;
2717 }
Linux with added FPC-III support