drivers/usb/musb/musb_cppi41.c

   1 #include <linux/device.h>
   2 #include <linux/dma-mapping.h>
   3 #include <linux/dmaengine.h>
   4 #include <linux/sizes.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/of.h>
   7
   8 #include "musb_core.h"
   9
  10 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
  11
  12 #define EP_MODE_AUTOREG_NONE            0
  13 #define EP_MODE_AUTOREG_ALL_NEOP        1
  14 #define EP_MODE_AUTOREG_ALWAYS          3
  15
  16 #define EP_MODE_DMA_TRANSPARENT         0
  17 #define EP_MODE_DMA_RNDIS               1
  18 #define EP_MODE_DMA_GEN_RNDIS           3
  19
  20 #define USB_CTRL_TX_MODE        0x70
  21 #define USB_CTRL_RX_MODE        0x74
  22 #define USB_CTRL_AUTOREQ        0xd0
  23 #define USB_TDOWN               0xd8
  24
  25 struct cppi41_dma_channel {
  26         struct dma_channel channel;
  27         struct cppi41_dma_controller *controller;
  28         struct musb_hw_ep *hw_ep;
  29         struct dma_chan *dc;
  30         dma_cookie_t cookie;
  31         u8 port_num;
  32         u8 is_tx;
  33         u8 is_allocated;
  34         u8 usb_toggle;
  35
  36         dma_addr_t buf_addr;
  37         u32 total_len;
  38         u32 prog_len;
  39         u32 transferred;
  40         u32 packet_sz;
  41         struct list_head tx_check;
  42 };
  43
  44 #define MUSB_DMA_NUM_CHANNELS 15
  45
  46 struct cppi41_dma_controller {
  47         struct dma_controller controller;
  48         struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
  49         struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
  50         struct musb *musb;
  51         struct hrtimer early_tx;
  52         struct list_head early_tx_list;
  53         u32 rx_mode;
  54         u32 tx_mode;
  55         u32 auto_req;
  56 };
  57
  58 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  59 {
  60         u16 csr;
  61         u8 toggle;
  62
  63         if (cppi41_channel->is_tx)
  64                 return;
  65         if (!is_host_active(cppi41_channel->controller->musb))
  66                 return;
  67
  68         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  69         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  70
  71         cppi41_channel->usb_toggle = toggle;
  72 }
  73
  74 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  75 {
  76         u16 csr;
  77         u8 toggle;
  78
  79         if (cppi41_channel->is_tx)
  80                 return;
  81         if (!is_host_active(cppi41_channel->controller->musb))
  82                 return;
  83
  84         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  85         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  86
  87         /*
  88          * AM335x Advisory 1.0.13: Due to internal synchronisation error the
  89          * data toggle may reset from DATA1 to DATA0 during receiving data from
  90          * more than one endpoint.
  91          */
  92         if (!toggle && toggle == cppi41_channel->usb_toggle) {
  93                 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
  94                 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
  95                 dev_dbg(cppi41_channel->controller->musb->controller,
  96                                 "Restoring DATA1 toggle.\n");
  97         }
  98
  99         cppi41_channel->usb_toggle = toggle;
 100 }
 101
 102 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
 103 {
 104         u8              epnum = hw_ep->epnum;
 105         struct musb     *musb = hw_ep->musb;
 106         void __iomem    *epio = musb->endpoints[epnum].regs;
 107         u16             csr;
 108
 109         csr = musb_readw(epio, MUSB_TXCSR);
 110         if (csr & MUSB_TXCSR_TXPKTRDY)
 111                 return false;
 112         return true;
 113 }
 114
 115 static void cppi41_dma_callback(void *private_data);
 116
 117 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
 118 {
 119         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 120         struct musb *musb = hw_ep->musb;
 121
 122         if (!cppi41_channel->prog_len) {
 123
 124                 /* done, complete */
 125                 cppi41_channel->channel.actual_len =
 126                         cppi41_channel->transferred;
 127                 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 128                 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
 129         } else {
 130                 /* next iteration, reload */
 131                 struct dma_chan *dc = cppi41_channel->dc;
 132                 struct dma_async_tx_descriptor *dma_desc;
 133                 enum dma_transfer_direction direction;
 134                 u16 csr;
 135                 u32 remain_bytes;
 136                 void __iomem *epio = cppi41_channel->hw_ep->regs;
 137
 138                 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
 139
 140                 remain_bytes = cppi41_channel->total_len;
 141                 remain_bytes -= cppi41_channel->transferred;
 142                 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
 143                 cppi41_channel->prog_len = remain_bytes;
 144
 145                 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
 146                         : DMA_DEV_TO_MEM;
 147                 dma_desc = dmaengine_prep_slave_single(dc,
 148                                 cppi41_channel->buf_addr,
 149                                 remain_bytes,
 150                                 direction,
 151                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 152                 if (WARN_ON(!dma_desc))
 153                         return;
 154
 155                 dma_desc->callback = cppi41_dma_callback;
 156                 dma_desc->callback_param = &cppi41_channel->channel;
 157                 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 158                 dma_async_issue_pending(dc);
 159
 160                 if (!cppi41_channel->is_tx) {
 161                         csr = musb_readw(epio, MUSB_RXCSR);
 162                         csr |= MUSB_RXCSR_H_REQPKT;
 163                         musb_writew(epio, MUSB_RXCSR, csr);
 164                 }
 165         }
 166 }
 167
 168 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
 169 {
 170         struct cppi41_dma_controller *controller;
 171         struct cppi41_dma_channel *cppi41_channel, *n;
 172         struct musb *musb;
 173         unsigned long flags;
 174         enum hrtimer_restart ret = HRTIMER_NORESTART;
 175
 176         controller = container_of(timer, struct cppi41_dma_controller,
 177                         early_tx);
 178         musb = controller->musb;
 179
 180         spin_lock_irqsave(&musb->lock, flags);
 181         list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
 182                         tx_check) {
 183                 bool empty;
 184                 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 185
 186                 empty = musb_is_tx_fifo_empty(hw_ep);
 187                 if (empty) {
 188                         list_del_init(&cppi41_channel->tx_check);
 189                         cppi41_trans_done(cppi41_channel);
 190                 }
 191         }
 192
 193         if (!list_empty(&controller->early_tx_list)) {
 194                 ret = HRTIMER_RESTART;
 195                 hrtimer_forward_now(&controller->early_tx,
 196                                 ktime_set(0, 50 * NSEC_PER_USEC));
 197         }
 198
 199         spin_unlock_irqrestore(&musb->lock, flags);
 200         return ret;
 201 }
 202
 203 static void cppi41_dma_callback(void *private_data)
 204 {
 205         struct dma_channel *channel = private_data;
 206         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 207         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 208         struct musb *musb = hw_ep->musb;
 209         unsigned long flags;
 210         struct dma_tx_state txstate;
 211         u32 transferred;
 212         bool empty;
 213
 214         spin_lock_irqsave(&musb->lock, flags);
 215
 216         dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
 217                         &txstate);
 218         transferred = cppi41_channel->prog_len - txstate.residue;
 219         cppi41_channel->transferred += transferred;
 220
 221         dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
 222                 hw_ep->epnum, cppi41_channel->transferred,
 223                 cppi41_channel->total_len);
 224
 225         update_rx_toggle(cppi41_channel);
 226
 227         if (cppi41_channel->transferred == cppi41_channel->total_len ||
 228                         transferred < cppi41_channel->packet_sz)
 229                 cppi41_channel->prog_len = 0;
 230
 231         empty = musb_is_tx_fifo_empty(hw_ep);
 232         if (empty) {
 233                 cppi41_trans_done(cppi41_channel);
 234         } else {
 235                 struct cppi41_dma_controller *controller;
 236                 /*
 237                  * On AM335x it has been observed that the TX interrupt fires
 238                  * too early that means the TXFIFO is not yet empty but the DMA
 239                  * engine says that it is done with the transfer. We don't
 240                  * receive a FIFO empty interrupt so the only thing we can do is
 241                  * to poll for the bit. On HS it usually takes 2us, on FS around
 242                  * 110us - 150us depending on the transfer size.
 243                  * We spin on HS (no longer than than 25us and setup a timer on
 244                  * FS to check for the bit and complete the transfer.
 245                  */
 246                 controller = cppi41_channel->controller;
 247
 248                 if (musb->g.speed == USB_SPEED_HIGH) {
 249                         unsigned wait = 25;
 250
 251                         do {
 252                                 empty = musb_is_tx_fifo_empty(hw_ep);
 253                                 if (empty)
 254                                         break;
 255                                 wait--;
 256                                 if (!wait)
 257                                         break;
 258                                 udelay(1);
 259                         } while (1);
 260
 261                         empty = musb_is_tx_fifo_empty(hw_ep);
 262                         if (empty) {
 263                                 cppi41_trans_done(cppi41_channel);
 264                                 goto out;
 265                         }
 266                 }
 267                 list_add_tail(&cppi41_channel->tx_check,
 268                                 &controller->early_tx_list);
 269                 if (!hrtimer_is_queued(&controller->early_tx)) {
 270                         unsigned long usecs = cppi41_channel->total_len / 10;
 271
 272                         hrtimer_start_range_ns(&controller->early_tx,
 273                                 ktime_set(0, usecs * NSEC_PER_USEC),
 274                                 40 * NSEC_PER_USEC,
 275                                 HRTIMER_MODE_REL);
 276                 }
 277         }
 278 out:
 279         spin_unlock_irqrestore(&musb->lock, flags);
 280 }
 281
 282 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
 283 {
 284         unsigned shift;
 285
 286         shift = (ep - 1) * 2;
 287         old &= ~(3 << shift);
 288         old |= mode << shift;
 289         return old;
 290 }
 291
 292 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
 293                 unsigned mode)
 294 {
 295         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 296         u32 port;
 297         u32 new_mode;
 298         u32 old_mode;
 299
 300         if (cppi41_channel->is_tx)
 301                 old_mode = controller->tx_mode;
 302         else
 303                 old_mode = controller->rx_mode;
 304         port = cppi41_channel->port_num;
 305         new_mode = update_ep_mode(port, mode, old_mode);
 306
 307         if (new_mode == old_mode)
 308                 return;
 309         if (cppi41_channel->is_tx) {
 310                 controller->tx_mode = new_mode;
 311                 musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
 312                                 new_mode);
 313         } else {
 314                 controller->rx_mode = new_mode;
 315                 musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
 316                                 new_mode);
 317         }
 318 }
 319
 320 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
 321                 unsigned mode)
 322 {
 323         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 324         u32 port;
 325         u32 new_mode;
 326         u32 old_mode;
 327
 328         old_mode = controller->auto_req;
 329         port = cppi41_channel->port_num;
 330         new_mode = update_ep_mode(port, mode, old_mode);
 331
 332         if (new_mode == old_mode)
 333                 return;
 334         controller->auto_req = new_mode;
 335         musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
 336 }
 337
 338 static bool cppi41_configure_channel(struct dma_channel *channel,
 339                                 u16 packet_sz, u8 mode,
 340                                 dma_addr_t dma_addr, u32 len)
 341 {
 342         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 343         struct dma_chan *dc = cppi41_channel->dc;
 344         struct dma_async_tx_descriptor *dma_desc;
 345         enum dma_transfer_direction direction;
 346         struct musb *musb = cppi41_channel->controller->musb;
 347         unsigned use_gen_rndis = 0;
 348
 349         dev_dbg(musb->controller,
 350                 "configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
 351                 cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
 352                 packet_sz, mode, (unsigned long long) dma_addr,
 353                 len, cppi41_channel->is_tx);
 354
 355         cppi41_channel->buf_addr = dma_addr;
 356         cppi41_channel->total_len = len;
 357         cppi41_channel->transferred = 0;
 358         cppi41_channel->packet_sz = packet_sz;
 359
 360         /*
 361          * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
 362          * than max packet size at a time.
 363          */
 364         if (cppi41_channel->is_tx)
 365                 use_gen_rndis = 1;
 366
 367         if (use_gen_rndis) {
 368                 /* RNDIS mode */
 369                 if (len > packet_sz) {
 370                         musb_writel(musb->ctrl_base,
 371                                 RNDIS_REG(cppi41_channel->port_num), len);
 372                         /* gen rndis */
 373                         cppi41_set_dma_mode(cppi41_channel,
 374                                         EP_MODE_DMA_GEN_RNDIS);
 375
 376                         /* auto req */
 377                         cppi41_set_autoreq_mode(cppi41_channel,
 378                                         EP_MODE_AUTOREG_ALL_NEOP);
 379                 } else {
 380                         musb_writel(musb->ctrl_base,
 381                                         RNDIS_REG(cppi41_channel->port_num), 0);
 382                         cppi41_set_dma_mode(cppi41_channel,
 383                                         EP_MODE_DMA_TRANSPARENT);
 384                         cppi41_set_autoreq_mode(cppi41_channel,
 385                                         EP_MODE_AUTOREG_NONE);
 386                 }
 387         } else {
 388                 /* fallback mode */
 389                 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
 390                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
 391                 len = min_t(u32, packet_sz, len);
 392         }
 393         cppi41_channel->prog_len = len;
 394         direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 395         dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
 396                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 397         if (!dma_desc)
 398                 return false;
 399
 400         dma_desc->callback = cppi41_dma_callback;
 401         dma_desc->callback_param = channel;
 402         cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 403
 404         save_rx_toggle(cppi41_channel);
 405         dma_async_issue_pending(dc);
 406         return true;
 407 }
 408
 409 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
 410                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 411 {
 412         struct cppi41_dma_controller *controller = container_of(c,
 413                         struct cppi41_dma_controller, controller);
 414         struct cppi41_dma_channel *cppi41_channel = NULL;
 415         u8 ch_num = hw_ep->epnum - 1;
 416
 417         if (ch_num >= MUSB_DMA_NUM_CHANNELS)
 418                 return NULL;
 419
 420         if (is_tx)
 421                 cppi41_channel = &controller->tx_channel[ch_num];
 422         else
 423                 cppi41_channel = &controller->rx_channel[ch_num];
 424
 425         if (!cppi41_channel->dc)
 426                 return NULL;
 427
 428         if (cppi41_channel->is_allocated)
 429                 return NULL;
 430
 431         cppi41_channel->hw_ep = hw_ep;
 432         cppi41_channel->is_allocated = 1;
 433
 434         return &cppi41_channel->channel;
 435 }
 436
 437 static void cppi41_dma_channel_release(struct dma_channel *channel)
 438 {
 439         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 440
 441         if (cppi41_channel->is_allocated) {
 442                 cppi41_channel->is_allocated = 0;
 443                 channel->status = MUSB_DMA_STATUS_FREE;
 444                 channel->actual_len = 0;
 445         }
 446 }
 447
 448 static int cppi41_dma_channel_program(struct dma_channel *channel,
 449                                 u16 packet_sz, u8 mode,
 450                                 dma_addr_t dma_addr, u32 len)
 451 {
 452         int ret;
 453
 454         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 455                 channel->status == MUSB_DMA_STATUS_BUSY);
 456
 457         channel->status = MUSB_DMA_STATUS_BUSY;
 458         channel->actual_len = 0;
 459         ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
 460         if (!ret)
 461                 channel->status = MUSB_DMA_STATUS_FREE;
 462
 463         return ret;
 464 }
 465
 466 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
 467                 void *buf, u32 length)
 468 {
 469         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 470         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 471         struct musb *musb = controller->musb;
 472
 473         if (is_host_active(musb)) {
 474                 WARN_ON(1);
 475                 return 1;
 476         }
 477         if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
 478                 return 0;
 479         if (cppi41_channel->is_tx)
 480                 return 1;
 481         /* AM335x Advisory 1.0.13. No workaround for device RX mode */
 482         return 0;
 483 }
 484
 485 static int cppi41_dma_channel_abort(struct dma_channel *channel)
 486 {
 487         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 488         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 489         struct musb *musb = controller->musb;
 490         void __iomem *epio = cppi41_channel->hw_ep->regs;
 491         int tdbit;
 492         int ret;
 493         unsigned is_tx;
 494         u16 csr;
 495
 496         is_tx = cppi41_channel->is_tx;
 497         dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
 498                         cppi41_channel->port_num, is_tx);
 499
 500         if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
 501                 return 0;
 502
 503         list_del_init(&cppi41_channel->tx_check);
 504         if (is_tx) {
 505                 csr = musb_readw(epio, MUSB_TXCSR);
 506                 csr &= ~MUSB_TXCSR_DMAENAB;
 507                 musb_writew(epio, MUSB_TXCSR, csr);
 508         } else {
 509                 csr = musb_readw(epio, MUSB_RXCSR);
 510                 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
 511                 musb_writew(epio, MUSB_RXCSR, csr);
 512
 513                 csr = musb_readw(epio, MUSB_RXCSR);
 514                 if (csr & MUSB_RXCSR_RXPKTRDY) {
 515                         csr |= MUSB_RXCSR_FLUSHFIFO;
 516                         musb_writew(epio, MUSB_RXCSR, csr);
 517                         musb_writew(epio, MUSB_RXCSR, csr);
 518                 }
 519         }
 520
 521         tdbit = 1 << cppi41_channel->port_num;
 522         if (is_tx)
 523                 tdbit <<= 16;
 524
 525         do {
 526                 musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 527                 ret = dmaengine_terminate_all(cppi41_channel->dc);
 528         } while (ret == -EAGAIN);
 529
 530         musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
 531
 532         if (is_tx) {
 533                 csr = musb_readw(epio, MUSB_TXCSR);
 534                 if (csr & MUSB_TXCSR_TXPKTRDY) {
 535                         csr |= MUSB_TXCSR_FLUSHFIFO;
 536                         musb_writew(epio, MUSB_TXCSR, csr);
 537                 }
 538         }
 539
 540         cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 541         return 0;
 542 }
 543
 544 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
 545 {
 546         struct dma_chan *dc;
 547         int i;
 548
 549         for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
 550                 dc = ctrl->tx_channel[i].dc;
 551                 if (dc)
 552                         dma_release_channel(dc);
 553                 dc = ctrl->rx_channel[i].dc;
 554                 if (dc)
 555                         dma_release_channel(dc);
 556         }
 557 }
 558
 559 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
 560 {
 561         cppi41_release_all_dma_chans(controller);
 562 }
 563
 564 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 565 {
 566         struct musb *musb = controller->musb;
 567         struct device *dev = musb->controller;
 568         struct device_node *np = dev->of_node;
 569         struct cppi41_dma_channel *cppi41_channel;
 570         int count;
 571         int i;
 572         int ret;
 573
 574         count = of_property_count_strings(np, "dma-names");
 575         if (count < 0)
 576                 return count;
 577
 578         for (i = 0; i < count; i++) {
 579                 struct dma_chan *dc;
 580                 struct dma_channel *musb_dma;
 581                 const char *str;
 582                 unsigned is_tx;
 583                 unsigned int port;
 584
 585                 ret = of_property_read_string_index(np, "dma-names", i, &str);
 586                 if (ret)
 587                         goto err;
 588                 if (!strncmp(str, "tx", 2))
 589                         is_tx = 1;
 590                 else if (!strncmp(str, "rx", 2))
 591                         is_tx = 0;
 592                 else {
 593                         dev_err(dev, "Wrong dmatype %s\n", str);
 594                         goto err;
 595                 }
 596                 ret = kstrtouint(str + 2, 0, &port);
 597                 if (ret)
 598                         goto err;
 599
 600                 if (port > MUSB_DMA_NUM_CHANNELS || !port)
 601                         goto err;
 602                 if (is_tx)
 603                         cppi41_channel = &controller->tx_channel[port - 1];
 604                 else
 605                         cppi41_channel = &controller->rx_channel[port - 1];
 606
 607                 cppi41_channel->controller = controller;
 608                 cppi41_channel->port_num = port;
 609                 cppi41_channel->is_tx = is_tx;
 610                 INIT_LIST_HEAD(&cppi41_channel->tx_check);
 611
 612                 musb_dma = &cppi41_channel->channel;
 613                 musb_dma->private_data = cppi41_channel;
 614                 musb_dma->status = MUSB_DMA_STATUS_FREE;
 615                 musb_dma->max_len = SZ_4M;
 616
 617                 dc = dma_request_slave_channel(dev, str);
 618                 if (!dc) {
 619                         dev_err(dev, "Falied to request %s.\n", str);
 620                         goto err;
 621                 }
 622                 cppi41_channel->dc = dc;
 623         }
 624         return 0;
 625 err:
 626         cppi41_release_all_dma_chans(controller);
 627         return -EINVAL;
 628 }
 629
 630 void dma_controller_destroy(struct dma_controller *c)
 631 {
 632         struct cppi41_dma_controller *controller = container_of(c,
 633                         struct cppi41_dma_controller, controller);
 634
 635         hrtimer_cancel(&controller->early_tx);
 636         cppi41_dma_controller_stop(controller);
 637         kfree(controller);
 638 }
 639
 640 struct dma_controller *dma_controller_create(struct musb *musb,
 641                                         void __iomem *base)
 642 {
 643         struct cppi41_dma_controller *controller;
 644         int ret;
 645
 646         if (!musb->controller->of_node) {
 647                 dev_err(musb->controller, "Need DT for the DMA engine.\n");
 648                 return NULL;
 649         }
 650
 651         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 652         if (!controller)
 653                 goto kzalloc_fail;
 654
 655         hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 656         controller->early_tx.function = cppi41_recheck_tx_req;
 657         INIT_LIST_HEAD(&controller->early_tx_list);
 658         controller->musb = musb;
 659
 660         controller->controller.channel_alloc = cppi41_dma_channel_allocate;
 661         controller->controller.channel_release = cppi41_dma_channel_release;
 662         controller->controller.channel_program = cppi41_dma_channel_program;
 663         controller->controller.channel_abort = cppi41_dma_channel_abort;
 664         controller->controller.is_compatible = cppi41_is_compatible;
 665
 666         ret = cppi41_dma_controller_start(controller);
 667         if (ret)
 668                 goto plat_get_fail;
 669         return &controller->controller;
 670
 671 plat_get_fail:
 672         kfree(controller);
 673 kzalloc_fail:
 674         return NULL;
 675 }