2 * linux/sound/soc/ep93xx-i2s.c
5 * Copyright (C) 2010 Ryan Mallon
7 * Based on the original driver by:
8 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/initval.h>
27 #include <sound/soc.h>
29 #include <mach/hardware.h>
30 #include <mach/ep93xx-regs.h>
31 #include <linux/platform_data/dma-ep93xx.h>
33 #define EP93XX_I2S_TXCLKCFG 0x00
34 #define EP93XX_I2S_RXCLKCFG 0x04
35 #define EP93XX_I2S_GLCTRL 0x0C
37 #define EP93XX_I2S_TXLINCTRLDATA 0x28
38 #define EP93XX_I2S_TXCTRL 0x2C
39 #define EP93XX_I2S_TXWRDLEN 0x30
40 #define EP93XX_I2S_TX0EN 0x34
42 #define EP93XX_I2S_RXLINCTRLDATA 0x58
43 #define EP93XX_I2S_RXCTRL 0x5C
44 #define EP93XX_I2S_RXWRDLEN 0x60
45 #define EP93XX_I2S_RX0EN 0x64
47 #define EP93XX_I2S_WRDLEN_16 (0 << 0)
48 #define EP93XX_I2S_WRDLEN_24 (1 << 0)
49 #define EP93XX_I2S_WRDLEN_32 (2 << 0)
51 #define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
53 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
54 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
55 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
56 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
57 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
59 struct ep93xx_i2s_info
{
66 static struct ep93xx_dma_data ep93xx_i2s_dma_data
[] = {
67 [SNDRV_PCM_STREAM_PLAYBACK
] = {
68 .name
= "i2s-pcm-out",
69 .port
= EP93XX_DMA_I2S1
,
70 .direction
= DMA_MEM_TO_DEV
,
72 [SNDRV_PCM_STREAM_CAPTURE
] = {
74 .port
= EP93XX_DMA_I2S1
,
75 .direction
= DMA_DEV_TO_MEM
,
79 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info
*info
,
80 unsigned reg
, unsigned val
)
82 __raw_writel(val
, info
->regs
+ reg
);
85 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info
*info
,
88 return __raw_readl(info
->regs
+ reg
);
91 static void ep93xx_i2s_enable(struct ep93xx_i2s_info
*info
, int stream
)
96 if ((ep93xx_i2s_read_reg(info
, EP93XX_I2S_TX0EN
) & 0x1) == 0 &&
97 (ep93xx_i2s_read_reg(info
, EP93XX_I2S_RX0EN
) & 0x1) == 0) {
99 clk_enable(info
->mclk
);
100 clk_enable(info
->sclk
);
101 clk_enable(info
->lrclk
);
104 ep93xx_i2s_write_reg(info
, EP93XX_I2S_GLCTRL
, 1);
108 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
109 base_reg
= EP93XX_I2S_TX0EN
;
111 base_reg
= EP93XX_I2S_RX0EN
;
112 for (i
= 0; i
< 3; i
++)
113 ep93xx_i2s_write_reg(info
, base_reg
+ (i
* 4), 1);
116 static void ep93xx_i2s_disable(struct ep93xx_i2s_info
*info
, int stream
)
122 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
123 base_reg
= EP93XX_I2S_TX0EN
;
125 base_reg
= EP93XX_I2S_RX0EN
;
126 for (i
= 0; i
< 3; i
++)
127 ep93xx_i2s_write_reg(info
, base_reg
+ (i
* 4), 0);
129 if ((ep93xx_i2s_read_reg(info
, EP93XX_I2S_TX0EN
) & 0x1) == 0 &&
130 (ep93xx_i2s_read_reg(info
, EP93XX_I2S_RX0EN
) & 0x1) == 0) {
132 ep93xx_i2s_write_reg(info
, EP93XX_I2S_GLCTRL
, 0);
135 clk_disable(info
->lrclk
);
136 clk_disable(info
->sclk
);
137 clk_disable(info
->mclk
);
141 static int ep93xx_i2s_dai_probe(struct snd_soc_dai
*dai
)
143 dai
->playback_dma_data
= &ep93xx_i2s_dma_data
[SNDRV_PCM_STREAM_PLAYBACK
];
144 dai
->capture_dma_data
= &ep93xx_i2s_dma_data
[SNDRV_PCM_STREAM_CAPTURE
];
149 static void ep93xx_i2s_shutdown(struct snd_pcm_substream
*substream
,
150 struct snd_soc_dai
*dai
)
152 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(dai
);
154 ep93xx_i2s_disable(info
, substream
->stream
);
157 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
160 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(cpu_dai
);
161 unsigned int clk_cfg
, lin_ctrl
;
163 clk_cfg
= ep93xx_i2s_read_reg(info
, EP93XX_I2S_RXCLKCFG
);
164 lin_ctrl
= ep93xx_i2s_read_reg(info
, EP93XX_I2S_RXLINCTRLDATA
);
166 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
167 case SND_SOC_DAIFMT_I2S
:
168 clk_cfg
|= EP93XX_I2S_CLKCFG_REL
;
169 lin_ctrl
&= ~EP93XX_I2S_LINCTRLDATA_R_JUST
;
172 case SND_SOC_DAIFMT_LEFT_J
:
173 clk_cfg
&= ~EP93XX_I2S_CLKCFG_REL
;
174 lin_ctrl
&= ~EP93XX_I2S_LINCTRLDATA_R_JUST
;
177 case SND_SOC_DAIFMT_RIGHT_J
:
178 clk_cfg
&= ~EP93XX_I2S_CLKCFG_REL
;
179 lin_ctrl
|= EP93XX_I2S_LINCTRLDATA_R_JUST
;
186 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
187 case SND_SOC_DAIFMT_CBS_CFS
:
189 clk_cfg
|= EP93XX_I2S_CLKCFG_MASTER
;
192 case SND_SOC_DAIFMT_CBM_CFM
:
193 /* Codec is master */
194 clk_cfg
&= ~EP93XX_I2S_CLKCFG_MASTER
;
201 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
202 case SND_SOC_DAIFMT_NB_NF
:
203 /* Negative bit clock, lrclk low on left word */
204 clk_cfg
&= ~(EP93XX_I2S_CLKCFG_CKP
| EP93XX_I2S_CLKCFG_REL
);
207 case SND_SOC_DAIFMT_NB_IF
:
208 /* Negative bit clock, lrclk low on right word */
209 clk_cfg
&= ~EP93XX_I2S_CLKCFG_CKP
;
210 clk_cfg
|= EP93XX_I2S_CLKCFG_REL
;
213 case SND_SOC_DAIFMT_IB_NF
:
214 /* Positive bit clock, lrclk low on left word */
215 clk_cfg
|= EP93XX_I2S_CLKCFG_CKP
;
216 clk_cfg
&= ~EP93XX_I2S_CLKCFG_REL
;
219 case SND_SOC_DAIFMT_IB_IF
:
220 /* Positive bit clock, lrclk low on right word */
221 clk_cfg
|= EP93XX_I2S_CLKCFG_CKP
| EP93XX_I2S_CLKCFG_REL
;
225 /* Write new register values */
226 ep93xx_i2s_write_reg(info
, EP93XX_I2S_RXCLKCFG
, clk_cfg
);
227 ep93xx_i2s_write_reg(info
, EP93XX_I2S_TXCLKCFG
, clk_cfg
);
228 ep93xx_i2s_write_reg(info
, EP93XX_I2S_RXLINCTRLDATA
, lin_ctrl
);
229 ep93xx_i2s_write_reg(info
, EP93XX_I2S_TXLINCTRLDATA
, lin_ctrl
);
233 static int ep93xx_i2s_hw_params(struct snd_pcm_substream
*substream
,
234 struct snd_pcm_hw_params
*params
,
235 struct snd_soc_dai
*dai
)
237 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(dai
);
238 unsigned word_len
, div
, sdiv
, lrdiv
;
241 switch (params_format(params
)) {
242 case SNDRV_PCM_FORMAT_S16_LE
:
243 word_len
= EP93XX_I2S_WRDLEN_16
;
246 case SNDRV_PCM_FORMAT_S24_LE
:
247 word_len
= EP93XX_I2S_WRDLEN_24
;
250 case SNDRV_PCM_FORMAT_S32_LE
:
251 word_len
= EP93XX_I2S_WRDLEN_32
;
258 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
259 ep93xx_i2s_write_reg(info
, EP93XX_I2S_TXWRDLEN
, word_len
);
261 ep93xx_i2s_write_reg(info
, EP93XX_I2S_RXWRDLEN
, word_len
);
264 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
265 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
266 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
267 * value is 64, because our sample size is 32 bit * 2 channels.
268 * I2S standard permits us to transmit more bits than
271 div
= clk_get_rate(info
->mclk
) / params_rate(params
);
273 if (div
> (256 + 512) / 2) {
277 if (div
< (128 + 256) / 2)
281 err
= clk_set_rate(info
->sclk
, clk_get_rate(info
->mclk
) / sdiv
);
285 err
= clk_set_rate(info
->lrclk
, clk_get_rate(info
->sclk
) / lrdiv
);
289 ep93xx_i2s_enable(info
, substream
->stream
);
293 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai
*cpu_dai
, int clk_id
,
294 unsigned int freq
, int dir
)
296 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(cpu_dai
);
298 if (dir
== SND_SOC_CLOCK_IN
|| clk_id
!= 0)
301 return clk_set_rate(info
->mclk
, freq
);
305 static int ep93xx_i2s_suspend(struct snd_soc_dai
*dai
)
307 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(dai
);
312 ep93xx_i2s_disable(info
, SNDRV_PCM_STREAM_PLAYBACK
);
313 ep93xx_i2s_disable(info
, SNDRV_PCM_STREAM_CAPTURE
);
318 static int ep93xx_i2s_resume(struct snd_soc_dai
*dai
)
320 struct ep93xx_i2s_info
*info
= snd_soc_dai_get_drvdata(dai
);
325 ep93xx_i2s_enable(info
, SNDRV_PCM_STREAM_PLAYBACK
);
326 ep93xx_i2s_enable(info
, SNDRV_PCM_STREAM_CAPTURE
);
331 #define ep93xx_i2s_suspend NULL
332 #define ep93xx_i2s_resume NULL
335 static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops
= {
336 .shutdown
= ep93xx_i2s_shutdown
,
337 .hw_params
= ep93xx_i2s_hw_params
,
338 .set_sysclk
= ep93xx_i2s_set_sysclk
,
339 .set_fmt
= ep93xx_i2s_set_dai_fmt
,
342 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
344 static struct snd_soc_dai_driver ep93xx_i2s_dai
= {
346 .probe
= ep93xx_i2s_dai_probe
,
347 .suspend
= ep93xx_i2s_suspend
,
348 .resume
= ep93xx_i2s_resume
,
352 .rates
= SNDRV_PCM_RATE_8000_192000
,
353 .formats
= EP93XX_I2S_FORMATS
,
358 .rates
= SNDRV_PCM_RATE_8000_192000
,
359 .formats
= EP93XX_I2S_FORMATS
,
361 .ops
= &ep93xx_i2s_dai_ops
,
364 static const struct snd_soc_component_driver ep93xx_i2s_component
= {
365 .name
= "ep93xx-i2s",
368 static int ep93xx_i2s_probe(struct platform_device
*pdev
)
370 struct ep93xx_i2s_info
*info
;
371 struct resource
*res
;
374 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
378 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
379 info
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
380 if (IS_ERR(info
->regs
))
381 return PTR_ERR(info
->regs
);
383 info
->mclk
= clk_get(&pdev
->dev
, "mclk");
384 if (IS_ERR(info
->mclk
)) {
385 err
= PTR_ERR(info
->mclk
);
389 info
->sclk
= clk_get(&pdev
->dev
, "sclk");
390 if (IS_ERR(info
->sclk
)) {
391 err
= PTR_ERR(info
->sclk
);
395 info
->lrclk
= clk_get(&pdev
->dev
, "lrclk");
396 if (IS_ERR(info
->lrclk
)) {
397 err
= PTR_ERR(info
->lrclk
);
401 dev_set_drvdata(&pdev
->dev
, info
);
403 err
= snd_soc_register_component(&pdev
->dev
, &ep93xx_i2s_component
,
411 clk_put(info
->lrclk
);
420 static int ep93xx_i2s_remove(struct platform_device
*pdev
)
422 struct ep93xx_i2s_info
*info
= dev_get_drvdata(&pdev
->dev
);
424 snd_soc_unregister_component(&pdev
->dev
);
425 clk_put(info
->lrclk
);
431 static struct platform_driver ep93xx_i2s_driver
= {
432 .probe
= ep93xx_i2s_probe
,
433 .remove
= ep93xx_i2s_remove
,
435 .name
= "ep93xx-i2s",
436 .owner
= THIS_MODULE
,
440 module_platform_driver(ep93xx_i2s_driver
);
442 MODULE_ALIAS("platform:ep93xx-i2s");
443 MODULE_AUTHOR("Ryan Mallon");
444 MODULE_DESCRIPTION("EP93XX I2S driver");
445 MODULE_LICENSE("GPL");