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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / sound / soc / codecs / lm49453.c
blobe19490cfb3a8bde2036e61d877b3a8c407cc510c
1 /*
2 * lm49453.c - LM49453 ALSA Soc Audio driver
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * Initially based on sound/soc/codecs/wm8350.c
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/tlv.h>
28 #include <sound/jack.h>
29 #include <sound/initval.h>
30 #include <asm/div64.h>
31 #include "lm49453.h"
32
33 static struct reg_default lm49453_reg_defs[] = {
34 { 0, 0x00 },
35 { 1, 0x00 },
36 { 2, 0x00 },
37 { 3, 0x00 },
38 { 4, 0x00 },
39 { 5, 0x00 },
40 { 6, 0x00 },
41 { 7, 0x00 },
42 { 8, 0x00 },
43 { 9, 0x00 },
44 { 10, 0x00 },
45 { 11, 0x00 },
46 { 12, 0x00 },
47 { 13, 0x00 },
48 { 14, 0x00 },
49 { 15, 0x00 },
50 { 16, 0x00 },
51 { 17, 0x00 },
52 { 18, 0x00 },
53 { 19, 0x00 },
54 { 20, 0x00 },
55 { 21, 0x00 },
56 { 22, 0x00 },
57 { 23, 0x00 },
58 { 32, 0x00 },
59 { 33, 0x00 },
60 { 35, 0x00 },
61 { 36, 0x00 },
62 { 37, 0x00 },
63 { 46, 0x00 },
64 { 48, 0x00 },
65 { 49, 0x00 },
66 { 51, 0x00 },
67 { 56, 0x00 },
68 { 58, 0x00 },
69 { 59, 0x00 },
70 { 60, 0x00 },
71 { 61, 0x00 },
72 { 62, 0x00 },
73 { 63, 0x00 },
74 { 64, 0x00 },
75 { 65, 0x00 },
76 { 66, 0x00 },
77 { 67, 0x00 },
78 { 68, 0x00 },
79 { 69, 0x00 },
80 { 70, 0x00 },
81 { 71, 0x00 },
82 { 72, 0x00 },
83 { 73, 0x00 },
84 { 74, 0x00 },
85 { 75, 0x00 },
86 { 76, 0x00 },
87 { 77, 0x00 },
88 { 78, 0x00 },
89 { 79, 0x00 },
90 { 80, 0x00 },
91 { 81, 0x00 },
92 { 82, 0x00 },
93 { 83, 0x00 },
94 { 85, 0x00 },
95 { 85, 0x00 },
96 { 86, 0x00 },
97 { 87, 0x00 },
98 { 88, 0x00 },
99 { 89, 0x00 },
100 { 90, 0x00 },
101 { 91, 0x00 },
102 { 92, 0x00 },
103 { 93, 0x00 },
104 { 94, 0x00 },
105 { 95, 0x00 },
106 { 96, 0x01 },
107 { 97, 0x00 },
108 { 98, 0x00 },
109 { 99, 0x00 },
110 { 100, 0x00 },
111 { 101, 0x00 },
112 { 102, 0x00 },
113 { 103, 0x01 },
114 { 104, 0x01 },
115 { 105, 0x00 },
116 { 106, 0x01 },
117 { 107, 0x00 },
118 { 108, 0x00 },
119 { 109, 0x00 },
120 { 110, 0x00 },
121 { 111, 0x02 },
122 { 112, 0x02 },
123 { 113, 0x00 },
124 { 121, 0x80 },
125 { 122, 0xBB },
126 { 123, 0x80 },
127 { 124, 0xBB },
128 { 128, 0x00 },
129 { 130, 0x00 },
130 { 131, 0x00 },
131 { 132, 0x00 },
132 { 133, 0x0A },
133 { 134, 0x0A },
134 { 135, 0x0A },
135 { 136, 0x0F },
136 { 137, 0x00 },
137 { 138, 0x73 },
138 { 139, 0x33 },
139 { 140, 0x73 },
140 { 141, 0x33 },
141 { 142, 0x73 },
142 { 143, 0x33 },
143 { 144, 0x73 },
144 { 145, 0x33 },
145 { 146, 0x73 },
146 { 147, 0x33 },
147 { 148, 0x73 },
148 { 149, 0x33 },
149 { 150, 0x73 },
150 { 151, 0x33 },
151 { 152, 0x00 },
152 { 153, 0x00 },
153 { 154, 0x00 },
154 { 155, 0x00 },
155 { 176, 0x00 },
156 { 177, 0x00 },
157 { 178, 0x00 },
158 { 179, 0x00 },
159 { 180, 0x00 },
160 { 181, 0x00 },
161 { 182, 0x00 },
162 { 183, 0x00 },
163 { 184, 0x00 },
164 { 185, 0x00 },
165 { 186, 0x00 },
166 { 187, 0x00 },
167 { 188, 0x00 },
168 { 189, 0x00 },
169 { 208, 0x06 },
170 { 209, 0x00 },
171 { 210, 0x08 },
172 { 211, 0x54 },
173 { 212, 0x14 },
174 { 213, 0x0d },
175 { 214, 0x0d },
176 { 215, 0x14 },
177 { 216, 0x60 },
178 { 221, 0x00 },
179 { 222, 0x00 },
180 { 223, 0x00 },
181 { 224, 0x00 },
182 { 248, 0x00 },
183 { 249, 0x00 },
184 { 250, 0x00 },
185 { 255, 0x00 },
186 };
187
188 /* codec private data */
189 struct lm49453_priv {
190 struct regmap *regmap;
191 int fs_rate;
192 };
193
194 /* capture path controls */
195
196 static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
197
198 static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
199 lm49453_mic2mode_text);
200
201 static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
202
203 static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
204 LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
205 7, lm49453_dmic_cfg_text);
206
207 static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
208 LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
209 7, lm49453_dmic_cfg_text);
210
211 /* MUX Controls */
212 static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
213
214 static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
215
216 static const struct soc_enum lm49453_adcl_enum =
217 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
218 ARRAY_SIZE(lm49453_adcl_mux_text),
219 lm49453_adcl_mux_text);
220
221 static const struct soc_enum lm49453_adcr_enum =
222 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
223 ARRAY_SIZE(lm49453_adcr_mux_text),
224 lm49453_adcr_mux_text);
225
226 static const struct snd_kcontrol_new lm49453_adcl_mux_control =
227 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
228
229 static const struct snd_kcontrol_new lm49453_adcr_mux_control =
230 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
231
232 static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
233 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
234 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
235 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
236 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
237 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
238 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
239 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
240 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
241 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
242 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
243 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
244 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
245 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
246 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
247 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
248 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
249 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
250 };
251
252 static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
253 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
254 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
255 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
256 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
257 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
258 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
259 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
260 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
261 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
262 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
263 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
264 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
265 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
266 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
267 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
268 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
269 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
270 };
271
272 static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
273 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
274 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
275 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
276 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
277 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
278 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
279 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
280 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
281 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
282 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
283 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
284 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
285 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
286 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
287 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
288 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
289 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
290 };
291
292 static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
293 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
294 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
295 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
296 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
297 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
298 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
299 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
300 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
301 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
302 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
303 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
304 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
305 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
306 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
307 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
308 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
309 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
310 };
311
312 static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
313 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
314 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
315 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
316 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
317 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
318 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
319 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
320 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
321 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
322 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
323 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
324 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
325 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
326 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
327 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
328 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
329 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
330 };
331
332 static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
333 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
334 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
335 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
336 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
337 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
338 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
339 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
340 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
341 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
342 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
343 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
344 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
345 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
346 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
347 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
348 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
349 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
350 };
351
352 static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
353 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
354 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
355 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
356 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
357 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
358 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
359 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
360 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
361 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
362 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
363 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
364 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
365 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
366 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
367 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
368 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
369 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
370 };
371
372 static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
373 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
374 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
375 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
376 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
377 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
378 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
379 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
380 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
381 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
382 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
383 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
384 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
385 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
386 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
387 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
388 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
389 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
390 };
391
392 static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
393 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
394 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
395 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
396 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
397 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
398 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
399 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
400 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
401 };
402
403 static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
404 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
405 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
406 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
407 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
408 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
409 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
410 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
411 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
412 };
413
414 static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
415 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
416 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
417 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
418 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
419 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
420 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
421 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
422 };
423
424 static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
425 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
426 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
427 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
428 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
429 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
430 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
431 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
432 };
433
434 static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
435 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
436 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
437 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
438 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
439 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
440 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
441 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
442 };
443
444 static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
445 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
446 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
447 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
448 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
449 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
450 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
451 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
452 };
453
454 static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
455 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
456 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
457 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
458 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
459 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
460 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
461 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
462 };
463
464 static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
465 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
466 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
467 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
468 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
469 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
470 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
471 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
472 };
473
474 static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
475 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
476 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
477 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
478 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
479 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
480 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
481 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
482 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
483 };
484
485 static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
486 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
487 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
488 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
489 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
490 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
491 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
492 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
493 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
494 };
495
496 /* TLV Declarations */
497 static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
498 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
499 static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
500 static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
501
502 static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
503 /* Sidetone supports mono only */
504 SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
505 0, 0x3F, 0, stn_tlv),
506 SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
507 0, 0x3F, 0, stn_tlv),
508 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
509 0, 0x3F, 0, stn_tlv),
510 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
511 0, 0x3F, 0, stn_tlv),
512 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
513 0, 0x3F, 0, stn_tlv),
514 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
515 0, 0x3F, 0, stn_tlv),
516 };
517
518 static const struct snd_kcontrol_new lm49453_snd_controls[] = {
519 /* mic1 and mic2 supports mono only */
520 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
521 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
522
523 SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
524 0, adc_dac_tlv),
525 SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
526 0, adc_dac_tlv),
527
528 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
529 LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
530 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
531 LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
532
533 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
534 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
535 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
536
537 /* Capture path filter enable */
538 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
539 0, 1, 0),
540 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
541 1, 1, 0),
542 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
543 2, 1, 0),
544
545 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
546 LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
547 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
548 LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
549 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
550 LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
551 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
552 LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
553
554 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
555 0, 63, 0, adc_dac_tlv),
556
557 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
558 0, 3, 0, port_tlv),
559 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
560 2, 3, 0, port_tlv),
561 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
562 4, 3, 0, port_tlv),
563 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
564 6, 3, 0, port_tlv),
565 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
566 0, 3, 0, port_tlv),
567 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
568 2, 3, 0, port_tlv),
569 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
570 4, 3, 0, port_tlv),
571 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
572 6, 3, 0, port_tlv),
573
574 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
575 0, 3, 0, port_tlv),
576 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
577 2, 3, 0, port_tlv),
578
579 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
580 1, 1, 0),
581 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
582 1, 1, 0),
583 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
584 2, 1, 0),
585 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
586 2, 1, 0)
587
588 };
589
590 /* DAPM widgets */
591 static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
592
593 /* All end points HP,EP, LS, Lineout and Haptic */
594 SND_SOC_DAPM_OUTPUT("HPOUTL"),
595 SND_SOC_DAPM_OUTPUT("HPOUTR"),
596 SND_SOC_DAPM_OUTPUT("EPOUT"),
597 SND_SOC_DAPM_OUTPUT("LSOUTL"),
598 SND_SOC_DAPM_OUTPUT("LSOUTR"),
599 SND_SOC_DAPM_OUTPUT("LOOUTR"),
600 SND_SOC_DAPM_OUTPUT("LOOUTL"),
601 SND_SOC_DAPM_OUTPUT("HAOUTL"),
602 SND_SOC_DAPM_OUTPUT("HAOUTR"),
603
604 SND_SOC_DAPM_INPUT("AMIC1"),
605 SND_SOC_DAPM_INPUT("AMIC2"),
606 SND_SOC_DAPM_INPUT("DMIC1DAT"),
607 SND_SOC_DAPM_INPUT("DMIC2DAT"),
608 SND_SOC_DAPM_INPUT("AUXL"),
609 SND_SOC_DAPM_INPUT("AUXR"),
610
611 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
612 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
613 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
614 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
615 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
616 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
617 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
618 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
619 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
620 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
621
622 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
623 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
624
625 /* playback path driver enables */
626 SND_SOC_DAPM_OUT_DRV("Headset Switch",
627 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
628 SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
629 LM49453_P0_EP_REG, 0, 0, NULL, 0),
630 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
631 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
632 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
633 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
634 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
635 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
636 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
637 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
638
639 /* DAC */
640 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
641 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
642 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
643 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
644 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
645 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
646 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
647 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
648
649
650 SND_SOC_DAPM_PGA("AUXL Input",
651 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
652 SND_SOC_DAPM_PGA("AUXR Input",
653 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
654
655 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
656
657 /* ADC */
658 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
659 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
660 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
661 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
662
663 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
664 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
665
666 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
667 &lm49453_adcl_mux_control),
668 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
669 &lm49453_adcr_mux_control),
670
671 SND_SOC_DAPM_MUX("Mic1 Input",
672 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
673
674 SND_SOC_DAPM_MUX("Mic2 Input",
675 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
676
677 /* AIF */
678 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
679 LM49453_P0_PULL_CONFIG1_REG, 2, 0),
680 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
681 LM49453_P0_PULL_CONFIG1_REG, 6, 0),
682
683 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
684 LM49453_P0_PULL_CONFIG1_REG, 3, 0),
685 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
686 LM49453_P0_PULL_CONFIG1_REG, 7, 0),
687
688 /* Port1 TX controls */
689 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
690 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
691 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
692 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
693 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
694 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
695 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
696 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
697
698 /* Port2 TX controls */
699 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
700 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
701
702 /* Sidetone Mixer */
703 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
704 lm49453_sidetone_mixer_controls,
705 ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
706
707 /* DAC MIXERS */
708 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
709 lm49453_headset_left_mixer,
710 ARRAY_SIZE(lm49453_headset_left_mixer)),
711 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
712 lm49453_headset_right_mixer,
713 ARRAY_SIZE(lm49453_headset_right_mixer)),
714 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
715 lm49453_lineout_left_mixer,
716 ARRAY_SIZE(lm49453_lineout_left_mixer)),
717 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
718 lm49453_lineout_right_mixer,
719 ARRAY_SIZE(lm49453_lineout_right_mixer)),
720 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
721 lm49453_speaker_left_mixer,
722 ARRAY_SIZE(lm49453_speaker_left_mixer)),
723 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
724 lm49453_speaker_right_mixer,
725 ARRAY_SIZE(lm49453_speaker_right_mixer)),
726 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
727 lm49453_haptic_left_mixer,
728 ARRAY_SIZE(lm49453_haptic_left_mixer)),
729 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
730 lm49453_haptic_right_mixer,
731 ARRAY_SIZE(lm49453_haptic_right_mixer)),
732
733 /* Capture Mixer */
734 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
735 lm49453_port1_tx1_mixer,
736 ARRAY_SIZE(lm49453_port1_tx1_mixer)),
737 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
738 lm49453_port1_tx2_mixer,
739 ARRAY_SIZE(lm49453_port1_tx2_mixer)),
740 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
741 lm49453_port1_tx3_mixer,
742 ARRAY_SIZE(lm49453_port1_tx3_mixer)),
743 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
744 lm49453_port1_tx4_mixer,
745 ARRAY_SIZE(lm49453_port1_tx4_mixer)),
746 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
747 lm49453_port1_tx5_mixer,
748 ARRAY_SIZE(lm49453_port1_tx5_mixer)),
749 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
750 lm49453_port1_tx6_mixer,
751 ARRAY_SIZE(lm49453_port1_tx6_mixer)),
752 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
753 lm49453_port1_tx7_mixer,
754 ARRAY_SIZE(lm49453_port1_tx7_mixer)),
755 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
756 lm49453_port1_tx8_mixer,
757 ARRAY_SIZE(lm49453_port1_tx8_mixer)),
758
759 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
760 lm49453_port2_tx1_mixer,
761 ARRAY_SIZE(lm49453_port2_tx1_mixer)),
762 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
763 lm49453_port2_tx2_mixer,
764 ARRAY_SIZE(lm49453_port2_tx2_mixer)),
765 };
766
767 static const struct snd_soc_dapm_route lm49453_audio_map[] = {
768 /* Port SDI mapping */
769 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
770 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
771 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
772 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
773 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
774 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
775 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
776 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
777
778 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
779 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
780
781 /* HP mapping */
782 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
783 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
784 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
785 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
786 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
787 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
788 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
789 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
790
791 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
792 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
793
794 { "HPL Mixer", "ADCL Switch", "ADC Left" },
795 { "HPL Mixer", "ADCR Switch", "ADC Right" },
796 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
797 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
798 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
799 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
800 { "HPL Mixer", "Sidetone Switch", "Sidetone" },
801
802 { "HPL DAC", NULL, "HPL Mixer" },
803
804 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
805 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
806 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
807 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
808 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
809 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
810 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
811 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
812
813 /* Port 2 */
814 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
815 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
816
817 { "HPR Mixer", "ADCL Switch", "ADC Left" },
818 { "HPR Mixer", "ADCR Switch", "ADC Right" },
819 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
820 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
821 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
822 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
823 { "HPR Mixer", "Sidetone Switch", "Sidetone" },
824
825 { "HPR DAC", NULL, "HPR Mixer" },
826
827 { "HPOUTL", "Headset Switch", "HPL DAC"},
828 { "HPOUTR", "Headset Switch", "HPR DAC"},
829
830 /* EP map */
831 { "EPOUT", "Earpiece Switch", "HPL DAC" },
832
833 /* Speaker map */
834 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
835 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
836 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
837 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
838 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
839 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
840 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
841 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
842
843 /* Port 2 */
844 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
845 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
846
847 { "LSL Mixer", "ADCL Switch", "ADC Left" },
848 { "LSL Mixer", "ADCR Switch", "ADC Right" },
849 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
850 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
851 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
852 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
853 { "LSL Mixer", "Sidetone Switch", "Sidetone" },
854
855 { "LSL DAC", NULL, "LSL Mixer" },
856
857 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
858 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
859 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
860 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
861 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
862 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
863 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
864 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
865
866 /* Port 2 */
867 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
868 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
869
870 { "LSR Mixer", "ADCL Switch", "ADC Left" },
871 { "LSR Mixer", "ADCR Switch", "ADC Right" },
872 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
873 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
874 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
875 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
876 { "LSR Mixer", "Sidetone Switch", "Sidetone" },
877
878 { "LSR DAC", NULL, "LSR Mixer" },
879
880 { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
881 { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
882
883 /* Haptic map */
884 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
885 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
886 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
887 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
888 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
889 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
890 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
891 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
892
893 /* Port 2 */
894 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
895 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
896
897 { "HAL Mixer", "ADCL Switch", "ADC Left" },
898 { "HAL Mixer", "ADCR Switch", "ADC Right" },
899 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
900 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
901 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
902 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
903 { "HAL Mixer", "Sidetone Switch", "Sidetone" },
904
905 { "HAL DAC", NULL, "HAL Mixer" },
906
907 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
908 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
909 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
910 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
911 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
912 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
913 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
914 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
915
916 /* Port 2 */
917 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
918 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
919
920 { "HAR Mixer", "ADCL Switch", "ADC Left" },
921 { "HAR Mixer", "ADCR Switch", "ADC Right" },
922 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
923 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
924 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
925 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
926 { "HAR Mixer", "Sideton Switch", "Sidetone" },
927
928 { "HAR DAC", NULL, "HAR Mixer" },
929
930 { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
931 { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
932
933 /* Lineout map */
934 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
935 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
936 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
937 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
938 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
939 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
940 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
941 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
942
943 /* Port 2 */
944 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
945 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
946
947 { "LOL Mixer", "ADCL Switch", "ADC Left" },
948 { "LOL Mixer", "ADCR Switch", "ADC Right" },
949 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
950 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
951 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
952 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
953 { "LOL Mixer", "Sidetone Switch", "Sidetone" },
954
955 { "LOL DAC", NULL, "LOL Mixer" },
956
957 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
958 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
959 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
960 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
961 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
962 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
963 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
964 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
965
966 /* Port 2 */
967 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
968 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
969
970 { "LOR Mixer", "ADCL Switch", "ADC Left" },
971 { "LOR Mixer", "ADCR Switch", "ADC Right" },
972 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
973 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
974 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
975 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
976 { "LOR Mixer", "Sidetone Switch", "Sidetone" },
977
978 { "LOR DAC", NULL, "LOR Mixer" },
979
980 { "LOOUTL", NULL, "LOL DAC" },
981 { "LOOUTR", NULL, "LOR DAC" },
982
983 /* TX map */
984 /* Port1 mappings */
985 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
986 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
987 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
988 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
989 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
990 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
991
992 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
993 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
994 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
995 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
996 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
997 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
998
999 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
1000 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1001 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1002 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1003 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1004 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1005
1006 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1007 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1008 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1009 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1010 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1011 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1012
1013 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1014 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1015 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1016 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1017 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1018 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1019
1020 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1021 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1022 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1023 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1024 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1025 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1026
1027 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1028 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1029 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1030 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1031 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1032 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1033
1034 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1035 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1036 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1037 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1038 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1039 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1040
1041 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1042 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1043 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1044 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1045 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1046 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1047
1048 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1049 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1050 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1051 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1052 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1053 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1054
1055 { "P1_1_TX", NULL, "Port1_1 Mixer" },
1056 { "P1_2_TX", NULL, "Port1_2 Mixer" },
1057 { "P1_3_TX", NULL, "Port1_3 Mixer" },
1058 { "P1_4_TX", NULL, "Port1_4 Mixer" },
1059 { "P1_5_TX", NULL, "Port1_5 Mixer" },
1060 { "P1_6_TX", NULL, "Port1_6 Mixer" },
1061 { "P1_7_TX", NULL, "Port1_7 Mixer" },
1062 { "P1_8_TX", NULL, "Port1_8 Mixer" },
1063
1064 { "P2_1_TX", NULL, "Port2_1 Mixer" },
1065 { "P2_2_TX", NULL, "Port2_2 Mixer" },
1066
1067 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1068 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1069 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1070 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1071 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1072 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1073 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1074 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1075
1076 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1077 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1078
1079 { "Mic1 Input", NULL, "AMIC1" },
1080 { "Mic2 Input", NULL, "AMIC2" },
1081
1082 { "AUXL Input", NULL, "AUXL" },
1083 { "AUXR Input", NULL, "AUXR" },
1084
1085 /* AUX connections */
1086 { "ADCL Mux", "Aux_L", "AUXL Input" },
1087 { "ADCL Mux", "MIC1", "Mic1 Input" },
1088
1089 { "ADCR Mux", "Aux_R", "AUXR Input" },
1090 { "ADCR Mux", "MIC2", "Mic2 Input" },
1091
1092 /* ADC connection */
1093 { "ADC Left", NULL, "ADCL Mux"},
1094 { "ADC Right", NULL, "ADCR Mux"},
1095
1096 { "DMIC1 Left", NULL, "DMIC1DAT"},
1097 { "DMIC1 Right", NULL, "DMIC1DAT"},
1098 { "DMIC2 Left", NULL, "DMIC2DAT"},
1099 { "DMIC2 Right", NULL, "DMIC2DAT"},
1100
1101 /* Sidetone map */
1102 { "Sidetone Mixer", NULL, "ADC Left" },
1103 { "Sidetone Mixer", NULL, "ADC Right" },
1104 { "Sidetone Mixer", NULL, "DMIC1 Left" },
1105 { "Sidetone Mixer", NULL, "DMIC1 Right" },
1106 { "Sidetone Mixer", NULL, "DMIC2 Left" },
1107 { "Sidetone Mixer", NULL, "DMIC2 Right" },
1108
1109 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1110 };
1111
1112 static int lm49453_hw_params(struct snd_pcm_substream *substream,
1113 struct snd_pcm_hw_params *params,
1114 struct snd_soc_dai *dai)
1115 {
1116 struct snd_soc_codec *codec = dai->codec;
1117 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1118 u16 clk_div = 0;
1119
1120 lm49453->fs_rate = params_rate(params);
1121
1122 /* Setting DAC clock dividers based on substream sample rate. */
1123 switch (lm49453->fs_rate) {
1124 case 8000:
1125 case 16000:
1126 case 32000:
1127 case 24000:
1128 case 48000:
1129 clk_div = 256;
1130 break;
1131 case 11025:
1132 case 22050:
1133 case 44100:
1134 clk_div = 216;
1135 break;
1136 case 96000:
1137 clk_div = 127;
1138 break;
1139 default:
1140 return -EINVAL;
1141 }
1142
1143 snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1144 snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1145
1146 return 0;
1147 }
1148
1149 static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1150 {
1151 struct snd_soc_codec *codec = codec_dai->codec;
1152
1153 u16 aif_val;
1154 int mode = 0;
1155 int clk_phase = 0;
1156 int clk_shift = 0;
1157
1158 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1159 case SND_SOC_DAIFMT_CBS_CFS:
1160 aif_val = 0;
1161 break;
1162 case SND_SOC_DAIFMT_CBS_CFM:
1163 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1164 break;
1165 case SND_SOC_DAIFMT_CBM_CFS:
1166 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
1167 break;
1168 case SND_SOC_DAIFMT_CBM_CFM:
1169 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1170 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1171 break;
1172 default:
1173 return -EINVAL;
1174 }
1175
1176
1177 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1178 case SND_SOC_DAIFMT_I2S:
1179 break;
1180 case SND_SOC_DAIFMT_DSP_A:
1181 mode = 1;
1182 clk_phase = (1 << 5);
1183 clk_shift = 1;
1184 break;
1185 case SND_SOC_DAIFMT_DSP_B:
1186 mode = 1;
1187 clk_phase = (1 << 5);
1188 clk_shift = 0;
1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193
1194 snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1195 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
1196 (aif_val | mode | clk_phase));
1197
1198 snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1199
1200 return 0;
1201 }
1202
1203 static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1204 unsigned int freq, int dir)
1205 {
1206 struct snd_soc_codec *codec = dai->codec;
1207 u16 pll_clk = 0;
1208
1209 switch (freq) {
1210 case 12288000:
1211 case 26000000:
1212 case 19200000:
1213 /* pll clk slection */
1214 pll_clk = 0;
1215 break;
1216 case 48000:
1217 case 32576:
1218 /* fll clk slection */
1219 pll_clk = BIT(4);
1220 return 0;
1221 default:
1222 return -EINVAL;
1223 }
1224
1225 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1226
1227 return 0;
1228 }
1229
1230 static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1231 {
1232 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1233 (mute ? (BIT(1)|BIT(0)) : 0));
1234 return 0;
1235 }
1236
1237 static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1238 {
1239 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1240 (mute ? (BIT(3)|BIT(2)) : 0));
1241 return 0;
1242 }
1243
1244 static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1245 {
1246 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1247 (mute ? (BIT(5)|BIT(4)) : 0));
1248 return 0;
1249 }
1250
1251 static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1252 {
1253 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1254 (mute ? BIT(4) : 0));
1255 return 0;
1256 }
1257
1258 static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1259 {
1260 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1261 (mute ? (BIT(7)|BIT(6)) : 0));
1262 return 0;
1263 }
1264
1265 static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1266 enum snd_soc_bias_level level)
1267 {
1268 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1269
1270 switch (level) {
1271 case SND_SOC_BIAS_ON:
1272 case SND_SOC_BIAS_PREPARE:
1273 break;
1274
1275 case SND_SOC_BIAS_STANDBY:
1276 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1277 regcache_sync(lm49453->regmap);
1278
1279 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1280 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1281 break;
1282
1283 case SND_SOC_BIAS_OFF:
1284 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1285 LM49453_PMC_SETUP_CHIP_EN, 0);
1286 break;
1287 }
1288
1289 codec->dapm.bias_level = level;
1290
1291 return 0;
1292 }
1293
1294 /* Formates supported by LM49453 driver. */
1295 #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1296 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1297
1298 static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1299 .hw_params = lm49453_hw_params,
1300 .set_sysclk = lm49453_set_dai_sysclk,
1301 .set_fmt = lm49453_set_dai_fmt,
1302 .digital_mute = lm49453_hp_mute,
1303 };
1304
1305 static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1306 .hw_params = lm49453_hw_params,
1307 .set_sysclk = lm49453_set_dai_sysclk,
1308 .set_fmt = lm49453_set_dai_fmt,
1309 .digital_mute = lm49453_ls_mute,
1310 };
1311
1312 static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1313 .hw_params = lm49453_hw_params,
1314 .set_sysclk = lm49453_set_dai_sysclk,
1315 .set_fmt = lm49453_set_dai_fmt,
1316 .digital_mute = lm49453_ha_mute,
1317 };
1318
1319 static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1320 .hw_params = lm49453_hw_params,
1321 .set_sysclk = lm49453_set_dai_sysclk,
1322 .set_fmt = lm49453_set_dai_fmt,
1323 .digital_mute = lm49453_ep_mute,
1324 };
1325
1326 static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1327 .hw_params = lm49453_hw_params,
1328 .set_sysclk = lm49453_set_dai_sysclk,
1329 .set_fmt = lm49453_set_dai_fmt,
1330 .digital_mute = lm49453_lo_mute,
1331 };
1332
1333 /* LM49453 dai structure. */
1334 static struct snd_soc_dai_driver lm49453_dai[] = {
1335 {
1336 .name = "LM49453 Headset",
1337 .playback = {
1338 .stream_name = "Headset",
1339 .channels_min = 2,
1340 .channels_max = 2,
1341 .rates = SNDRV_PCM_RATE_8000_192000,
1342 .formats = LM49453_FORMATS,
1343 },
1344 .capture = {
1345 .stream_name = "Capture",
1346 .channels_min = 1,
1347 .channels_max = 5,
1348 .rates = SNDRV_PCM_RATE_8000_192000,
1349 .formats = LM49453_FORMATS,
1350 },
1351 .ops = &lm49453_headset_dai_ops,
1352 .symmetric_rates = 1,
1353 },
1354 {
1355 .name = "LM49453 Speaker",
1356 .playback = {
1357 .stream_name = "Speaker",
1358 .channels_min = 2,
1359 .channels_max = 2,
1360 .rates = SNDRV_PCM_RATE_8000_192000,
1361 .formats = LM49453_FORMATS,
1362 },
1363 .ops = &lm49453_speaker_dai_ops,
1364 },
1365 {
1366 .name = "LM49453 Haptic",
1367 .playback = {
1368 .stream_name = "Haptic",
1369 .channels_min = 2,
1370 .channels_max = 2,
1371 .rates = SNDRV_PCM_RATE_8000_192000,
1372 .formats = LM49453_FORMATS,
1373 },
1374 .ops = &lm49453_haptic_dai_ops,
1375 },
1376 {
1377 .name = "LM49453 Earpiece",
1378 .playback = {
1379 .stream_name = "Earpiece",
1380 .channels_min = 1,
1381 .channels_max = 1,
1382 .rates = SNDRV_PCM_RATE_8000_192000,
1383 .formats = LM49453_FORMATS,
1384 },
1385 .ops = &lm49453_ep_dai_ops,
1386 },
1387 {
1388 .name = "LM49453 line out",
1389 .playback = {
1390 .stream_name = "Lineout",
1391 .channels_min = 2,
1392 .channels_max = 2,
1393 .rates = SNDRV_PCM_RATE_8000_192000,
1394 .formats = LM49453_FORMATS,
1395 },
1396 .ops = &lm49453_lineout_dai_ops,
1397 },
1398 };
1399
1400 static int lm49453_suspend(struct snd_soc_codec *codec)
1401 {
1402 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1403 return 0;
1404 }
1405
1406 static int lm49453_resume(struct snd_soc_codec *codec)
1407 {
1408 lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1409 return 0;
1410 }
1411
1412 static int lm49453_probe(struct snd_soc_codec *codec)
1413 {
1414 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1415 int ret = 0;
1416
1417 codec->control_data = lm49453->regmap;
1418
1419 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1420 if (ret < 0) {
1421 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1422 return ret;
1423 }
1424
1425 return 0;
1426 }
1427
1428 /* power down chip */
1429 static int lm49453_remove(struct snd_soc_codec *codec)
1430 {
1431 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1432 return 0;
1433 }
1434
1435 static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1436 .probe = lm49453_probe,
1437 .remove = lm49453_remove,
1438 .suspend = lm49453_suspend,
1439 .resume = lm49453_resume,
1440 .set_bias_level = lm49453_set_bias_level,
1441 .controls = lm49453_snd_controls,
1442 .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1443 .dapm_widgets = lm49453_dapm_widgets,
1444 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1445 .dapm_routes = lm49453_audio_map,
1446 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1447 .idle_bias_off = true,
1448 };
1449
1450 static const struct regmap_config lm49453_regmap_config = {
1451 .reg_bits = 8,
1452 .val_bits = 8,
1453
1454 .max_register = LM49453_MAX_REGISTER,
1455 .reg_defaults = lm49453_reg_defs,
1456 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1457 .cache_type = REGCACHE_RBTREE,
1458 };
1459
1460 static int lm49453_i2c_probe(struct i2c_client *i2c,
1461 const struct i2c_device_id *id)
1462 {
1463 struct lm49453_priv *lm49453;
1464 int ret = 0;
1465
1466 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1467 GFP_KERNEL);
1468
1469 if (lm49453 == NULL)
1470 return -ENOMEM;
1471
1472 i2c_set_clientdata(i2c, lm49453);
1473
1474 lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
1475 if (IS_ERR(lm49453->regmap)) {
1476 ret = PTR_ERR(lm49453->regmap);
1477 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1478 ret);
1479 return ret;
1480 }
1481
1482 ret = snd_soc_register_codec(&i2c->dev,
1483 &soc_codec_dev_lm49453,
1484 lm49453_dai, ARRAY_SIZE(lm49453_dai));
1485 if (ret < 0)
1486 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1487
1488 return ret;
1489 }
1490
1491 static int lm49453_i2c_remove(struct i2c_client *client)
1492 {
1493 snd_soc_unregister_codec(&client->dev);
1494 return 0;
1495 }
1496
1497 static const struct i2c_device_id lm49453_i2c_id[] = {
1498 { "lm49453", 0 },
1499 { }
1500 };
1501 MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1502
1503 static struct i2c_driver lm49453_i2c_driver = {
1504 .driver = {
1505 .name = "lm49453",
1506 .owner = THIS_MODULE,
1507 },
1508 .probe = lm49453_i2c_probe,
1509 .remove = lm49453_i2c_remove,
1510 .id_table = lm49453_i2c_id,
1511 };
1512
1513 module_i2c_driver(lm49453_i2c_driver);
1514
1515 MODULE_DESCRIPTION("ASoC LM49453 driver");
1516 MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
1517 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support