?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/xen: resume timer irqs early
[linux/fpc-iii.git] / sound / soc / codecs / max98088.c
blob566a367c94fa0ce71ac04f86686923ed63ece58d
1 /*
2 * max98088.c -- MAX98088 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <linux/slab.h>
25 #include <asm/div64.h>
26 #include <sound/max98088.h>
27 #include "max98088.h"
28
29 enum max98088_type {
30 MAX98088,
31 MAX98089,
32 };
33
34 struct max98088_cdata {
35 unsigned int rate;
36 unsigned int fmt;
37 int eq_sel;
38 };
39
40 struct max98088_priv {
41 enum max98088_type devtype;
42 struct max98088_pdata *pdata;
43 unsigned int sysclk;
44 struct max98088_cdata dai[2];
45 int eq_textcnt;
46 const char **eq_texts;
47 struct soc_enum eq_enum;
48 u8 ina_state;
49 u8 inb_state;
50 unsigned int ex_mode;
51 unsigned int digmic;
52 unsigned int mic1pre;
53 unsigned int mic2pre;
54 unsigned int extmic_mode;
55 };
56
57 static const u8 max98088_reg[M98088_REG_CNT] = {
58 0x00, /* 00 IRQ status */
59 0x00, /* 01 MIC status */
60 0x00, /* 02 jack status */
61 0x00, /* 03 battery voltage */
62 0x00, /* 04 */
63 0x00, /* 05 */
64 0x00, /* 06 */
65 0x00, /* 07 */
66 0x00, /* 08 */
67 0x00, /* 09 */
68 0x00, /* 0A */
69 0x00, /* 0B */
70 0x00, /* 0C */
71 0x00, /* 0D */
72 0x00, /* 0E */
73 0x00, /* 0F interrupt enable */
74
75 0x00, /* 10 master clock */
76 0x00, /* 11 DAI1 clock mode */
77 0x00, /* 12 DAI1 clock control */
78 0x00, /* 13 DAI1 clock control */
79 0x00, /* 14 DAI1 format */
80 0x00, /* 15 DAI1 clock */
81 0x00, /* 16 DAI1 config */
82 0x00, /* 17 DAI1 TDM */
83 0x00, /* 18 DAI1 filters */
84 0x00, /* 19 DAI2 clock mode */
85 0x00, /* 1A DAI2 clock control */
86 0x00, /* 1B DAI2 clock control */
87 0x00, /* 1C DAI2 format */
88 0x00, /* 1D DAI2 clock */
89 0x00, /* 1E DAI2 config */
90 0x00, /* 1F DAI2 TDM */
91
92 0x00, /* 20 DAI2 filters */
93 0x00, /* 21 data config */
94 0x00, /* 22 DAC mixer */
95 0x00, /* 23 left ADC mixer */
96 0x00, /* 24 right ADC mixer */
97 0x00, /* 25 left HP mixer */
98 0x00, /* 26 right HP mixer */
99 0x00, /* 27 HP control */
100 0x00, /* 28 left REC mixer */
101 0x00, /* 29 right REC mixer */
102 0x00, /* 2A REC control */
103 0x00, /* 2B left SPK mixer */
104 0x00, /* 2C right SPK mixer */
105 0x00, /* 2D SPK control */
106 0x00, /* 2E sidetone */
107 0x00, /* 2F DAI1 playback level */
108
109 0x00, /* 30 DAI1 playback level */
110 0x00, /* 31 DAI2 playback level */
111 0x00, /* 32 DAI2 playbakc level */
112 0x00, /* 33 left ADC level */
113 0x00, /* 34 right ADC level */
114 0x00, /* 35 MIC1 level */
115 0x00, /* 36 MIC2 level */
116 0x00, /* 37 INA level */
117 0x00, /* 38 INB level */
118 0x00, /* 39 left HP volume */
119 0x00, /* 3A right HP volume */
120 0x00, /* 3B left REC volume */
121 0x00, /* 3C right REC volume */
122 0x00, /* 3D left SPK volume */
123 0x00, /* 3E right SPK volume */
124 0x00, /* 3F MIC config */
125
126 0x00, /* 40 MIC threshold */
127 0x00, /* 41 excursion limiter filter */
128 0x00, /* 42 excursion limiter threshold */
129 0x00, /* 43 ALC */
130 0x00, /* 44 power limiter threshold */
131 0x00, /* 45 power limiter config */
132 0x00, /* 46 distortion limiter config */
133 0x00, /* 47 audio input */
134 0x00, /* 48 microphone */
135 0x00, /* 49 level control */
136 0x00, /* 4A bypass switches */
137 0x00, /* 4B jack detect */
138 0x00, /* 4C input enable */
139 0x00, /* 4D output enable */
140 0xF0, /* 4E bias control */
141 0x00, /* 4F DAC power */
142
143 0x0F, /* 50 DAC power */
144 0x00, /* 51 system */
145 0x00, /* 52 DAI1 EQ1 */
146 0x00, /* 53 DAI1 EQ1 */
147 0x00, /* 54 DAI1 EQ1 */
148 0x00, /* 55 DAI1 EQ1 */
149 0x00, /* 56 DAI1 EQ1 */
150 0x00, /* 57 DAI1 EQ1 */
151 0x00, /* 58 DAI1 EQ1 */
152 0x00, /* 59 DAI1 EQ1 */
153 0x00, /* 5A DAI1 EQ1 */
154 0x00, /* 5B DAI1 EQ1 */
155 0x00, /* 5C DAI1 EQ2 */
156 0x00, /* 5D DAI1 EQ2 */
157 0x00, /* 5E DAI1 EQ2 */
158 0x00, /* 5F DAI1 EQ2 */
159
160 0x00, /* 60 DAI1 EQ2 */
161 0x00, /* 61 DAI1 EQ2 */
162 0x00, /* 62 DAI1 EQ2 */
163 0x00, /* 63 DAI1 EQ2 */
164 0x00, /* 64 DAI1 EQ2 */
165 0x00, /* 65 DAI1 EQ2 */
166 0x00, /* 66 DAI1 EQ3 */
167 0x00, /* 67 DAI1 EQ3 */
168 0x00, /* 68 DAI1 EQ3 */
169 0x00, /* 69 DAI1 EQ3 */
170 0x00, /* 6A DAI1 EQ3 */
171 0x00, /* 6B DAI1 EQ3 */
172 0x00, /* 6C DAI1 EQ3 */
173 0x00, /* 6D DAI1 EQ3 */
174 0x00, /* 6E DAI1 EQ3 */
175 0x00, /* 6F DAI1 EQ3 */
176
177 0x00, /* 70 DAI1 EQ4 */
178 0x00, /* 71 DAI1 EQ4 */
179 0x00, /* 72 DAI1 EQ4 */
180 0x00, /* 73 DAI1 EQ4 */
181 0x00, /* 74 DAI1 EQ4 */
182 0x00, /* 75 DAI1 EQ4 */
183 0x00, /* 76 DAI1 EQ4 */
184 0x00, /* 77 DAI1 EQ4 */
185 0x00, /* 78 DAI1 EQ4 */
186 0x00, /* 79 DAI1 EQ4 */
187 0x00, /* 7A DAI1 EQ5 */
188 0x00, /* 7B DAI1 EQ5 */
189 0x00, /* 7C DAI1 EQ5 */
190 0x00, /* 7D DAI1 EQ5 */
191 0x00, /* 7E DAI1 EQ5 */
192 0x00, /* 7F DAI1 EQ5 */
193
194 0x00, /* 80 DAI1 EQ5 */
195 0x00, /* 81 DAI1 EQ5 */
196 0x00, /* 82 DAI1 EQ5 */
197 0x00, /* 83 DAI1 EQ5 */
198 0x00, /* 84 DAI2 EQ1 */
199 0x00, /* 85 DAI2 EQ1 */
200 0x00, /* 86 DAI2 EQ1 */
201 0x00, /* 87 DAI2 EQ1 */
202 0x00, /* 88 DAI2 EQ1 */
203 0x00, /* 89 DAI2 EQ1 */
204 0x00, /* 8A DAI2 EQ1 */
205 0x00, /* 8B DAI2 EQ1 */
206 0x00, /* 8C DAI2 EQ1 */
207 0x00, /* 8D DAI2 EQ1 */
208 0x00, /* 8E DAI2 EQ2 */
209 0x00, /* 8F DAI2 EQ2 */
210
211 0x00, /* 90 DAI2 EQ2 */
212 0x00, /* 91 DAI2 EQ2 */
213 0x00, /* 92 DAI2 EQ2 */
214 0x00, /* 93 DAI2 EQ2 */
215 0x00, /* 94 DAI2 EQ2 */
216 0x00, /* 95 DAI2 EQ2 */
217 0x00, /* 96 DAI2 EQ2 */
218 0x00, /* 97 DAI2 EQ2 */
219 0x00, /* 98 DAI2 EQ3 */
220 0x00, /* 99 DAI2 EQ3 */
221 0x00, /* 9A DAI2 EQ3 */
222 0x00, /* 9B DAI2 EQ3 */
223 0x00, /* 9C DAI2 EQ3 */
224 0x00, /* 9D DAI2 EQ3 */
225 0x00, /* 9E DAI2 EQ3 */
226 0x00, /* 9F DAI2 EQ3 */
227
228 0x00, /* A0 DAI2 EQ3 */
229 0x00, /* A1 DAI2 EQ3 */
230 0x00, /* A2 DAI2 EQ4 */
231 0x00, /* A3 DAI2 EQ4 */
232 0x00, /* A4 DAI2 EQ4 */
233 0x00, /* A5 DAI2 EQ4 */
234 0x00, /* A6 DAI2 EQ4 */
235 0x00, /* A7 DAI2 EQ4 */
236 0x00, /* A8 DAI2 EQ4 */
237 0x00, /* A9 DAI2 EQ4 */
238 0x00, /* AA DAI2 EQ4 */
239 0x00, /* AB DAI2 EQ4 */
240 0x00, /* AC DAI2 EQ5 */
241 0x00, /* AD DAI2 EQ5 */
242 0x00, /* AE DAI2 EQ5 */
243 0x00, /* AF DAI2 EQ5 */
244
245 0x00, /* B0 DAI2 EQ5 */
246 0x00, /* B1 DAI2 EQ5 */
247 0x00, /* B2 DAI2 EQ5 */
248 0x00, /* B3 DAI2 EQ5 */
249 0x00, /* B4 DAI2 EQ5 */
250 0x00, /* B5 DAI2 EQ5 */
251 0x00, /* B6 DAI1 biquad */
252 0x00, /* B7 DAI1 biquad */
253 0x00, /* B8 DAI1 biquad */
254 0x00, /* B9 DAI1 biquad */
255 0x00, /* BA DAI1 biquad */
256 0x00, /* BB DAI1 biquad */
257 0x00, /* BC DAI1 biquad */
258 0x00, /* BD DAI1 biquad */
259 0x00, /* BE DAI1 biquad */
260 0x00, /* BF DAI1 biquad */
261
262 0x00, /* C0 DAI2 biquad */
263 0x00, /* C1 DAI2 biquad */
264 0x00, /* C2 DAI2 biquad */
265 0x00, /* C3 DAI2 biquad */
266 0x00, /* C4 DAI2 biquad */
267 0x00, /* C5 DAI2 biquad */
268 0x00, /* C6 DAI2 biquad */
269 0x00, /* C7 DAI2 biquad */
270 0x00, /* C8 DAI2 biquad */
271 0x00, /* C9 DAI2 biquad */
272 0x00, /* CA */
273 0x00, /* CB */
274 0x00, /* CC */
275 0x00, /* CD */
276 0x00, /* CE */
277 0x00, /* CF */
278
279 0x00, /* D0 */
280 0x00, /* D1 */
281 0x00, /* D2 */
282 0x00, /* D3 */
283 0x00, /* D4 */
284 0x00, /* D5 */
285 0x00, /* D6 */
286 0x00, /* D7 */
287 0x00, /* D8 */
288 0x00, /* D9 */
289 0x00, /* DA */
290 0x70, /* DB */
291 0x00, /* DC */
292 0x00, /* DD */
293 0x00, /* DE */
294 0x00, /* DF */
295
296 0x00, /* E0 */
297 0x00, /* E1 */
298 0x00, /* E2 */
299 0x00, /* E3 */
300 0x00, /* E4 */
301 0x00, /* E5 */
302 0x00, /* E6 */
303 0x00, /* E7 */
304 0x00, /* E8 */
305 0x00, /* E9 */
306 0x00, /* EA */
307 0x00, /* EB */
308 0x00, /* EC */
309 0x00, /* ED */
310 0x00, /* EE */
311 0x00, /* EF */
312
313 0x00, /* F0 */
314 0x00, /* F1 */
315 0x00, /* F2 */
316 0x00, /* F3 */
317 0x00, /* F4 */
318 0x00, /* F5 */
319 0x00, /* F6 */
320 0x00, /* F7 */
321 0x00, /* F8 */
322 0x00, /* F9 */
323 0x00, /* FA */
324 0x00, /* FB */
325 0x00, /* FC */
326 0x00, /* FD */
327 0x00, /* FE */
328 0x00, /* FF */
329 };
330
331 static struct {
332 int readable;
333 int writable;
334 int vol;
335 } max98088_access[M98088_REG_CNT] = {
336 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
337 { 0xFF, 0x00, 1 }, /* 01 MIC status */
338 { 0xFF, 0x00, 1 }, /* 02 jack status */
339 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
340 { 0xFF, 0xFF, 0 }, /* 04 */
341 { 0xFF, 0xFF, 0 }, /* 05 */
342 { 0xFF, 0xFF, 0 }, /* 06 */
343 { 0xFF, 0xFF, 0 }, /* 07 */
344 { 0xFF, 0xFF, 0 }, /* 08 */
345 { 0xFF, 0xFF, 0 }, /* 09 */
346 { 0xFF, 0xFF, 0 }, /* 0A */
347 { 0xFF, 0xFF, 0 }, /* 0B */
348 { 0xFF, 0xFF, 0 }, /* 0C */
349 { 0xFF, 0xFF, 0 }, /* 0D */
350 { 0xFF, 0xFF, 0 }, /* 0E */
351 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
352
353 { 0xFF, 0xFF, 0 }, /* 10 master clock */
354 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
355 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
356 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
357 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
358 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
359 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
360 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
361 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
362 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
363 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
364 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
365 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
366 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
367 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
368 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
369
370 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
371 { 0xFF, 0xFF, 0 }, /* 21 data config */
372 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
373 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
374 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
375 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
376 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
377 { 0xFF, 0xFF, 0 }, /* 27 HP control */
378 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
379 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
380 { 0xFF, 0xFF, 0 }, /* 2A REC control */
381 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
382 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
383 { 0xFF, 0xFF, 0 }, /* 2D SPK control */
384 { 0xFF, 0xFF, 0 }, /* 2E sidetone */
385 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
386
387 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
388 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
389 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
390 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
391 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
392 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
393 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
394 { 0xFF, 0xFF, 0 }, /* 37 INA level */
395 { 0xFF, 0xFF, 0 }, /* 38 INB level */
396 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
397 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
398 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
399 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
400 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
401 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
402 { 0xFF, 0xFF, 0 }, /* 3F MIC config */
403
404 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
405 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
406 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
407 { 0xFF, 0xFF, 0 }, /* 43 ALC */
408 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
409 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
410 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
411 { 0xFF, 0xFF, 0 }, /* 47 audio input */
412 { 0xFF, 0xFF, 0 }, /* 48 microphone */
413 { 0xFF, 0xFF, 0 }, /* 49 level control */
414 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
415 { 0xFF, 0xFF, 0 }, /* 4B jack detect */
416 { 0xFF, 0xFF, 0 }, /* 4C input enable */
417 { 0xFF, 0xFF, 0 }, /* 4D output enable */
418 { 0xFF, 0xFF, 0 }, /* 4E bias control */
419 { 0xFF, 0xFF, 0 }, /* 4F DAC power */
420
421 { 0xFF, 0xFF, 0 }, /* 50 DAC power */
422 { 0xFF, 0xFF, 0 }, /* 51 system */
423 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
424 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
425 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
426 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
427 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
428 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
429 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
430 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
431 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
432 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
433 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
434 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
435 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
436 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
437
438 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
439 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
440 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
441 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
442 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
443 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
444 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
445 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
446 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
447 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
448 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
449 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
450 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
451 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
452 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
453 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
454
455 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
456 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
457 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
458 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
459 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
460 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
461 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
462 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
463 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
464 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
465 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
466 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
467 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
468 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
469 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
470 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
471
472 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
473 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
474 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
475 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
476 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
477 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
478 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
479 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
480 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
481 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
482 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
483 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
484 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
485 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
486 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
487 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
488
489 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
490 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
491 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
492 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
493 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
494 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
495 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
496 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
497 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
498 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
499 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
500 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
501 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
502 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
503 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
504 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
505
506 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
507 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
508 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
509 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
510 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
511 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
512 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
513 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
514 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
515 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
516 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
517 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
518 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
519 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
520 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
521 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
522
523 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
524 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
525 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
526 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
527 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
528 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
529 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
530 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
531 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
532 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
533 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
534 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
535 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
536 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
537 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
538 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
539
540 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
541 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
542 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
543 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
544 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
545 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
546 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
547 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
548 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
549 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
550 { 0x00, 0x00, 0 }, /* CA */
551 { 0x00, 0x00, 0 }, /* CB */
552 { 0x00, 0x00, 0 }, /* CC */
553 { 0x00, 0x00, 0 }, /* CD */
554 { 0x00, 0x00, 0 }, /* CE */
555 { 0x00, 0x00, 0 }, /* CF */
556
557 { 0x00, 0x00, 0 }, /* D0 */
558 { 0x00, 0x00, 0 }, /* D1 */
559 { 0x00, 0x00, 0 }, /* D2 */
560 { 0x00, 0x00, 0 }, /* D3 */
561 { 0x00, 0x00, 0 }, /* D4 */
562 { 0x00, 0x00, 0 }, /* D5 */
563 { 0x00, 0x00, 0 }, /* D6 */
564 { 0x00, 0x00, 0 }, /* D7 */
565 { 0x00, 0x00, 0 }, /* D8 */
566 { 0x00, 0x00, 0 }, /* D9 */
567 { 0x00, 0x00, 0 }, /* DA */
568 { 0x00, 0x00, 0 }, /* DB */
569 { 0x00, 0x00, 0 }, /* DC */
570 { 0x00, 0x00, 0 }, /* DD */
571 { 0x00, 0x00, 0 }, /* DE */
572 { 0x00, 0x00, 0 }, /* DF */
573
574 { 0x00, 0x00, 0 }, /* E0 */
575 { 0x00, 0x00, 0 }, /* E1 */
576 { 0x00, 0x00, 0 }, /* E2 */
577 { 0x00, 0x00, 0 }, /* E3 */
578 { 0x00, 0x00, 0 }, /* E4 */
579 { 0x00, 0x00, 0 }, /* E5 */
580 { 0x00, 0x00, 0 }, /* E6 */
581 { 0x00, 0x00, 0 }, /* E7 */
582 { 0x00, 0x00, 0 }, /* E8 */
583 { 0x00, 0x00, 0 }, /* E9 */
584 { 0x00, 0x00, 0 }, /* EA */
585 { 0x00, 0x00, 0 }, /* EB */
586 { 0x00, 0x00, 0 }, /* EC */
587 { 0x00, 0x00, 0 }, /* ED */
588 { 0x00, 0x00, 0 }, /* EE */
589 { 0x00, 0x00, 0 }, /* EF */
590
591 { 0x00, 0x00, 0 }, /* F0 */
592 { 0x00, 0x00, 0 }, /* F1 */
593 { 0x00, 0x00, 0 }, /* F2 */
594 { 0x00, 0x00, 0 }, /* F3 */
595 { 0x00, 0x00, 0 }, /* F4 */
596 { 0x00, 0x00, 0 }, /* F5 */
597 { 0x00, 0x00, 0 }, /* F6 */
598 { 0x00, 0x00, 0 }, /* F7 */
599 { 0x00, 0x00, 0 }, /* F8 */
600 { 0x00, 0x00, 0 }, /* F9 */
601 { 0x00, 0x00, 0 }, /* FA */
602 { 0x00, 0x00, 0 }, /* FB */
603 { 0x00, 0x00, 0 }, /* FC */
604 { 0x00, 0x00, 0 }, /* FD */
605 { 0x00, 0x00, 0 }, /* FE */
606 { 0xFF, 0x00, 1 }, /* FF */
607 };
608
609 static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
610 {
611 return max98088_access[reg].vol;
612 }
613
614
615 /*
616 * Load equalizer DSP coefficient configurations registers
617 */
618 static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
619 unsigned int band, u16 *coefs)
620 {
621 unsigned int eq_reg;
622 unsigned int i;
623
624 BUG_ON(band > 4);
625 BUG_ON(dai > 1);
626
627 /* Load the base register address */
628 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
629
630 /* Add the band address offset, note adjustment for word address */
631 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
632
633 /* Step through the registers and coefs */
634 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
635 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
636 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
637 }
638 }
639
640 /*
641 * Excursion limiter modes
642 */
643 static const char *max98088_exmode_texts[] = {
644 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
645 "400-600Hz", "400-800Hz",
646 };
647
648 static const unsigned int max98088_exmode_values[] = {
649 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
650 };
651
652 static const struct soc_enum max98088_exmode_enum =
653 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
654 ARRAY_SIZE(max98088_exmode_texts),
655 max98088_exmode_texts,
656 max98088_exmode_values);
657
658 static const char *max98088_ex_thresh[] = { /* volts PP */
659 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
660 static const struct soc_enum max98088_ex_thresh_enum[] = {
661 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
662 max98088_ex_thresh),
663 };
664
665 static const char *max98088_fltr_mode[] = {"Voice", "Music" };
666 static const struct soc_enum max98088_filter_mode_enum[] = {
667 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
668 };
669
670 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
671
672 static const struct soc_enum max98088_extmic_enum =
673 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
674
675 static const struct snd_kcontrol_new max98088_extmic_mux =
676 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
677
678 static const char *max98088_dai1_fltr[] = {
679 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
680 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
681 static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
682 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
683 };
684 static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
685 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
686 };
687
688 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
689 struct snd_ctl_elem_value *ucontrol)
690 {
691 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
692 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
693 unsigned int sel = ucontrol->value.integer.value[0];
694
695 max98088->mic1pre = sel;
696 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
697 (1+sel)<<M98088_MICPRE_SHIFT);
698
699 return 0;
700 }
701
702 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
703 struct snd_ctl_elem_value *ucontrol)
704 {
705 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
706 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
707
708 ucontrol->value.integer.value[0] = max98088->mic1pre;
709 return 0;
710 }
711
712 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
713 struct snd_ctl_elem_value *ucontrol)
714 {
715 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
716 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
717 unsigned int sel = ucontrol->value.integer.value[0];
718
719 max98088->mic2pre = sel;
720 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
721 (1+sel)<<M98088_MICPRE_SHIFT);
722
723 return 0;
724 }
725
726 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
727 struct snd_ctl_elem_value *ucontrol)
728 {
729 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
730 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
731
732 ucontrol->value.integer.value[0] = max98088->mic2pre;
733 return 0;
734 }
735
736 static const unsigned int max98088_micboost_tlv[] = {
737 TLV_DB_RANGE_HEAD(2),
738 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
739 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
740 };
741
742 static const unsigned int max98088_hp_tlv[] = {
743 TLV_DB_RANGE_HEAD(5),
744 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
745 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
746 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
747 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
748 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
749 };
750
751 static const unsigned int max98088_spk_tlv[] = {
752 TLV_DB_RANGE_HEAD(5),
753 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
754 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
755 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
756 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
757 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
758 };
759
760 static const struct snd_kcontrol_new max98088_snd_controls[] = {
761
762 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
763 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
764 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
765 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
766 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
767 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
768
769 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
770 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
771 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
772 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
773 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
774 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
775
776 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
777 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
778
779 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
780 M98088_REG_35_LVL_MIC1, 5, 2, 0,
781 max98088_mic1pre_get, max98088_mic1pre_set,
782 max98088_micboost_tlv),
783 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
784 M98088_REG_36_LVL_MIC2, 5, 2, 0,
785 max98088_mic2pre_get, max98088_mic2pre_set,
786 max98088_micboost_tlv),
787
788 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
789 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
790
791 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
792 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
793
794 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
795 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
796
797 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
798 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
799
800 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
801 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
802
803 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
804 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
805 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
806 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
807 0, 1, 0),
808
809 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
810 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
811 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
812 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
813
814 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
815 4, 15, 0),
816 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
817 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
818 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
819
820 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
821 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
822 };
823
824 /* Left speaker mixer switch */
825 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
826 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
827 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
828 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
829 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
830 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
831 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
832 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
833 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
834 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
835 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
836 };
837
838 /* Right speaker mixer switch */
839 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
840 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
841 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
842 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
843 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
844 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
845 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
846 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
847 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
848 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
849 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
850 };
851
852 /* Left headphone mixer switch */
853 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
854 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
855 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
856 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
857 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
858 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
859 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
860 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
861 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
862 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
863 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
864 };
865
866 /* Right headphone mixer switch */
867 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
868 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
869 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
870 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
871 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
872 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
873 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
874 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
875 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
876 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
877 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
878 };
879
880 /* Left earpiece/receiver mixer switch */
881 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
882 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
883 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
884 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
885 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
886 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
887 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
888 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
889 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
890 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
891 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
892 };
893
894 /* Right earpiece/receiver mixer switch */
895 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
896 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
897 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
898 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
899 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
900 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
901 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
902 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
903 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
904 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
905 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
906 };
907
908 /* Left ADC mixer switch */
909 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
910 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
911 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
912 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
913 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
914 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
915 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
916 };
917
918 /* Right ADC mixer switch */
919 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
920 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
921 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
922 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
923 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
924 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
925 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
926 };
927
928 static int max98088_mic_event(struct snd_soc_dapm_widget *w,
929 struct snd_kcontrol *kcontrol, int event)
930 {
931 struct snd_soc_codec *codec = w->codec;
932 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
933
934 switch (event) {
935 case SND_SOC_DAPM_POST_PMU:
936 if (w->reg == M98088_REG_35_LVL_MIC1) {
937 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
938 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
939 } else {
940 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
941 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
942 }
943 break;
944 case SND_SOC_DAPM_POST_PMD:
945 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
946 break;
947 default:
948 return -EINVAL;
949 }
950
951 return 0;
952 }
953
954 /*
955 * The line inputs are 2-channel stereo inputs with the left
956 * and right channels sharing a common PGA power control signal.
957 */
958 static int max98088_line_pga(struct snd_soc_dapm_widget *w,
959 int event, int line, u8 channel)
960 {
961 struct snd_soc_codec *codec = w->codec;
962 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
963 u8 *state;
964
965 BUG_ON(!((channel == 1) || (channel == 2)));
966
967 switch (line) {
968 case LINE_INA:
969 state = &max98088->ina_state;
970 break;
971 case LINE_INB:
972 state = &max98088->inb_state;
973 break;
974 default:
975 return -EINVAL;
976 }
977
978 switch (event) {
979 case SND_SOC_DAPM_POST_PMU:
980 *state |= channel;
981 snd_soc_update_bits(codec, w->reg,
982 (1 << w->shift), (1 << w->shift));
983 break;
984 case SND_SOC_DAPM_POST_PMD:
985 *state &= ~channel;
986 if (*state == 0) {
987 snd_soc_update_bits(codec, w->reg,
988 (1 << w->shift), 0);
989 }
990 break;
991 default:
992 return -EINVAL;
993 }
994
995 return 0;
996 }
997
998 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
999 struct snd_kcontrol *k, int event)
1000 {
1001 return max98088_line_pga(w, event, LINE_INA, 1);
1002 }
1003
1004 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
1005 struct snd_kcontrol *k, int event)
1006 {
1007 return max98088_line_pga(w, event, LINE_INA, 2);
1008 }
1009
1010 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
1011 struct snd_kcontrol *k, int event)
1012 {
1013 return max98088_line_pga(w, event, LINE_INB, 1);
1014 }
1015
1016 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
1017 struct snd_kcontrol *k, int event)
1018 {
1019 return max98088_line_pga(w, event, LINE_INB, 2);
1020 }
1021
1022 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
1023
1024 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
1025 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
1026
1027 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
1028 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1029 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
1030 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1031 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
1032 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1033 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
1034 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1035
1036 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
1037 7, 0, NULL, 0),
1038 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
1039 6, 0, NULL, 0),
1040
1041 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
1042 5, 0, NULL, 0),
1043 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
1044 4, 0, NULL, 0),
1045
1046 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
1047 3, 0, NULL, 0),
1048 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
1049 2, 0, NULL, 0),
1050
1051 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1052 &max98088_extmic_mux),
1053
1054 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1055 &max98088_left_hp_mixer_controls[0],
1056 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1057
1058 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1059 &max98088_right_hp_mixer_controls[0],
1060 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1061
1062 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1063 &max98088_left_speaker_mixer_controls[0],
1064 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1065
1066 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1067 &max98088_right_speaker_mixer_controls[0],
1068 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1069
1070 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1071 &max98088_left_rec_mixer_controls[0],
1072 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1073
1074 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1075 &max98088_right_rec_mixer_controls[0],
1076 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1077
1078 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1079 &max98088_left_ADC_mixer_controls[0],
1080 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1081
1082 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1083 &max98088_right_ADC_mixer_controls[0],
1084 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1085
1086 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1087 5, 0, NULL, 0, max98088_mic_event,
1088 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1089
1090 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1091 5, 0, NULL, 0, max98088_mic_event,
1092 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1093
1094 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1095 7, 0, NULL, 0, max98088_pga_ina1_event,
1096 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1097
1098 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1099 7, 0, NULL, 0, max98088_pga_ina2_event,
1100 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1101
1102 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1103 6, 0, NULL, 0, max98088_pga_inb1_event,
1104 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1105
1106 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1107 6, 0, NULL, 0, max98088_pga_inb2_event,
1108 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1109
1110 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1111
1112 SND_SOC_DAPM_OUTPUT("HPL"),
1113 SND_SOC_DAPM_OUTPUT("HPR"),
1114 SND_SOC_DAPM_OUTPUT("SPKL"),
1115 SND_SOC_DAPM_OUTPUT("SPKR"),
1116 SND_SOC_DAPM_OUTPUT("RECL"),
1117 SND_SOC_DAPM_OUTPUT("RECR"),
1118
1119 SND_SOC_DAPM_INPUT("MIC1"),
1120 SND_SOC_DAPM_INPUT("MIC2"),
1121 SND_SOC_DAPM_INPUT("INA1"),
1122 SND_SOC_DAPM_INPUT("INA2"),
1123 SND_SOC_DAPM_INPUT("INB1"),
1124 SND_SOC_DAPM_INPUT("INB2"),
1125 };
1126
1127 static const struct snd_soc_dapm_route max98088_audio_map[] = {
1128 /* Left headphone output mixer */
1129 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1130 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1131 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1132 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1133 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1134 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1135 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1136 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1137 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1138 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1139
1140 /* Right headphone output mixer */
1141 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1142 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1143 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1144 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1145 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1146 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1147 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1148 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1149 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1150 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1151
1152 /* Left speaker output mixer */
1153 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1154 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1155 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1156 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1157 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1158 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1159 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1160 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1161 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1162 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1163
1164 /* Right speaker output mixer */
1165 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1166 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1167 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1168 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1169 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1170 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1171 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1172 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1173 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1174 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1175
1176 /* Earpiece/Receiver output mixer */
1177 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1178 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1179 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1180 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1181 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1182 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1183 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1184 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1185 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1186 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1187
1188 /* Earpiece/Receiver output mixer */
1189 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1190 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1191 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1192 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1193 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1194 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1195 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1196 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1197 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1198 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1199
1200 {"HP Left Out", NULL, "Left HP Mixer"},
1201 {"HP Right Out", NULL, "Right HP Mixer"},
1202 {"SPK Left Out", NULL, "Left SPK Mixer"},
1203 {"SPK Right Out", NULL, "Right SPK Mixer"},
1204 {"REC Left Out", NULL, "Left REC Mixer"},
1205 {"REC Right Out", NULL, "Right REC Mixer"},
1206
1207 {"HPL", NULL, "HP Left Out"},
1208 {"HPR", NULL, "HP Right Out"},
1209 {"SPKL", NULL, "SPK Left Out"},
1210 {"SPKR", NULL, "SPK Right Out"},
1211 {"RECL", NULL, "REC Left Out"},
1212 {"RECR", NULL, "REC Right Out"},
1213
1214 /* Left ADC input mixer */
1215 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1216 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1217 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1218 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1219 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1220 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1221
1222 /* Right ADC input mixer */
1223 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1224 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1225 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1226 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1227 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1228 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1229
1230 /* Inputs */
1231 {"ADCL", NULL, "Left ADC Mixer"},
1232 {"ADCR", NULL, "Right ADC Mixer"},
1233 {"INA1 Input", NULL, "INA1"},
1234 {"INA2 Input", NULL, "INA2"},
1235 {"INB1 Input", NULL, "INB1"},
1236 {"INB2 Input", NULL, "INB2"},
1237 {"MIC1 Input", NULL, "MIC1"},
1238 {"MIC2 Input", NULL, "MIC2"},
1239 };
1240
1241 /* codec mclk clock divider coefficients */
1242 static const struct {
1243 u32 rate;
1244 u8 sr;
1245 } rate_table[] = {
1246 {8000, 0x10},
1247 {11025, 0x20},
1248 {16000, 0x30},
1249 {22050, 0x40},
1250 {24000, 0x50},
1251 {32000, 0x60},
1252 {44100, 0x70},
1253 {48000, 0x80},
1254 {88200, 0x90},
1255 {96000, 0xA0},
1256 };
1257
1258 static inline int rate_value(int rate, u8 *value)
1259 {
1260 int i;
1261
1262 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1263 if (rate_table[i].rate >= rate) {
1264 *value = rate_table[i].sr;
1265 return 0;
1266 }
1267 }
1268 *value = rate_table[0].sr;
1269 return -EINVAL;
1270 }
1271
1272 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1273 struct snd_pcm_hw_params *params,
1274 struct snd_soc_dai *dai)
1275 {
1276 struct snd_soc_codec *codec = dai->codec;
1277 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1278 struct max98088_cdata *cdata;
1279 unsigned long long ni;
1280 unsigned int rate;
1281 u8 regval;
1282
1283 cdata = &max98088->dai[0];
1284
1285 rate = params_rate(params);
1286
1287 switch (params_format(params)) {
1288 case SNDRV_PCM_FORMAT_S16_LE:
1289 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1290 M98088_DAI_WS, 0);
1291 break;
1292 case SNDRV_PCM_FORMAT_S24_LE:
1293 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1294 M98088_DAI_WS, M98088_DAI_WS);
1295 break;
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1301
1302 if (rate_value(rate, &regval))
1303 return -EINVAL;
1304
1305 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1306 M98088_CLKMODE_MASK, regval);
1307 cdata->rate = rate;
1308
1309 /* Configure NI when operating as master */
1310 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1311 & M98088_DAI_MAS) {
1312 if (max98088->sysclk == 0) {
1313 dev_err(codec->dev, "Invalid system clock frequency\n");
1314 return -EINVAL;
1315 }
1316 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1317 * (unsigned long long int)rate;
1318 do_div(ni, (unsigned long long int)max98088->sysclk);
1319 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1320 (ni >> 8) & 0x7F);
1321 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1322 ni & 0xFF);
1323 }
1324
1325 /* Update sample rate mode */
1326 if (rate < 50000)
1327 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1328 M98088_DAI_DHF, 0);
1329 else
1330 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1331 M98088_DAI_DHF, M98088_DAI_DHF);
1332
1333 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1334 M98088_SHDNRUN);
1335
1336 return 0;
1337 }
1338
1339 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1340 struct snd_pcm_hw_params *params,
1341 struct snd_soc_dai *dai)
1342 {
1343 struct snd_soc_codec *codec = dai->codec;
1344 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1345 struct max98088_cdata *cdata;
1346 unsigned long long ni;
1347 unsigned int rate;
1348 u8 regval;
1349
1350 cdata = &max98088->dai[1];
1351
1352 rate = params_rate(params);
1353
1354 switch (params_format(params)) {
1355 case SNDRV_PCM_FORMAT_S16_LE:
1356 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1357 M98088_DAI_WS, 0);
1358 break;
1359 case SNDRV_PCM_FORMAT_S24_LE:
1360 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1361 M98088_DAI_WS, M98088_DAI_WS);
1362 break;
1363 default:
1364 return -EINVAL;
1365 }
1366
1367 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1368
1369 if (rate_value(rate, &regval))
1370 return -EINVAL;
1371
1372 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1373 M98088_CLKMODE_MASK, regval);
1374 cdata->rate = rate;
1375
1376 /* Configure NI when operating as master */
1377 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1378 & M98088_DAI_MAS) {
1379 if (max98088->sysclk == 0) {
1380 dev_err(codec->dev, "Invalid system clock frequency\n");
1381 return -EINVAL;
1382 }
1383 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1384 * (unsigned long long int)rate;
1385 do_div(ni, (unsigned long long int)max98088->sysclk);
1386 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1387 (ni >> 8) & 0x7F);
1388 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1389 ni & 0xFF);
1390 }
1391
1392 /* Update sample rate mode */
1393 if (rate < 50000)
1394 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1395 M98088_DAI_DHF, 0);
1396 else
1397 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1398 M98088_DAI_DHF, M98088_DAI_DHF);
1399
1400 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1401 M98088_SHDNRUN);
1402
1403 return 0;
1404 }
1405
1406 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1407 int clk_id, unsigned int freq, int dir)
1408 {
1409 struct snd_soc_codec *codec = dai->codec;
1410 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1411
1412 /* Requested clock frequency is already setup */
1413 if (freq == max98088->sysclk)
1414 return 0;
1415
1416 /* Setup clocks for slave mode, and using the PLL
1417 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1418 * 0x02 (when master clk is 20MHz to 30MHz)..
1419 */
1420 if ((freq >= 10000000) && (freq < 20000000)) {
1421 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1422 } else if ((freq >= 20000000) && (freq < 30000000)) {
1423 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1424 } else {
1425 dev_err(codec->dev, "Invalid master clock frequency\n");
1426 return -EINVAL;
1427 }
1428
1429 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1430 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1431 M98088_SHDNRUN, 0);
1432 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1433 M98088_SHDNRUN, M98088_SHDNRUN);
1434 }
1435
1436 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1437
1438 max98088->sysclk = freq;
1439 return 0;
1440 }
1441
1442 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1443 unsigned int fmt)
1444 {
1445 struct snd_soc_codec *codec = codec_dai->codec;
1446 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1447 struct max98088_cdata *cdata;
1448 u8 reg15val;
1449 u8 reg14val = 0;
1450
1451 cdata = &max98088->dai[0];
1452
1453 if (fmt != cdata->fmt) {
1454 cdata->fmt = fmt;
1455
1456 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1457 case SND_SOC_DAIFMT_CBS_CFS:
1458 /* Slave mode PLL */
1459 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1460 0x80);
1461 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1462 0x00);
1463 break;
1464 case SND_SOC_DAIFMT_CBM_CFM:
1465 /* Set to master mode */
1466 reg14val |= M98088_DAI_MAS;
1467 break;
1468 case SND_SOC_DAIFMT_CBS_CFM:
1469 case SND_SOC_DAIFMT_CBM_CFS:
1470 default:
1471 dev_err(codec->dev, "Clock mode unsupported");
1472 return -EINVAL;
1473 }
1474
1475 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1476 case SND_SOC_DAIFMT_I2S:
1477 reg14val |= M98088_DAI_DLY;
1478 break;
1479 case SND_SOC_DAIFMT_LEFT_J:
1480 break;
1481 default:
1482 return -EINVAL;
1483 }
1484
1485 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1486 case SND_SOC_DAIFMT_NB_NF:
1487 break;
1488 case SND_SOC_DAIFMT_NB_IF:
1489 reg14val |= M98088_DAI_WCI;
1490 break;
1491 case SND_SOC_DAIFMT_IB_NF:
1492 reg14val |= M98088_DAI_BCI;
1493 break;
1494 case SND_SOC_DAIFMT_IB_IF:
1495 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1502 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1503 M98088_DAI_WCI, reg14val);
1504
1505 reg15val = M98088_DAI_BSEL64;
1506 if (max98088->digmic)
1507 reg15val |= M98088_DAI_OSR64;
1508 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1515 unsigned int fmt)
1516 {
1517 struct snd_soc_codec *codec = codec_dai->codec;
1518 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1519 struct max98088_cdata *cdata;
1520 u8 reg1Cval = 0;
1521
1522 cdata = &max98088->dai[1];
1523
1524 if (fmt != cdata->fmt) {
1525 cdata->fmt = fmt;
1526
1527 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1528 case SND_SOC_DAIFMT_CBS_CFS:
1529 /* Slave mode PLL */
1530 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1531 0x80);
1532 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1533 0x00);
1534 break;
1535 case SND_SOC_DAIFMT_CBM_CFM:
1536 /* Set to master mode */
1537 reg1Cval |= M98088_DAI_MAS;
1538 break;
1539 case SND_SOC_DAIFMT_CBS_CFM:
1540 case SND_SOC_DAIFMT_CBM_CFS:
1541 default:
1542 dev_err(codec->dev, "Clock mode unsupported");
1543 return -EINVAL;
1544 }
1545
1546 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1547 case SND_SOC_DAIFMT_I2S:
1548 reg1Cval |= M98088_DAI_DLY;
1549 break;
1550 case SND_SOC_DAIFMT_LEFT_J:
1551 break;
1552 default:
1553 return -EINVAL;
1554 }
1555
1556 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1557 case SND_SOC_DAIFMT_NB_NF:
1558 break;
1559 case SND_SOC_DAIFMT_NB_IF:
1560 reg1Cval |= M98088_DAI_WCI;
1561 break;
1562 case SND_SOC_DAIFMT_IB_NF:
1563 reg1Cval |= M98088_DAI_BCI;
1564 break;
1565 case SND_SOC_DAIFMT_IB_IF:
1566 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1567 break;
1568 default:
1569 return -EINVAL;
1570 }
1571
1572 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1573 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1574 M98088_DAI_WCI, reg1Cval);
1575
1576 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1577 M98088_DAI_BSEL64);
1578 }
1579
1580 return 0;
1581 }
1582
1583 static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1584 {
1585 struct snd_soc_codec *codec = codec_dai->codec;
1586 int reg;
1587
1588 if (mute)
1589 reg = M98088_DAI_MUTE;
1590 else
1591 reg = 0;
1592
1593 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY,
1594 M98088_DAI_MUTE_MASK, reg);
1595 return 0;
1596 }
1597
1598 static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1599 {
1600 struct snd_soc_codec *codec = codec_dai->codec;
1601 int reg;
1602
1603 if (mute)
1604 reg = M98088_DAI_MUTE;
1605 else
1606 reg = 0;
1607
1608 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY,
1609 M98088_DAI_MUTE_MASK, reg);
1610 return 0;
1611 }
1612
1613 static void max98088_sync_cache(struct snd_soc_codec *codec)
1614 {
1615 u8 *reg_cache = codec->reg_cache;
1616 int i;
1617
1618 if (!codec->cache_sync)
1619 return;
1620
1621 codec->cache_only = 0;
1622
1623 /* write back cached values if they're writeable and
1624 * different from the hardware default.
1625 */
1626 for (i = 1; i < codec->driver->reg_cache_size; i++) {
1627 if (!max98088_access[i].writable)
1628 continue;
1629
1630 if (reg_cache[i] == max98088_reg[i])
1631 continue;
1632
1633 snd_soc_write(codec, i, reg_cache[i]);
1634 }
1635
1636 codec->cache_sync = 0;
1637 }
1638
1639 static int max98088_set_bias_level(struct snd_soc_codec *codec,
1640 enum snd_soc_bias_level level)
1641 {
1642 switch (level) {
1643 case SND_SOC_BIAS_ON:
1644 break;
1645
1646 case SND_SOC_BIAS_PREPARE:
1647 break;
1648
1649 case SND_SOC_BIAS_STANDBY:
1650 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1651 max98088_sync_cache(codec);
1652
1653 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1654 M98088_MBEN, M98088_MBEN);
1655 break;
1656
1657 case SND_SOC_BIAS_OFF:
1658 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1659 M98088_MBEN, 0);
1660 codec->cache_sync = 1;
1661 break;
1662 }
1663 codec->dapm.bias_level = level;
1664 return 0;
1665 }
1666
1667 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1668 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1669
1670 static const struct snd_soc_dai_ops max98088_dai1_ops = {
1671 .set_sysclk = max98088_dai_set_sysclk,
1672 .set_fmt = max98088_dai1_set_fmt,
1673 .hw_params = max98088_dai1_hw_params,
1674 .digital_mute = max98088_dai1_digital_mute,
1675 };
1676
1677 static const struct snd_soc_dai_ops max98088_dai2_ops = {
1678 .set_sysclk = max98088_dai_set_sysclk,
1679 .set_fmt = max98088_dai2_set_fmt,
1680 .hw_params = max98088_dai2_hw_params,
1681 .digital_mute = max98088_dai2_digital_mute,
1682 };
1683
1684 static struct snd_soc_dai_driver max98088_dai[] = {
1685 {
1686 .name = "HiFi",
1687 .playback = {
1688 .stream_name = "HiFi Playback",
1689 .channels_min = 1,
1690 .channels_max = 2,
1691 .rates = MAX98088_RATES,
1692 .formats = MAX98088_FORMATS,
1693 },
1694 .capture = {
1695 .stream_name = "HiFi Capture",
1696 .channels_min = 1,
1697 .channels_max = 2,
1698 .rates = MAX98088_RATES,
1699 .formats = MAX98088_FORMATS,
1700 },
1701 .ops = &max98088_dai1_ops,
1702 },
1703 {
1704 .name = "Aux",
1705 .playback = {
1706 .stream_name = "Aux Playback",
1707 .channels_min = 1,
1708 .channels_max = 2,
1709 .rates = MAX98088_RATES,
1710 .formats = MAX98088_FORMATS,
1711 },
1712 .ops = &max98088_dai2_ops,
1713 }
1714 };
1715
1716 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1717
1718 static int max98088_get_channel(struct snd_soc_codec *codec, const char *name)
1719 {
1720 int i;
1721
1722 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++)
1723 if (strcmp(name, eq_mode_name[i]) == 0)
1724 return i;
1725
1726 /* Shouldn't happen */
1727 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name);
1728 return -EINVAL;
1729 }
1730
1731 static void max98088_setup_eq1(struct snd_soc_codec *codec)
1732 {
1733 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1734 struct max98088_pdata *pdata = max98088->pdata;
1735 struct max98088_eq_cfg *coef_set;
1736 int best, best_val, save, i, sel, fs;
1737 struct max98088_cdata *cdata;
1738
1739 cdata = &max98088->dai[0];
1740
1741 if (!pdata || !max98088->eq_textcnt)
1742 return;
1743
1744 /* Find the selected configuration with nearest sample rate */
1745 fs = cdata->rate;
1746 sel = cdata->eq_sel;
1747
1748 best = 0;
1749 best_val = INT_MAX;
1750 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1751 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1752 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1753 best = i;
1754 best_val = abs(pdata->eq_cfg[i].rate - fs);
1755 }
1756 }
1757
1758 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1759 pdata->eq_cfg[best].name,
1760 pdata->eq_cfg[best].rate, fs);
1761
1762 /* Disable EQ while configuring, and save current on/off state */
1763 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1764 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1765
1766 coef_set = &pdata->eq_cfg[sel];
1767
1768 m98088_eq_band(codec, 0, 0, coef_set->band1);
1769 m98088_eq_band(codec, 0, 1, coef_set->band2);
1770 m98088_eq_band(codec, 0, 2, coef_set->band3);
1771 m98088_eq_band(codec, 0, 3, coef_set->band4);
1772 m98088_eq_band(codec, 0, 4, coef_set->band5);
1773
1774 /* Restore the original on/off state */
1775 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1776 }
1777
1778 static void max98088_setup_eq2(struct snd_soc_codec *codec)
1779 {
1780 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1781 struct max98088_pdata *pdata = max98088->pdata;
1782 struct max98088_eq_cfg *coef_set;
1783 int best, best_val, save, i, sel, fs;
1784 struct max98088_cdata *cdata;
1785
1786 cdata = &max98088->dai[1];
1787
1788 if (!pdata || !max98088->eq_textcnt)
1789 return;
1790
1791 /* Find the selected configuration with nearest sample rate */
1792 fs = cdata->rate;
1793
1794 sel = cdata->eq_sel;
1795 best = 0;
1796 best_val = INT_MAX;
1797 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1798 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1799 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1800 best = i;
1801 best_val = abs(pdata->eq_cfg[i].rate - fs);
1802 }
1803 }
1804
1805 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1806 pdata->eq_cfg[best].name,
1807 pdata->eq_cfg[best].rate, fs);
1808
1809 /* Disable EQ while configuring, and save current on/off state */
1810 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1811 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1812
1813 coef_set = &pdata->eq_cfg[sel];
1814
1815 m98088_eq_band(codec, 1, 0, coef_set->band1);
1816 m98088_eq_band(codec, 1, 1, coef_set->band2);
1817 m98088_eq_band(codec, 1, 2, coef_set->band3);
1818 m98088_eq_band(codec, 1, 3, coef_set->band4);
1819 m98088_eq_band(codec, 1, 4, coef_set->band5);
1820
1821 /* Restore the original on/off state */
1822 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1823 save);
1824 }
1825
1826 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1827 struct snd_ctl_elem_value *ucontrol)
1828 {
1829 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1830 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1831 struct max98088_pdata *pdata = max98088->pdata;
1832 int channel = max98088_get_channel(codec, kcontrol->id.name);
1833 struct max98088_cdata *cdata;
1834 int sel = ucontrol->value.integer.value[0];
1835
1836 if (channel < 0)
1837 return channel;
1838
1839 cdata = &max98088->dai[channel];
1840
1841 if (sel >= pdata->eq_cfgcnt)
1842 return -EINVAL;
1843
1844 cdata->eq_sel = sel;
1845
1846 switch (channel) {
1847 case 0:
1848 max98088_setup_eq1(codec);
1849 break;
1850 case 1:
1851 max98088_setup_eq2(codec);
1852 break;
1853 }
1854
1855 return 0;
1856 }
1857
1858 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1859 struct snd_ctl_elem_value *ucontrol)
1860 {
1861 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1862 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1863 int channel = max98088_get_channel(codec, kcontrol->id.name);
1864 struct max98088_cdata *cdata;
1865
1866 if (channel < 0)
1867 return channel;
1868
1869 cdata = &max98088->dai[channel];
1870 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1871 return 0;
1872 }
1873
1874 static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1875 {
1876 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1877 struct max98088_pdata *pdata = max98088->pdata;
1878 struct max98088_eq_cfg *cfg;
1879 unsigned int cfgcnt;
1880 int i, j;
1881 const char **t;
1882 int ret;
1883 struct snd_kcontrol_new controls[] = {
1884 SOC_ENUM_EXT((char *)eq_mode_name[0],
1885 max98088->eq_enum,
1886 max98088_get_eq_enum,
1887 max98088_put_eq_enum),
1888 SOC_ENUM_EXT((char *)eq_mode_name[1],
1889 max98088->eq_enum,
1890 max98088_get_eq_enum,
1891 max98088_put_eq_enum),
1892 };
1893 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
1894
1895 cfg = pdata->eq_cfg;
1896 cfgcnt = pdata->eq_cfgcnt;
1897
1898 /* Setup an array of texts for the equalizer enum.
1899 * This is based on Mark Brown's equalizer driver code.
1900 */
1901 max98088->eq_textcnt = 0;
1902 max98088->eq_texts = NULL;
1903 for (i = 0; i < cfgcnt; i++) {
1904 for (j = 0; j < max98088->eq_textcnt; j++) {
1905 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1906 break;
1907 }
1908
1909 if (j != max98088->eq_textcnt)
1910 continue;
1911
1912 /* Expand the array */
1913 t = krealloc(max98088->eq_texts,
1914 sizeof(char *) * (max98088->eq_textcnt + 1),
1915 GFP_KERNEL);
1916 if (t == NULL)
1917 continue;
1918
1919 /* Store the new entry */
1920 t[max98088->eq_textcnt] = cfg[i].name;
1921 max98088->eq_textcnt++;
1922 max98088->eq_texts = t;
1923 }
1924
1925 /* Now point the soc_enum to .texts array items */
1926 max98088->eq_enum.texts = max98088->eq_texts;
1927 max98088->eq_enum.max = max98088->eq_textcnt;
1928
1929 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
1930 if (ret != 0)
1931 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1932 }
1933
1934 static void max98088_handle_pdata(struct snd_soc_codec *codec)
1935 {
1936 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1937 struct max98088_pdata *pdata = max98088->pdata;
1938 u8 regval = 0;
1939
1940 if (!pdata) {
1941 dev_dbg(codec->dev, "No platform data\n");
1942 return;
1943 }
1944
1945 /* Configure mic for analog/digital mic mode */
1946 if (pdata->digmic_left_mode)
1947 regval |= M98088_DIGMIC_L;
1948
1949 if (pdata->digmic_right_mode)
1950 regval |= M98088_DIGMIC_R;
1951
1952 max98088->digmic = (regval ? 1 : 0);
1953
1954 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1955
1956 /* Configure receiver output */
1957 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1958 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1959 M98088_REC_LINEMODE_MASK, regval);
1960
1961 /* Configure equalizers */
1962 if (pdata->eq_cfgcnt)
1963 max98088_handle_eq_pdata(codec);
1964 }
1965
1966 #ifdef CONFIG_PM
1967 static int max98088_suspend(struct snd_soc_codec *codec)
1968 {
1969 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
1970
1971 return 0;
1972 }
1973
1974 static int max98088_resume(struct snd_soc_codec *codec)
1975 {
1976 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1977
1978 return 0;
1979 }
1980 #else
1981 #define max98088_suspend NULL
1982 #define max98088_resume NULL
1983 #endif
1984
1985 static int max98088_probe(struct snd_soc_codec *codec)
1986 {
1987 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1988 struct max98088_cdata *cdata;
1989 int ret = 0;
1990
1991 codec->cache_sync = 1;
1992
1993 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1994 if (ret != 0) {
1995 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1996 return ret;
1997 }
1998
1999 /* initialize private data */
2000
2001 max98088->sysclk = (unsigned)-1;
2002 max98088->eq_textcnt = 0;
2003
2004 cdata = &max98088->dai[0];
2005 cdata->rate = (unsigned)-1;
2006 cdata->fmt = (unsigned)-1;
2007 cdata->eq_sel = 0;
2008
2009 cdata = &max98088->dai[1];
2010 cdata->rate = (unsigned)-1;
2011 cdata->fmt = (unsigned)-1;
2012 cdata->eq_sel = 0;
2013
2014 max98088->ina_state = 0;
2015 max98088->inb_state = 0;
2016 max98088->ex_mode = 0;
2017 max98088->digmic = 0;
2018 max98088->mic1pre = 0;
2019 max98088->mic2pre = 0;
2020
2021 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
2022 if (ret < 0) {
2023 dev_err(codec->dev, "Failed to read device revision: %d\n",
2024 ret);
2025 goto err_access;
2026 }
2027 dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A');
2028
2029 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
2030
2031 /* initialize registers cache to hardware default */
2032 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2033
2034 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
2035
2036 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
2037 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
2038 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
2039
2040 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
2041 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
2042
2043 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
2044 M98088_S1NORMAL|M98088_SDATA);
2045
2046 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
2047 M98088_S2NORMAL|M98088_SDATA);
2048
2049 max98088_handle_pdata(codec);
2050
2051 snd_soc_add_codec_controls(codec, max98088_snd_controls,
2052 ARRAY_SIZE(max98088_snd_controls));
2053
2054 err_access:
2055 return ret;
2056 }
2057
2058 static int max98088_remove(struct snd_soc_codec *codec)
2059 {
2060 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
2061
2062 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
2063 kfree(max98088->eq_texts);
2064
2065 return 0;
2066 }
2067
2068 static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
2069 .probe = max98088_probe,
2070 .remove = max98088_remove,
2071 .suspend = max98088_suspend,
2072 .resume = max98088_resume,
2073 .set_bias_level = max98088_set_bias_level,
2074 .reg_cache_size = ARRAY_SIZE(max98088_reg),
2075 .reg_word_size = sizeof(u8),
2076 .reg_cache_default = max98088_reg,
2077 .volatile_register = max98088_volatile_register,
2078 .dapm_widgets = max98088_dapm_widgets,
2079 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
2080 .dapm_routes = max98088_audio_map,
2081 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
2082 };
2083
2084 static int max98088_i2c_probe(struct i2c_client *i2c,
2085 const struct i2c_device_id *id)
2086 {
2087 struct max98088_priv *max98088;
2088 int ret;
2089
2090 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
2091 GFP_KERNEL);
2092 if (max98088 == NULL)
2093 return -ENOMEM;
2094
2095 max98088->devtype = id->driver_data;
2096
2097 i2c_set_clientdata(i2c, max98088);
2098 max98088->pdata = i2c->dev.platform_data;
2099
2100 ret = snd_soc_register_codec(&i2c->dev,
2101 &soc_codec_dev_max98088, &max98088_dai[0], 2);
2102 return ret;
2103 }
2104
2105 static int max98088_i2c_remove(struct i2c_client *client)
2106 {
2107 snd_soc_unregister_codec(&client->dev);
2108 return 0;
2109 }
2110
2111 static const struct i2c_device_id max98088_i2c_id[] = {
2112 { "max98088", MAX98088 },
2113 { "max98089", MAX98089 },
2114 { }
2115 };
2116 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2117
2118 static struct i2c_driver max98088_i2c_driver = {
2119 .driver = {
2120 .name = "max98088",
2121 .owner = THIS_MODULE,
2122 },
2123 .probe = max98088_i2c_probe,
2124 .remove = max98088_i2c_remove,
2125 .id_table = max98088_i2c_id,
2126 };
2127
2128 module_i2c_driver(max98088_i2c_driver);
2129
2130 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2131 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2132 MODULE_LICENSE("GPL");
Linux with added FPC-III support