2 * wm8904.c -- WM8904 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8904.h>
38 #define WM8904_NUM_DCS_CHANNELS 4
40 #define WM8904_NUM_SUPPLIES 5
41 static const char *wm8904_supply_names
[WM8904_NUM_SUPPLIES
] = {
49 /* codec private data */
51 struct regmap
*regmap
;
53 enum wm8904_type devtype
;
55 struct regulator_bulk_data supplies
[WM8904_NUM_SUPPLIES
];
57 struct wm8904_pdata
*pdata
;
61 /* Platform provided DRC configuration */
62 const char **drc_texts
;
64 struct soc_enum drc_enum
;
66 /* Platform provided ReTune mobile configuration */
67 int num_retune_mobile_texts
;
68 const char **retune_mobile_texts
;
69 int retune_mobile_cfg
;
70 struct soc_enum retune_mobile_enum
;
77 /* Clocking configuration */
78 unsigned int mclk_rate
;
80 unsigned int sysclk_rate
;
87 /* DC servo configuration - cached offset values */
88 int dcs_state
[WM8904_NUM_DCS_CHANNELS
];
91 static const struct reg_default wm8904_reg_defaults
[] = {
92 { 4, 0x0018 }, /* R4 - Bias Control 0 */
93 { 5, 0x0000 }, /* R5 - VMID Control 0 */
94 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
95 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
96 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
97 { 9, 0x9696 }, /* R9 - mic Filter Control */
98 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
99 { 12, 0x0000 }, /* R12 - Power Management 0 */
100 { 14, 0x0000 }, /* R14 - Power Management 2 */
101 { 15, 0x0000 }, /* R15 - Power Management 3 */
102 { 18, 0x0000 }, /* R18 - Power Management 6 */
103 { 20, 0x945E }, /* R20 - Clock Rates 0 */
104 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
105 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
106 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
107 { 25, 0x000A }, /* R25 - Audio Interface 1 */
108 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
109 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
110 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
111 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
112 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
113 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
114 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
115 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
116 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
117 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
118 { 40, 0x01AF }, /* R40 - DRC 0 */
119 { 41, 0x3248 }, /* R41 - DRC 1 */
120 { 42, 0x0000 }, /* R42 - DRC 2 */
121 { 43, 0x0000 }, /* R43 - DRC 3 */
122 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
123 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
124 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
125 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
126 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
127 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
128 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
129 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
130 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
131 { 67, 0x0000 }, /* R67 - DC Servo 0 */
132 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
133 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
134 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
135 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
136 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
137 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
138 { 104, 0x0004 }, /* R104 - Class W 0 */
139 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
140 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
141 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
142 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
143 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
144 { 116, 0x0000 }, /* R116 - FLL Control 1 */
145 { 117, 0x0007 }, /* R117 - FLL Control 2 */
146 { 118, 0x0000 }, /* R118 - FLL Control 3 */
147 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
148 { 120, 0x0004 }, /* R120 - FLL Control 5 */
149 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
150 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
151 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
152 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
153 { 126, 0x0000 }, /* R126 - Digital Pulls */
154 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
155 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
156 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
157 { 134, 0x0000 }, /* R134 - EQ1 */
158 { 135, 0x000C }, /* R135 - EQ2 */
159 { 136, 0x000C }, /* R136 - EQ3 */
160 { 137, 0x000C }, /* R137 - EQ4 */
161 { 138, 0x000C }, /* R138 - EQ5 */
162 { 139, 0x000C }, /* R139 - EQ6 */
163 { 140, 0x0FCA }, /* R140 - EQ7 */
164 { 141, 0x0400 }, /* R141 - EQ8 */
165 { 142, 0x00D8 }, /* R142 - EQ9 */
166 { 143, 0x1EB5 }, /* R143 - EQ10 */
167 { 144, 0xF145 }, /* R144 - EQ11 */
168 { 145, 0x0B75 }, /* R145 - EQ12 */
169 { 146, 0x01C5 }, /* R146 - EQ13 */
170 { 147, 0x1C58 }, /* R147 - EQ14 */
171 { 148, 0xF373 }, /* R148 - EQ15 */
172 { 149, 0x0A54 }, /* R149 - EQ16 */
173 { 150, 0x0558 }, /* R150 - EQ17 */
174 { 151, 0x168E }, /* R151 - EQ18 */
175 { 152, 0xF829 }, /* R152 - EQ19 */
176 { 153, 0x07AD }, /* R153 - EQ20 */
177 { 154, 0x1103 }, /* R154 - EQ21 */
178 { 155, 0x0564 }, /* R155 - EQ22 */
179 { 156, 0x0559 }, /* R156 - EQ23 */
180 { 157, 0x4000 }, /* R157 - EQ24 */
181 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
182 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
183 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
184 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
187 static bool wm8904_volatile_register(struct device
*dev
, unsigned int reg
)
190 case WM8904_SW_RESET_AND_ID
:
191 case WM8904_REVISION
:
192 case WM8904_DC_SERVO_1
:
193 case WM8904_DC_SERVO_6
:
194 case WM8904_DC_SERVO_7
:
195 case WM8904_DC_SERVO_8
:
196 case WM8904_DC_SERVO_9
:
197 case WM8904_DC_SERVO_READBACK_0
:
198 case WM8904_INTERRUPT_STATUS
:
205 static bool wm8904_readable_register(struct device
*dev
, unsigned int reg
)
208 case WM8904_SW_RESET_AND_ID
:
209 case WM8904_REVISION
:
210 case WM8904_BIAS_CONTROL_0
:
211 case WM8904_VMID_CONTROL_0
:
212 case WM8904_MIC_BIAS_CONTROL_0
:
213 case WM8904_MIC_BIAS_CONTROL_1
:
214 case WM8904_ANALOGUE_DAC_0
:
215 case WM8904_MIC_FILTER_CONTROL
:
216 case WM8904_ANALOGUE_ADC_0
:
217 case WM8904_POWER_MANAGEMENT_0
:
218 case WM8904_POWER_MANAGEMENT_2
:
219 case WM8904_POWER_MANAGEMENT_3
:
220 case WM8904_POWER_MANAGEMENT_6
:
221 case WM8904_CLOCK_RATES_0
:
222 case WM8904_CLOCK_RATES_1
:
223 case WM8904_CLOCK_RATES_2
:
224 case WM8904_AUDIO_INTERFACE_0
:
225 case WM8904_AUDIO_INTERFACE_1
:
226 case WM8904_AUDIO_INTERFACE_2
:
227 case WM8904_AUDIO_INTERFACE_3
:
228 case WM8904_DAC_DIGITAL_VOLUME_LEFT
:
229 case WM8904_DAC_DIGITAL_VOLUME_RIGHT
:
230 case WM8904_DAC_DIGITAL_0
:
231 case WM8904_DAC_DIGITAL_1
:
232 case WM8904_ADC_DIGITAL_VOLUME_LEFT
:
233 case WM8904_ADC_DIGITAL_VOLUME_RIGHT
:
234 case WM8904_ADC_DIGITAL_0
:
235 case WM8904_DIGITAL_MICROPHONE_0
:
240 case WM8904_ANALOGUE_LEFT_INPUT_0
:
241 case WM8904_ANALOGUE_RIGHT_INPUT_0
:
242 case WM8904_ANALOGUE_LEFT_INPUT_1
:
243 case WM8904_ANALOGUE_RIGHT_INPUT_1
:
244 case WM8904_ANALOGUE_OUT1_LEFT
:
245 case WM8904_ANALOGUE_OUT1_RIGHT
:
246 case WM8904_ANALOGUE_OUT2_LEFT
:
247 case WM8904_ANALOGUE_OUT2_RIGHT
:
248 case WM8904_ANALOGUE_OUT12_ZC
:
249 case WM8904_DC_SERVO_0
:
250 case WM8904_DC_SERVO_1
:
251 case WM8904_DC_SERVO_2
:
252 case WM8904_DC_SERVO_4
:
253 case WM8904_DC_SERVO_5
:
254 case WM8904_DC_SERVO_6
:
255 case WM8904_DC_SERVO_7
:
256 case WM8904_DC_SERVO_8
:
257 case WM8904_DC_SERVO_9
:
258 case WM8904_DC_SERVO_READBACK_0
:
259 case WM8904_ANALOGUE_HP_0
:
260 case WM8904_ANALOGUE_LINEOUT_0
:
261 case WM8904_CHARGE_PUMP_0
:
262 case WM8904_CLASS_W_0
:
263 case WM8904_WRITE_SEQUENCER_0
:
264 case WM8904_WRITE_SEQUENCER_1
:
265 case WM8904_WRITE_SEQUENCER_2
:
266 case WM8904_WRITE_SEQUENCER_3
:
267 case WM8904_WRITE_SEQUENCER_4
:
268 case WM8904_FLL_CONTROL_1
:
269 case WM8904_FLL_CONTROL_2
:
270 case WM8904_FLL_CONTROL_3
:
271 case WM8904_FLL_CONTROL_4
:
272 case WM8904_FLL_CONTROL_5
:
273 case WM8904_GPIO_CONTROL_1
:
274 case WM8904_GPIO_CONTROL_2
:
275 case WM8904_GPIO_CONTROL_3
:
276 case WM8904_GPIO_CONTROL_4
:
277 case WM8904_DIGITAL_PULLS
:
278 case WM8904_INTERRUPT_STATUS
:
279 case WM8904_INTERRUPT_STATUS_MASK
:
280 case WM8904_INTERRUPT_POLARITY
:
281 case WM8904_INTERRUPT_DEBOUNCE
:
306 case WM8904_CONTROL_INTERFACE_TEST_1
:
307 case WM8904_ADC_TEST_0
:
308 case WM8904_ANALOGUE_OUTPUT_BIAS_0
:
309 case WM8904_FLL_NCO_TEST_0
:
310 case WM8904_FLL_NCO_TEST_1
:
317 static int wm8904_configure_clocking(struct snd_soc_codec
*codec
)
319 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
320 unsigned int clock0
, clock2
, rate
;
322 /* Gate the clock while we're updating to avoid misclocking */
323 clock2
= snd_soc_read(codec
, WM8904_CLOCK_RATES_2
);
324 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
325 WM8904_SYSCLK_SRC
, 0);
327 /* This should be done on init() for bypass paths */
328 switch (wm8904
->sysclk_src
) {
329 case WM8904_CLK_MCLK
:
330 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm8904
->mclk_rate
);
332 clock2
&= ~WM8904_SYSCLK_SRC
;
333 rate
= wm8904
->mclk_rate
;
335 /* Ensure the FLL is stopped */
336 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
337 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
341 dev_dbg(codec
->dev
, "Using %dHz FLL clock\n",
344 clock2
|= WM8904_SYSCLK_SRC
;
345 rate
= wm8904
->fll_fout
;
349 dev_err(codec
->dev
, "System clock not configured\n");
353 /* SYSCLK shouldn't be over 13.5MHz */
354 if (rate
> 13500000) {
355 clock0
= WM8904_MCLK_DIV
;
356 wm8904
->sysclk_rate
= rate
/ 2;
359 wm8904
->sysclk_rate
= rate
;
362 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_0
, WM8904_MCLK_DIV
,
365 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
366 WM8904_CLK_SYS_ENA
| WM8904_SYSCLK_SRC
, clock2
);
368 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm8904
->sysclk_rate
);
373 static void wm8904_set_drc(struct snd_soc_codec
*codec
)
375 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
376 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
379 /* Save any enables; the configuration should clear them. */
380 save
= snd_soc_read(codec
, WM8904_DRC_0
);
382 for (i
= 0; i
< WM8904_DRC_REGS
; i
++)
383 snd_soc_update_bits(codec
, WM8904_DRC_0
+ i
, 0xffff,
384 pdata
->drc_cfgs
[wm8904
->drc_cfg
].regs
[i
]);
386 /* Reenable the DRC */
387 snd_soc_update_bits(codec
, WM8904_DRC_0
,
388 WM8904_DRC_ENA
| WM8904_DRC_DAC_PATH
, save
);
391 static int wm8904_put_drc_enum(struct snd_kcontrol
*kcontrol
,
392 struct snd_ctl_elem_value
*ucontrol
)
394 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
395 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
396 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
397 int value
= ucontrol
->value
.integer
.value
[0];
399 if (value
>= pdata
->num_drc_cfgs
)
402 wm8904
->drc_cfg
= value
;
404 wm8904_set_drc(codec
);
409 static int wm8904_get_drc_enum(struct snd_kcontrol
*kcontrol
,
410 struct snd_ctl_elem_value
*ucontrol
)
412 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
413 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
415 ucontrol
->value
.enumerated
.item
[0] = wm8904
->drc_cfg
;
420 static void wm8904_set_retune_mobile(struct snd_soc_codec
*codec
)
422 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
423 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
424 int best
, best_val
, save
, i
, cfg
;
426 if (!pdata
|| !wm8904
->num_retune_mobile_texts
)
429 /* Find the version of the currently selected configuration
430 * with the nearest sample rate. */
431 cfg
= wm8904
->retune_mobile_cfg
;
434 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
435 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
436 wm8904
->retune_mobile_texts
[cfg
]) == 0 &&
437 abs(pdata
->retune_mobile_cfgs
[i
].rate
438 - wm8904
->fs
) < best_val
) {
440 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
445 dev_dbg(codec
->dev
, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
446 pdata
->retune_mobile_cfgs
[best
].name
,
447 pdata
->retune_mobile_cfgs
[best
].rate
,
450 /* The EQ will be disabled while reconfiguring it, remember the
451 * current configuration.
453 save
= snd_soc_read(codec
, WM8904_EQ1
);
455 for (i
= 0; i
< WM8904_EQ_REGS
; i
++)
456 snd_soc_update_bits(codec
, WM8904_EQ1
+ i
, 0xffff,
457 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
459 snd_soc_update_bits(codec
, WM8904_EQ1
, WM8904_EQ_ENA
, save
);
462 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
463 struct snd_ctl_elem_value
*ucontrol
)
465 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
466 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
467 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
468 int value
= ucontrol
->value
.integer
.value
[0];
470 if (value
>= pdata
->num_retune_mobile_cfgs
)
473 wm8904
->retune_mobile_cfg
= value
;
475 wm8904_set_retune_mobile(codec
);
480 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
481 struct snd_ctl_elem_value
*ucontrol
)
483 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
484 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
486 ucontrol
->value
.enumerated
.item
[0] = wm8904
->retune_mobile_cfg
;
491 static int deemph_settings
[] = { 0, 32000, 44100, 48000 };
493 static int wm8904_set_deemph(struct snd_soc_codec
*codec
)
495 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
498 /* If we're using deemphasis select the nearest available sample
501 if (wm8904
->deemph
) {
503 for (i
= 2; i
< ARRAY_SIZE(deemph_settings
); i
++) {
504 if (abs(deemph_settings
[i
] - wm8904
->fs
) <
505 abs(deemph_settings
[best
] - wm8904
->fs
))
509 val
= best
<< WM8904_DEEMPH_SHIFT
;
514 dev_dbg(codec
->dev
, "Set deemphasis %d\n", val
);
516 return snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
,
517 WM8904_DEEMPH_MASK
, val
);
520 static int wm8904_get_deemph(struct snd_kcontrol
*kcontrol
,
521 struct snd_ctl_elem_value
*ucontrol
)
523 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
524 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
526 ucontrol
->value
.enumerated
.item
[0] = wm8904
->deemph
;
530 static int wm8904_put_deemph(struct snd_kcontrol
*kcontrol
,
531 struct snd_ctl_elem_value
*ucontrol
)
533 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
534 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
535 int deemph
= ucontrol
->value
.enumerated
.item
[0];
540 wm8904
->deemph
= deemph
;
542 return wm8904_set_deemph(codec
);
545 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
546 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
547 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
548 static const DECLARE_TLV_DB_SCALE(sidetone_tlv
, -3600, 300, 0);
549 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
551 static const char *input_mode_text
[] = {
552 "Single-Ended", "Differential Line", "Differential Mic"
555 static const struct soc_enum lin_mode
=
556 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
558 static const struct soc_enum rin_mode
=
559 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
561 static const char *hpf_mode_text
[] = {
562 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
565 static const struct soc_enum hpf_mode
=
566 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
568 static int wm8904_adc_osr_put(struct snd_kcontrol
*kcontrol
,
569 struct snd_ctl_elem_value
*ucontrol
)
571 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
575 ret
= snd_soc_put_volsw(kcontrol
, ucontrol
);
579 if (ucontrol
->value
.integer
.value
[0])
582 val
= WM8904_ADC_128_OSR_TST_MODE
| WM8904_ADC_BIASX1P5
;
584 snd_soc_update_bits(codec
, WM8904_ADC_TEST_0
,
585 WM8904_ADC_128_OSR_TST_MODE
| WM8904_ADC_BIASX1P5
,
591 static const struct snd_kcontrol_new wm8904_adc_snd_controls
[] = {
592 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT
,
593 WM8904_ADC_DIGITAL_VOLUME_RIGHT
, 1, 119, 0, digital_tlv
),
595 SOC_ENUM("Left Caputure Mode", lin_mode
),
596 SOC_ENUM("Right Capture Mode", rin_mode
),
598 /* No TLV since it depends on mode */
599 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0
,
600 WM8904_ANALOGUE_RIGHT_INPUT_0
, 0, 31, 0),
601 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0
,
602 WM8904_ANALOGUE_RIGHT_INPUT_0
, 7, 1, 1),
604 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0
, 4, 1, 0),
605 SOC_ENUM("High Pass Filter Mode", hpf_mode
),
606 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0
, 0, 1, 0,
607 snd_soc_get_volsw
, wm8904_adc_osr_put
),
610 static const char *drc_path_text
[] = {
614 static const struct soc_enum drc_path
=
615 SOC_ENUM_SINGLE(WM8904_DRC_0
, 14, 2, drc_path_text
);
617 static const struct snd_kcontrol_new wm8904_dac_snd_controls
[] = {
618 SOC_SINGLE_TLV("Digital Playback Boost Volume",
619 WM8904_AUDIO_INTERFACE_0
, 9, 3, 0, dac_boost_tlv
),
620 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT
,
621 WM8904_DAC_DIGITAL_VOLUME_RIGHT
, 1, 96, 0, digital_tlv
),
623 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT
,
624 WM8904_ANALOGUE_OUT1_RIGHT
, 0, 63, 0, out_tlv
),
625 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT
,
626 WM8904_ANALOGUE_OUT1_RIGHT
, 8, 1, 1),
627 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT
,
628 WM8904_ANALOGUE_OUT1_RIGHT
, 6, 1, 0),
630 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT
,
631 WM8904_ANALOGUE_OUT2_RIGHT
, 0, 63, 0, out_tlv
),
632 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT
,
633 WM8904_ANALOGUE_OUT2_RIGHT
, 8, 1, 1),
634 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT
,
635 WM8904_ANALOGUE_OUT2_RIGHT
, 6, 1, 0),
637 SOC_SINGLE("EQ Switch", WM8904_EQ1
, 0, 1, 0),
638 SOC_SINGLE("DRC Switch", WM8904_DRC_0
, 15, 1, 0),
639 SOC_ENUM("DRC Path", drc_path
),
640 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1
, 6, 1, 0),
641 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
642 wm8904_get_deemph
, wm8904_put_deemph
),
645 static const struct snd_kcontrol_new wm8904_snd_controls
[] = {
646 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0
, 4, 8, 15, 0,
650 static const struct snd_kcontrol_new wm8904_eq_controls
[] = {
651 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2
, 0, 24, 0, eq_tlv
),
652 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3
, 0, 24, 0, eq_tlv
),
653 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4
, 0, 24, 0, eq_tlv
),
654 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5
, 0, 24, 0, eq_tlv
),
655 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6
, 0, 24, 0, eq_tlv
),
658 static int cp_event(struct snd_soc_dapm_widget
*w
,
659 struct snd_kcontrol
*kcontrol
, int event
)
661 BUG_ON(event
!= SND_SOC_DAPM_POST_PMU
);
663 /* Maximum startup time */
669 static int sysclk_event(struct snd_soc_dapm_widget
*w
,
670 struct snd_kcontrol
*kcontrol
, int event
)
672 struct snd_soc_codec
*codec
= w
->codec
;
673 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
676 case SND_SOC_DAPM_PRE_PMU
:
677 /* If we're using the FLL then we only start it when
678 * required; we assume that the configuration has been
679 * done previously and all we need to do is kick it
682 switch (wm8904
->sysclk_src
) {
684 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
688 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
698 case SND_SOC_DAPM_POST_PMD
:
699 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
700 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
707 static int out_pga_event(struct snd_soc_dapm_widget
*w
,
708 struct snd_kcontrol
*kcontrol
, int event
)
710 struct snd_soc_codec
*codec
= w
->codec
;
711 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
715 int dcs_l_reg
, dcs_r_reg
;
719 /* This code is shared between HP and LINEOUT; we do all our
720 * power management in stereo pairs to avoid latency issues so
721 * we reuse shift to identify which rather than strcmp() the
726 case WM8904_ANALOGUE_HP_0
:
727 pwr_reg
= WM8904_POWER_MANAGEMENT_2
;
728 dcs_mask
= WM8904_DCS_ENA_CHAN_0
| WM8904_DCS_ENA_CHAN_1
;
729 dcs_r_reg
= WM8904_DC_SERVO_8
;
730 dcs_l_reg
= WM8904_DC_SERVO_9
;
734 case WM8904_ANALOGUE_LINEOUT_0
:
735 pwr_reg
= WM8904_POWER_MANAGEMENT_3
;
736 dcs_mask
= WM8904_DCS_ENA_CHAN_2
| WM8904_DCS_ENA_CHAN_3
;
737 dcs_r_reg
= WM8904_DC_SERVO_6
;
738 dcs_l_reg
= WM8904_DC_SERVO_7
;
748 case SND_SOC_DAPM_PRE_PMU
:
749 /* Power on the PGAs */
750 snd_soc_update_bits(codec
, pwr_reg
,
751 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
,
752 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
);
754 /* Power on the amplifier */
755 snd_soc_update_bits(codec
, reg
,
756 WM8904_HPL_ENA
| WM8904_HPR_ENA
,
757 WM8904_HPL_ENA
| WM8904_HPR_ENA
);
760 /* Enable the first stage */
761 snd_soc_update_bits(codec
, reg
,
762 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
,
763 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
);
765 /* Power up the DC servo */
766 snd_soc_update_bits(codec
, WM8904_DC_SERVO_0
,
769 /* Either calibrate the DC servo or restore cached state
772 if (wm8904
->dcs_state
[dcs_l
] || wm8904
->dcs_state
[dcs_r
]) {
773 dev_dbg(codec
->dev
, "Restoring DC servo state\n");
775 snd_soc_write(codec
, dcs_l_reg
,
776 wm8904
->dcs_state
[dcs_l
]);
777 snd_soc_write(codec
, dcs_r_reg
,
778 wm8904
->dcs_state
[dcs_r
]);
780 snd_soc_write(codec
, WM8904_DC_SERVO_1
, dcs_mask
);
784 dev_dbg(codec
->dev
, "Calibrating DC servo\n");
786 snd_soc_write(codec
, WM8904_DC_SERVO_1
,
787 dcs_mask
<< WM8904_DCS_TRIG_STARTUP_0_SHIFT
);
792 /* Wait for DC servo to complete */
793 dcs_mask
<<= WM8904_DCS_CAL_COMPLETE_SHIFT
;
795 val
= snd_soc_read(codec
, WM8904_DC_SERVO_READBACK_0
);
796 if ((val
& dcs_mask
) == dcs_mask
)
802 if ((val
& dcs_mask
) != dcs_mask
)
803 dev_warn(codec
->dev
, "DC servo timed out\n");
805 dev_dbg(codec
->dev
, "DC servo ready\n");
807 /* Enable the output stage */
808 snd_soc_update_bits(codec
, reg
,
809 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
,
810 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
);
813 case SND_SOC_DAPM_POST_PMU
:
814 /* Unshort the output itself */
815 snd_soc_update_bits(codec
, reg
,
816 WM8904_HPL_RMV_SHORT
|
817 WM8904_HPR_RMV_SHORT
,
818 WM8904_HPL_RMV_SHORT
|
819 WM8904_HPR_RMV_SHORT
);
823 case SND_SOC_DAPM_PRE_PMD
:
824 /* Short the output */
825 snd_soc_update_bits(codec
, reg
,
826 WM8904_HPL_RMV_SHORT
|
827 WM8904_HPR_RMV_SHORT
, 0);
830 case SND_SOC_DAPM_POST_PMD
:
831 /* Cache the DC servo configuration; this will be
832 * invalidated if we change the configuration. */
833 wm8904
->dcs_state
[dcs_l
] = snd_soc_read(codec
, dcs_l_reg
);
834 wm8904
->dcs_state
[dcs_r
] = snd_soc_read(codec
, dcs_r_reg
);
836 snd_soc_update_bits(codec
, WM8904_DC_SERVO_0
,
839 /* Disable the amplifier input and output stages */
840 snd_soc_update_bits(codec
, reg
,
841 WM8904_HPL_ENA
| WM8904_HPR_ENA
|
842 WM8904_HPL_ENA_DLY
| WM8904_HPR_ENA_DLY
|
843 WM8904_HPL_ENA_OUTP
| WM8904_HPR_ENA_OUTP
,
847 snd_soc_update_bits(codec
, pwr_reg
,
848 WM8904_HPL_PGA_ENA
| WM8904_HPR_PGA_ENA
,
856 static const char *lin_text
[] = {
857 "IN1L", "IN2L", "IN3L"
860 static const struct soc_enum lin_enum
=
861 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 2, 3, lin_text
);
863 static const struct snd_kcontrol_new lin_mux
=
864 SOC_DAPM_ENUM("Left Capture Mux", lin_enum
);
866 static const struct soc_enum lin_inv_enum
=
867 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1
, 4, 3, lin_text
);
869 static const struct snd_kcontrol_new lin_inv_mux
=
870 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum
);
872 static const char *rin_text
[] = {
873 "IN1R", "IN2R", "IN3R"
876 static const struct soc_enum rin_enum
=
877 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rin_text
);
879 static const struct snd_kcontrol_new rin_mux
=
880 SOC_DAPM_ENUM("Right Capture Mux", rin_enum
);
882 static const struct soc_enum rin_inv_enum
=
883 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rin_text
);
885 static const struct snd_kcontrol_new rin_inv_mux
=
886 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum
);
888 static const char *aif_text
[] = {
892 static const struct soc_enum aifoutl_enum
=
893 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
895 static const struct snd_kcontrol_new aifoutl_mux
=
896 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum
);
898 static const struct soc_enum aifoutr_enum
=
899 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
901 static const struct snd_kcontrol_new aifoutr_mux
=
902 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum
);
904 static const struct soc_enum aifinl_enum
=
905 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
907 static const struct snd_kcontrol_new aifinl_mux
=
908 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum
);
910 static const struct soc_enum aifinr_enum
=
911 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
913 static const struct snd_kcontrol_new aifinr_mux
=
914 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum
);
916 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets
[] = {
917 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2
, 2, 0, sysclk_event
,
918 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
919 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2
, 1, 0, NULL
, 0),
920 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2
, 0, 0, NULL
, 0),
923 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets
[] = {
924 SND_SOC_DAPM_INPUT("IN1L"),
925 SND_SOC_DAPM_INPUT("IN1R"),
926 SND_SOC_DAPM_INPUT("IN2L"),
927 SND_SOC_DAPM_INPUT("IN2R"),
928 SND_SOC_DAPM_INPUT("IN3L"),
929 SND_SOC_DAPM_INPUT("IN3R"),
931 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0
, 0, 0, NULL
, 0),
933 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lin_mux
),
934 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM
, 0, 0,
936 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rin_mux
),
937 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM
, 0, 0,
940 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0
, 1, 0,
942 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0
, 0, 0,
945 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8904_POWER_MANAGEMENT_6
, 1, 0),
946 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8904_POWER_MANAGEMENT_6
, 0, 0),
948 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM
, 0, 0, &aifoutl_mux
),
949 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM
, 0, 0, &aifoutr_mux
),
951 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM
, 0, 0),
952 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM
, 0, 0),
955 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets
[] = {
956 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM
, 0, 0),
957 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM
, 0, 0),
959 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM
, 0, 0, &aifinl_mux
),
960 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM
, 0, 0, &aifinr_mux
),
962 SND_SOC_DAPM_DAC("DACL", NULL
, WM8904_POWER_MANAGEMENT_6
, 3, 0),
963 SND_SOC_DAPM_DAC("DACR", NULL
, WM8904_POWER_MANAGEMENT_6
, 2, 0),
965 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0
, 0, 0, cp_event
,
966 SND_SOC_DAPM_POST_PMU
),
968 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM
, 1, 0, NULL
, 0),
969 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
971 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM
, 1, 0, NULL
, 0),
972 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
974 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM
, WM8904_ANALOGUE_HP_0
,
975 0, NULL
, 0, out_pga_event
,
976 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
977 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
978 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM
, WM8904_ANALOGUE_LINEOUT_0
,
979 0, NULL
, 0, out_pga_event
,
980 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMU
|
981 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMD
),
983 SND_SOC_DAPM_OUTPUT("HPOUTL"),
984 SND_SOC_DAPM_OUTPUT("HPOUTR"),
985 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
986 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
989 static const char *out_mux_text
[] = {
993 static const struct soc_enum hpl_enum
=
994 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 3, 2, out_mux_text
);
996 static const struct snd_kcontrol_new hpl_mux
=
997 SOC_DAPM_ENUM("HPL Mux", hpl_enum
);
999 static const struct soc_enum hpr_enum
=
1000 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 2, 2, out_mux_text
);
1002 static const struct snd_kcontrol_new hpr_mux
=
1003 SOC_DAPM_ENUM("HPR Mux", hpr_enum
);
1005 static const struct soc_enum linel_enum
=
1006 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 1, 2, out_mux_text
);
1008 static const struct snd_kcontrol_new linel_mux
=
1009 SOC_DAPM_ENUM("LINEL Mux", linel_enum
);
1011 static const struct soc_enum liner_enum
=
1012 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC
, 0, 2, out_mux_text
);
1014 static const struct snd_kcontrol_new liner_mux
=
1015 SOC_DAPM_ENUM("LINER Mux", liner_enum
);
1017 static const char *sidetone_text
[] = {
1018 "None", "Left", "Right"
1021 static const struct soc_enum dacl_sidetone_enum
=
1022 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
1024 static const struct snd_kcontrol_new dacl_sidetone_mux
=
1025 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum
);
1027 static const struct soc_enum dacr_sidetone_enum
=
1028 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
1030 static const struct snd_kcontrol_new dacr_sidetone_mux
=
1031 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum
);
1033 static const struct snd_soc_dapm_widget wm8904_dapm_widgets
[] = {
1034 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0
, 0, 1, NULL
, 0),
1035 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1036 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1038 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &dacl_sidetone_mux
),
1039 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &dacr_sidetone_mux
),
1041 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1042 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1043 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM
, 0, 0, &linel_mux
),
1044 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM
, 0, 0, &liner_mux
),
1047 static const struct snd_soc_dapm_route core_intercon
[] = {
1048 { "CLK_DSP", NULL
, "SYSCLK" },
1049 { "TOCLK", NULL
, "SYSCLK" },
1052 static const struct snd_soc_dapm_route adc_intercon
[] = {
1053 { "Left Capture Mux", "IN1L", "IN1L" },
1054 { "Left Capture Mux", "IN2L", "IN2L" },
1055 { "Left Capture Mux", "IN3L", "IN3L" },
1057 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1058 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1059 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1061 { "Right Capture Mux", "IN1R", "IN1R" },
1062 { "Right Capture Mux", "IN2R", "IN2R" },
1063 { "Right Capture Mux", "IN3R", "IN3R" },
1065 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1066 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1067 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1069 { "Left Capture PGA", NULL
, "Left Capture Mux" },
1070 { "Left Capture PGA", NULL
, "Left Capture Inverting Mux" },
1072 { "Right Capture PGA", NULL
, "Right Capture Mux" },
1073 { "Right Capture PGA", NULL
, "Right Capture Inverting Mux" },
1075 { "AIFOUTL", "Left", "ADCL" },
1076 { "AIFOUTL", "Right", "ADCR" },
1077 { "AIFOUTR", "Left", "ADCL" },
1078 { "AIFOUTR", "Right", "ADCR" },
1080 { "ADCL", NULL
, "CLK_DSP" },
1081 { "ADCL", NULL
, "Left Capture PGA" },
1083 { "ADCR", NULL
, "CLK_DSP" },
1084 { "ADCR", NULL
, "Right Capture PGA" },
1087 static const struct snd_soc_dapm_route dac_intercon
[] = {
1088 { "DACL", "Right", "AIFINR" },
1089 { "DACL", "Left", "AIFINL" },
1090 { "DACL", NULL
, "CLK_DSP" },
1092 { "DACR", "Right", "AIFINR" },
1093 { "DACR", "Left", "AIFINL" },
1094 { "DACR", NULL
, "CLK_DSP" },
1096 { "Charge pump", NULL
, "SYSCLK" },
1098 { "Headphone Output", NULL
, "HPL PGA" },
1099 { "Headphone Output", NULL
, "HPR PGA" },
1100 { "Headphone Output", NULL
, "Charge pump" },
1101 { "Headphone Output", NULL
, "TOCLK" },
1103 { "Line Output", NULL
, "LINEL PGA" },
1104 { "Line Output", NULL
, "LINER PGA" },
1105 { "Line Output", NULL
, "Charge pump" },
1106 { "Line Output", NULL
, "TOCLK" },
1108 { "HPOUTL", NULL
, "Headphone Output" },
1109 { "HPOUTR", NULL
, "Headphone Output" },
1111 { "LINEOUTL", NULL
, "Line Output" },
1112 { "LINEOUTR", NULL
, "Line Output" },
1115 static const struct snd_soc_dapm_route wm8904_intercon
[] = {
1116 { "Left Sidetone", "Left", "ADCL" },
1117 { "Left Sidetone", "Right", "ADCR" },
1118 { "DACL", NULL
, "Left Sidetone" },
1120 { "Right Sidetone", "Left", "ADCL" },
1121 { "Right Sidetone", "Right", "ADCR" },
1122 { "DACR", NULL
, "Right Sidetone" },
1124 { "Left Bypass", NULL
, "Class G" },
1125 { "Left Bypass", NULL
, "Left Capture PGA" },
1127 { "Right Bypass", NULL
, "Class G" },
1128 { "Right Bypass", NULL
, "Right Capture PGA" },
1130 { "HPL Mux", "DAC", "DACL" },
1131 { "HPL Mux", "Bypass", "Left Bypass" },
1133 { "HPR Mux", "DAC", "DACR" },
1134 { "HPR Mux", "Bypass", "Right Bypass" },
1136 { "LINEL Mux", "DAC", "DACL" },
1137 { "LINEL Mux", "Bypass", "Left Bypass" },
1139 { "LINER Mux", "DAC", "DACR" },
1140 { "LINER Mux", "Bypass", "Right Bypass" },
1142 { "HPL PGA", NULL
, "HPL Mux" },
1143 { "HPR PGA", NULL
, "HPR Mux" },
1145 { "LINEL PGA", NULL
, "LINEL Mux" },
1146 { "LINER PGA", NULL
, "LINER Mux" },
1149 static const struct snd_soc_dapm_route wm8912_intercon
[] = {
1150 { "HPL PGA", NULL
, "DACL" },
1151 { "HPR PGA", NULL
, "DACR" },
1153 { "LINEL PGA", NULL
, "DACL" },
1154 { "LINER PGA", NULL
, "DACR" },
1157 static int wm8904_add_widgets(struct snd_soc_codec
*codec
)
1159 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1160 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1162 snd_soc_dapm_new_controls(dapm
, wm8904_core_dapm_widgets
,
1163 ARRAY_SIZE(wm8904_core_dapm_widgets
));
1164 snd_soc_dapm_add_routes(dapm
, core_intercon
,
1165 ARRAY_SIZE(core_intercon
));
1167 switch (wm8904
->devtype
) {
1169 snd_soc_add_codec_controls(codec
, wm8904_adc_snd_controls
,
1170 ARRAY_SIZE(wm8904_adc_snd_controls
));
1171 snd_soc_add_codec_controls(codec
, wm8904_dac_snd_controls
,
1172 ARRAY_SIZE(wm8904_dac_snd_controls
));
1173 snd_soc_add_codec_controls(codec
, wm8904_snd_controls
,
1174 ARRAY_SIZE(wm8904_snd_controls
));
1176 snd_soc_dapm_new_controls(dapm
, wm8904_adc_dapm_widgets
,
1177 ARRAY_SIZE(wm8904_adc_dapm_widgets
));
1178 snd_soc_dapm_new_controls(dapm
, wm8904_dac_dapm_widgets
,
1179 ARRAY_SIZE(wm8904_dac_dapm_widgets
));
1180 snd_soc_dapm_new_controls(dapm
, wm8904_dapm_widgets
,
1181 ARRAY_SIZE(wm8904_dapm_widgets
));
1183 snd_soc_dapm_add_routes(dapm
, adc_intercon
,
1184 ARRAY_SIZE(adc_intercon
));
1185 snd_soc_dapm_add_routes(dapm
, dac_intercon
,
1186 ARRAY_SIZE(dac_intercon
));
1187 snd_soc_dapm_add_routes(dapm
, wm8904_intercon
,
1188 ARRAY_SIZE(wm8904_intercon
));
1192 snd_soc_add_codec_controls(codec
, wm8904_dac_snd_controls
,
1193 ARRAY_SIZE(wm8904_dac_snd_controls
));
1195 snd_soc_dapm_new_controls(dapm
, wm8904_dac_dapm_widgets
,
1196 ARRAY_SIZE(wm8904_dac_dapm_widgets
));
1198 snd_soc_dapm_add_routes(dapm
, dac_intercon
,
1199 ARRAY_SIZE(dac_intercon
));
1200 snd_soc_dapm_add_routes(dapm
, wm8912_intercon
,
1201 ARRAY_SIZE(wm8912_intercon
));
1210 unsigned int clk_sys_rate
;
1211 } clk_sys_rates
[] = {
1227 } sample_rates
[] = {
1240 int div
; /* *10 due to .5s */
1266 static int wm8904_hw_params(struct snd_pcm_substream
*substream
,
1267 struct snd_pcm_hw_params
*params
,
1268 struct snd_soc_dai
*dai
)
1270 struct snd_soc_codec
*codec
= dai
->codec
;
1271 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1272 int ret
, i
, best
, best_val
, cur_val
;
1273 unsigned int aif1
= 0;
1274 unsigned int aif2
= 0;
1275 unsigned int aif3
= 0;
1276 unsigned int clock1
= 0;
1277 unsigned int dac_digital1
= 0;
1279 /* What BCLK do we need? */
1280 wm8904
->fs
= params_rate(params
);
1281 if (wm8904
->tdm_slots
) {
1282 dev_dbg(codec
->dev
, "Configuring for %d %d bit TDM slots\n",
1283 wm8904
->tdm_slots
, wm8904
->tdm_width
);
1284 wm8904
->bclk
= snd_soc_calc_bclk(wm8904
->fs
,
1285 wm8904
->tdm_width
, 2,
1288 wm8904
->bclk
= snd_soc_params_to_bclk(params
);
1291 switch (params_format(params
)) {
1292 case SNDRV_PCM_FORMAT_S16_LE
:
1294 case SNDRV_PCM_FORMAT_S20_3LE
:
1297 case SNDRV_PCM_FORMAT_S24_LE
:
1300 case SNDRV_PCM_FORMAT_S32_LE
:
1308 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm8904
->bclk
);
1310 ret
= wm8904_configure_clocking(codec
);
1314 /* Select nearest CLK_SYS_RATE */
1316 best_val
= abs((wm8904
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1318 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1319 cur_val
= abs((wm8904
->sysclk_rate
/
1320 clk_sys_rates
[i
].ratio
) - wm8904
->fs
);
1321 if (cur_val
< best_val
) {
1326 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1327 clk_sys_rates
[best
].ratio
);
1328 clock1
|= (clk_sys_rates
[best
].clk_sys_rate
1329 << WM8904_CLK_SYS_RATE_SHIFT
);
1333 best_val
= abs(wm8904
->fs
- sample_rates
[0].rate
);
1334 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1336 cur_val
= abs(wm8904
->fs
- sample_rates
[i
].rate
);
1337 if (cur_val
< best_val
) {
1342 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1343 sample_rates
[best
].rate
);
1344 clock1
|= (sample_rates
[best
].sample_rate
1345 << WM8904_SAMPLE_RATE_SHIFT
);
1347 /* Enable sloping stopband filter for low sample rates */
1348 if (wm8904
->fs
<= 24000)
1349 dac_digital1
|= WM8904_DAC_SB_FILT
;
1354 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1355 cur_val
= ((wm8904
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1357 if (cur_val
< 0) /* Table is sorted */
1359 if (cur_val
< best_val
) {
1364 wm8904
->bclk
= (wm8904
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1365 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1366 bclk_divs
[best
].div
, wm8904
->bclk
);
1367 aif2
|= bclk_divs
[best
].bclk_div
;
1369 /* LRCLK is a simple fraction of BCLK */
1370 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm8904
->bclk
/ wm8904
->fs
);
1371 aif3
|= wm8904
->bclk
/ wm8904
->fs
;
1373 /* Apply the settings */
1374 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
,
1375 WM8904_DAC_SB_FILT
, dac_digital1
);
1376 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1377 WM8904_AIF_WL_MASK
, aif1
);
1378 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_2
,
1379 WM8904_BCLK_DIV_MASK
, aif2
);
1380 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_3
,
1381 WM8904_LRCLK_RATE_MASK
, aif3
);
1382 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_1
,
1383 WM8904_SAMPLE_RATE_MASK
|
1384 WM8904_CLK_SYS_RATE_MASK
, clock1
);
1386 /* Update filters for the new settings */
1387 wm8904_set_retune_mobile(codec
);
1388 wm8904_set_deemph(codec
);
1394 static int wm8904_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
1395 unsigned int freq
, int dir
)
1397 struct snd_soc_codec
*codec
= dai
->codec
;
1398 struct wm8904_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1401 case WM8904_CLK_MCLK
:
1402 priv
->sysclk_src
= clk_id
;
1403 priv
->mclk_rate
= freq
;
1406 case WM8904_CLK_FLL
:
1407 priv
->sysclk_src
= clk_id
;
1414 dev_dbg(dai
->dev
, "Clock source is %d at %uHz\n", clk_id
, freq
);
1416 wm8904_configure_clocking(codec
);
1421 static int wm8904_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1423 struct snd_soc_codec
*codec
= dai
->codec
;
1424 unsigned int aif1
= 0;
1425 unsigned int aif3
= 0;
1427 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1428 case SND_SOC_DAIFMT_CBS_CFS
:
1430 case SND_SOC_DAIFMT_CBS_CFM
:
1431 aif3
|= WM8904_LRCLK_DIR
;
1433 case SND_SOC_DAIFMT_CBM_CFS
:
1434 aif1
|= WM8904_BCLK_DIR
;
1436 case SND_SOC_DAIFMT_CBM_CFM
:
1437 aif1
|= WM8904_BCLK_DIR
;
1438 aif3
|= WM8904_LRCLK_DIR
;
1444 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1445 case SND_SOC_DAIFMT_DSP_B
:
1446 aif1
|= 0x3 | WM8904_AIF_LRCLK_INV
;
1447 case SND_SOC_DAIFMT_DSP_A
:
1450 case SND_SOC_DAIFMT_I2S
:
1453 case SND_SOC_DAIFMT_RIGHT_J
:
1455 case SND_SOC_DAIFMT_LEFT_J
:
1462 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1463 case SND_SOC_DAIFMT_DSP_A
:
1464 case SND_SOC_DAIFMT_DSP_B
:
1465 /* frame inversion not valid for DSP modes */
1466 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1467 case SND_SOC_DAIFMT_NB_NF
:
1469 case SND_SOC_DAIFMT_IB_NF
:
1470 aif1
|= WM8904_AIF_BCLK_INV
;
1477 case SND_SOC_DAIFMT_I2S
:
1478 case SND_SOC_DAIFMT_RIGHT_J
:
1479 case SND_SOC_DAIFMT_LEFT_J
:
1480 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1481 case SND_SOC_DAIFMT_NB_NF
:
1483 case SND_SOC_DAIFMT_IB_IF
:
1484 aif1
|= WM8904_AIF_BCLK_INV
| WM8904_AIF_LRCLK_INV
;
1486 case SND_SOC_DAIFMT_IB_NF
:
1487 aif1
|= WM8904_AIF_BCLK_INV
;
1489 case SND_SOC_DAIFMT_NB_IF
:
1490 aif1
|= WM8904_AIF_LRCLK_INV
;
1500 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1501 WM8904_AIF_BCLK_INV
| WM8904_AIF_LRCLK_INV
|
1502 WM8904_AIF_FMT_MASK
| WM8904_BCLK_DIR
, aif1
);
1503 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_3
,
1504 WM8904_LRCLK_DIR
, aif3
);
1510 static int wm8904_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
1511 unsigned int rx_mask
, int slots
, int slot_width
)
1513 struct snd_soc_codec
*codec
= dai
->codec
;
1514 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1517 /* Don't need to validate anything if we're turning off TDM */
1521 /* Note that we allow configurations we can't handle ourselves -
1522 * for example, we can generate clocks for slots 2 and up even if
1523 * we can't use those slots ourselves.
1525 aif1
|= WM8904_AIFADC_TDM
| WM8904_AIFDAC_TDM
;
1531 aif1
|= WM8904_AIFADC_TDM_CHAN
;
1542 aif1
|= WM8904_AIFDAC_TDM_CHAN
;
1549 wm8904
->tdm_width
= slot_width
;
1550 wm8904
->tdm_slots
= slots
/ 2;
1552 snd_soc_update_bits(codec
, WM8904_AUDIO_INTERFACE_1
,
1553 WM8904_AIFADC_TDM
| WM8904_AIFADC_TDM_CHAN
|
1554 WM8904_AIFDAC_TDM
| WM8904_AIFDAC_TDM_CHAN
, aif1
);
1562 u16 fll_clk_ref_div
;
1567 /* The size in bits of the FLL divide multiplied by 10
1568 * to allow rounding later */
1569 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1577 { 0, 64000, 4, 16 },
1578 { 64000, 128000, 3, 8 },
1579 { 128000, 256000, 2, 4 },
1580 { 256000, 1000000, 1, 2 },
1581 { 1000000, 13500000, 0, 1 },
1584 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
1588 unsigned int K
, Ndiv
, Nmod
, target
;
1592 /* Fref must be <=13.5MHz */
1594 fll_div
->fll_clk_ref_div
= 0;
1595 while ((Fref
/ div
) > 13500000) {
1597 fll_div
->fll_clk_ref_div
++;
1600 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1606 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
1608 /* Apply the division for our remaining calculations */
1611 /* Fvco should be 90-100MHz; don't check the upper bound */
1613 while (Fout
* div
< 90000000) {
1616 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1621 target
= Fout
* div
;
1622 fll_div
->fll_outdiv
= div
- 1;
1624 pr_debug("Fvco=%dHz\n", target
);
1626 /* Find an appropriate FLL_FRATIO and factor it out of the target */
1627 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1628 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1629 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
1630 target
/= fll_fratios
[i
].ratio
;
1634 if (i
== ARRAY_SIZE(fll_fratios
)) {
1635 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
1639 /* Now, calculate N.K */
1640 Ndiv
= target
/ Fref
;
1643 Nmod
= target
% Fref
;
1644 pr_debug("Nmod=%d\n", Nmod
);
1646 /* Calculate fractional part - scale up so we can round. */
1647 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1649 do_div(Kpart
, Fref
);
1651 K
= Kpart
& 0xFFFFFFFF;
1656 /* Move down to proper range now rounding is done */
1657 fll_div
->k
= K
/ 10;
1659 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1660 fll_div
->n
, fll_div
->k
,
1661 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
1662 fll_div
->fll_clk_ref_div
);
1667 static int wm8904_set_fll(struct snd_soc_dai
*dai
, int fll_id
, int source
,
1668 unsigned int Fref
, unsigned int Fout
)
1670 struct snd_soc_codec
*codec
= dai
->codec
;
1671 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1672 struct _fll_div fll_div
;
1677 if (source
== wm8904
->fll_src
&& Fref
== wm8904
->fll_fref
&&
1678 Fout
== wm8904
->fll_fout
)
1681 clock2
= snd_soc_read(codec
, WM8904_CLOCK_RATES_2
);
1684 dev_dbg(codec
->dev
, "FLL disabled\n");
1686 wm8904
->fll_fref
= 0;
1687 wm8904
->fll_fout
= 0;
1689 /* Gate SYSCLK to avoid glitches */
1690 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1691 WM8904_CLK_SYS_ENA
, 0);
1693 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1694 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
1699 /* Validate the FLL ID */
1701 case WM8904_FLL_MCLK
:
1702 case WM8904_FLL_LRCLK
:
1703 case WM8904_FLL_BCLK
:
1704 ret
= fll_factors(&fll_div
, Fref
, Fout
);
1709 case WM8904_FLL_FREE_RUNNING
:
1710 dev_dbg(codec
->dev
, "Using free running FLL\n");
1711 /* Force 12MHz and output/4 for now */
1715 memset(&fll_div
, 0, sizeof(fll_div
));
1716 fll_div
.fll_outdiv
= 3;
1720 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
1724 /* Save current state then disable the FLL and SYSCLK to avoid
1726 fll1
= snd_soc_read(codec
, WM8904_FLL_CONTROL_1
);
1727 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1728 WM8904_CLK_SYS_ENA
, 0);
1729 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1730 WM8904_FLL_OSC_ENA
| WM8904_FLL_ENA
, 0);
1732 /* Unlock forced oscilator control to switch it on/off */
1733 snd_soc_update_bits(codec
, WM8904_CONTROL_INTERFACE_TEST_1
,
1734 WM8904_USER_KEY
, WM8904_USER_KEY
);
1736 if (fll_id
== WM8904_FLL_FREE_RUNNING
) {
1737 val
= WM8904_FLL_FRC_NCO
;
1742 snd_soc_update_bits(codec
, WM8904_FLL_NCO_TEST_1
, WM8904_FLL_FRC_NCO
,
1744 snd_soc_update_bits(codec
, WM8904_CONTROL_INTERFACE_TEST_1
,
1745 WM8904_USER_KEY
, 0);
1748 case WM8904_FLL_MCLK
:
1749 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1750 WM8904_FLL_CLK_REF_SRC_MASK
, 0);
1753 case WM8904_FLL_LRCLK
:
1754 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1755 WM8904_FLL_CLK_REF_SRC_MASK
, 1);
1758 case WM8904_FLL_BCLK
:
1759 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1760 WM8904_FLL_CLK_REF_SRC_MASK
, 2);
1765 val
= WM8904_FLL_FRACN_ENA
;
1768 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1769 WM8904_FLL_FRACN_ENA
, val
);
1771 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_2
,
1772 WM8904_FLL_OUTDIV_MASK
| WM8904_FLL_FRATIO_MASK
,
1773 (fll_div
.fll_outdiv
<< WM8904_FLL_OUTDIV_SHIFT
) |
1774 (fll_div
.fll_fratio
<< WM8904_FLL_FRATIO_SHIFT
));
1776 snd_soc_write(codec
, WM8904_FLL_CONTROL_3
, fll_div
.k
);
1778 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_4
, WM8904_FLL_N_MASK
,
1779 fll_div
.n
<< WM8904_FLL_N_SHIFT
);
1781 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_5
,
1782 WM8904_FLL_CLK_REF_DIV_MASK
,
1783 fll_div
.fll_clk_ref_div
1784 << WM8904_FLL_CLK_REF_DIV_SHIFT
);
1786 dev_dbg(codec
->dev
, "FLL configured for %dHz->%dHz\n", Fref
, Fout
);
1788 wm8904
->fll_fref
= Fref
;
1789 wm8904
->fll_fout
= Fout
;
1790 wm8904
->fll_src
= source
;
1792 /* Enable the FLL if it was previously active */
1793 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1794 WM8904_FLL_OSC_ENA
, fll1
);
1795 snd_soc_update_bits(codec
, WM8904_FLL_CONTROL_1
,
1796 WM8904_FLL_ENA
, fll1
);
1799 /* Reenable SYSCLK if it was previously active */
1800 snd_soc_update_bits(codec
, WM8904_CLOCK_RATES_2
,
1801 WM8904_CLK_SYS_ENA
, clock2
);
1806 static int wm8904_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1808 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1812 val
= WM8904_DAC_MUTE
;
1816 snd_soc_update_bits(codec
, WM8904_DAC_DIGITAL_1
, WM8904_DAC_MUTE
, val
);
1821 static int wm8904_set_bias_level(struct snd_soc_codec
*codec
,
1822 enum snd_soc_bias_level level
)
1824 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1828 case SND_SOC_BIAS_ON
:
1831 case SND_SOC_BIAS_PREPARE
:
1832 /* VMID resistance 2*50k */
1833 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1834 WM8904_VMID_RES_MASK
,
1835 0x1 << WM8904_VMID_RES_SHIFT
);
1837 /* Normal bias current */
1838 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1839 WM8904_ISEL_MASK
, 2 << WM8904_ISEL_SHIFT
);
1842 case SND_SOC_BIAS_STANDBY
:
1843 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1844 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8904
->supplies
),
1848 "Failed to enable supplies: %d\n",
1853 regcache_cache_only(wm8904
->regmap
, false);
1854 regcache_sync(wm8904
->regmap
);
1857 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1858 WM8904_BIAS_ENA
, WM8904_BIAS_ENA
);
1860 /* Enable VMID, VMID buffering, 2*5k resistance */
1861 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1863 WM8904_VMID_RES_MASK
,
1865 0x3 << WM8904_VMID_RES_SHIFT
);
1871 /* Maintain VMID with 2*250k */
1872 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1873 WM8904_VMID_RES_MASK
,
1874 0x2 << WM8904_VMID_RES_SHIFT
);
1876 /* Bias current *0.5 */
1877 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1878 WM8904_ISEL_MASK
, 0);
1881 case SND_SOC_BIAS_OFF
:
1883 snd_soc_update_bits(codec
, WM8904_VMID_CONTROL_0
,
1884 WM8904_VMID_RES_MASK
| WM8904_VMID_ENA
, 0);
1886 /* Stop bias generation */
1887 snd_soc_update_bits(codec
, WM8904_BIAS_CONTROL_0
,
1888 WM8904_BIAS_ENA
, 0);
1890 regcache_cache_only(wm8904
->regmap
, true);
1891 regcache_mark_dirty(wm8904
->regmap
);
1893 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
),
1897 codec
->dapm
.bias_level
= level
;
1901 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1903 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1904 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1906 static const struct snd_soc_dai_ops wm8904_dai_ops
= {
1907 .set_sysclk
= wm8904_set_sysclk
,
1908 .set_fmt
= wm8904_set_fmt
,
1909 .set_tdm_slot
= wm8904_set_tdm_slot
,
1910 .set_pll
= wm8904_set_fll
,
1911 .hw_params
= wm8904_hw_params
,
1912 .digital_mute
= wm8904_digital_mute
,
1915 static struct snd_soc_dai_driver wm8904_dai
= {
1916 .name
= "wm8904-hifi",
1918 .stream_name
= "Playback",
1921 .rates
= WM8904_RATES
,
1922 .formats
= WM8904_FORMATS
,
1925 .stream_name
= "Capture",
1928 .rates
= WM8904_RATES
,
1929 .formats
= WM8904_FORMATS
,
1931 .ops
= &wm8904_dai_ops
,
1932 .symmetric_rates
= 1,
1935 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec
*codec
)
1937 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1938 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
1939 struct snd_kcontrol_new control
=
1940 SOC_ENUM_EXT("EQ Mode",
1941 wm8904
->retune_mobile_enum
,
1942 wm8904_get_retune_mobile_enum
,
1943 wm8904_put_retune_mobile_enum
);
1947 /* We need an array of texts for the enum API but the number
1948 * of texts is likely to be less than the number of
1949 * configurations due to the sample rate dependency of the
1950 * configurations. */
1951 wm8904
->num_retune_mobile_texts
= 0;
1952 wm8904
->retune_mobile_texts
= NULL
;
1953 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
1954 for (j
= 0; j
< wm8904
->num_retune_mobile_texts
; j
++) {
1955 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
1956 wm8904
->retune_mobile_texts
[j
]) == 0)
1960 if (j
!= wm8904
->num_retune_mobile_texts
)
1963 /* Expand the array... */
1964 t
= krealloc(wm8904
->retune_mobile_texts
,
1966 (wm8904
->num_retune_mobile_texts
+ 1),
1971 /* ...store the new entry... */
1972 t
[wm8904
->num_retune_mobile_texts
] =
1973 pdata
->retune_mobile_cfgs
[i
].name
;
1975 /* ...and remember the new version. */
1976 wm8904
->num_retune_mobile_texts
++;
1977 wm8904
->retune_mobile_texts
= t
;
1980 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
1981 wm8904
->num_retune_mobile_texts
);
1983 wm8904
->retune_mobile_enum
.max
= wm8904
->num_retune_mobile_texts
;
1984 wm8904
->retune_mobile_enum
.texts
= wm8904
->retune_mobile_texts
;
1986 ret
= snd_soc_add_codec_controls(codec
, &control
, 1);
1989 "Failed to add ReTune Mobile control: %d\n", ret
);
1992 static void wm8904_handle_pdata(struct snd_soc_codec
*codec
)
1994 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
1995 struct wm8904_pdata
*pdata
= wm8904
->pdata
;
1999 snd_soc_add_codec_controls(codec
, wm8904_eq_controls
,
2000 ARRAY_SIZE(wm8904_eq_controls
));
2004 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2006 if (pdata
->num_drc_cfgs
) {
2007 struct snd_kcontrol_new control
=
2008 SOC_ENUM_EXT("DRC Mode", wm8904
->drc_enum
,
2009 wm8904_get_drc_enum
, wm8904_put_drc_enum
);
2011 /* We need an array of texts for the enum API */
2012 wm8904
->drc_texts
= kmalloc(sizeof(char *)
2013 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2014 if (!wm8904
->drc_texts
) {
2016 "Failed to allocate %d DRC config texts\n",
2017 pdata
->num_drc_cfgs
);
2021 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2022 wm8904
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2024 wm8904
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2025 wm8904
->drc_enum
.texts
= wm8904
->drc_texts
;
2027 ret
= snd_soc_add_codec_controls(codec
, &control
, 1);
2030 "Failed to add DRC mode control: %d\n", ret
);
2032 wm8904_set_drc(codec
);
2035 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2036 pdata
->num_retune_mobile_cfgs
);
2038 if (pdata
->num_retune_mobile_cfgs
)
2039 wm8904_handle_retune_mobile_pdata(codec
);
2041 snd_soc_add_codec_controls(codec
, wm8904_eq_controls
,
2042 ARRAY_SIZE(wm8904_eq_controls
));
2046 static int wm8904_probe(struct snd_soc_codec
*codec
)
2048 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
2051 codec
->control_data
= wm8904
->regmap
;
2053 switch (wm8904
->devtype
) {
2057 memset(&wm8904_dai
.capture
, 0, sizeof(wm8904_dai
.capture
));
2060 dev_err(codec
->dev
, "Unknown device type %d\n",
2065 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_REGMAP
);
2067 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2071 wm8904_handle_pdata(codec
);
2073 wm8904_add_widgets(codec
);
2078 static int wm8904_remove(struct snd_soc_codec
*codec
)
2080 struct wm8904_priv
*wm8904
= snd_soc_codec_get_drvdata(codec
);
2082 kfree(wm8904
->retune_mobile_texts
);
2083 kfree(wm8904
->drc_texts
);
2088 static struct snd_soc_codec_driver soc_codec_dev_wm8904
= {
2089 .probe
= wm8904_probe
,
2090 .remove
= wm8904_remove
,
2091 .set_bias_level
= wm8904_set_bias_level
,
2092 .idle_bias_off
= true,
2095 static const struct regmap_config wm8904_regmap
= {
2099 .max_register
= WM8904_MAX_REGISTER
,
2100 .volatile_reg
= wm8904_volatile_register
,
2101 .readable_reg
= wm8904_readable_register
,
2103 .cache_type
= REGCACHE_RBTREE
,
2104 .reg_defaults
= wm8904_reg_defaults
,
2105 .num_reg_defaults
= ARRAY_SIZE(wm8904_reg_defaults
),
2108 static int wm8904_i2c_probe(struct i2c_client
*i2c
,
2109 const struct i2c_device_id
*id
)
2111 struct wm8904_priv
*wm8904
;
2115 wm8904
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8904_priv
),
2120 wm8904
->regmap
= devm_regmap_init_i2c(i2c
, &wm8904_regmap
);
2121 if (IS_ERR(wm8904
->regmap
)) {
2122 ret
= PTR_ERR(wm8904
->regmap
);
2123 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2128 wm8904
->devtype
= id
->driver_data
;
2129 i2c_set_clientdata(i2c
, wm8904
);
2130 wm8904
->pdata
= i2c
->dev
.platform_data
;
2132 for (i
= 0; i
< ARRAY_SIZE(wm8904
->supplies
); i
++)
2133 wm8904
->supplies
[i
].supply
= wm8904_supply_names
[i
];
2135 ret
= devm_regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(wm8904
->supplies
),
2138 dev_err(&i2c
->dev
, "Failed to request supplies: %d\n", ret
);
2142 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8904
->supplies
),
2145 dev_err(&i2c
->dev
, "Failed to enable supplies: %d\n", ret
);
2149 ret
= regmap_read(wm8904
->regmap
, WM8904_SW_RESET_AND_ID
, &val
);
2151 dev_err(&i2c
->dev
, "Failed to read ID register: %d\n", ret
);
2154 if (val
!= 0x8904) {
2155 dev_err(&i2c
->dev
, "Device is not a WM8904, ID is %x\n", val
);
2160 ret
= regmap_read(wm8904
->regmap
, WM8904_REVISION
, &val
);
2162 dev_err(&i2c
->dev
, "Failed to read device revision: %d\n",
2166 dev_info(&i2c
->dev
, "revision %c\n", val
+ 'A');
2168 ret
= regmap_write(wm8904
->regmap
, WM8904_SW_RESET_AND_ID
, 0);
2170 dev_err(&i2c
->dev
, "Failed to issue reset: %d\n", ret
);
2174 /* Change some default settings - latch VU and enable ZC */
2175 regmap_update_bits(wm8904
->regmap
, WM8904_ADC_DIGITAL_VOLUME_LEFT
,
2176 WM8904_ADC_VU
, WM8904_ADC_VU
);
2177 regmap_update_bits(wm8904
->regmap
, WM8904_ADC_DIGITAL_VOLUME_RIGHT
,
2178 WM8904_ADC_VU
, WM8904_ADC_VU
);
2179 regmap_update_bits(wm8904
->regmap
, WM8904_DAC_DIGITAL_VOLUME_LEFT
,
2180 WM8904_DAC_VU
, WM8904_DAC_VU
);
2181 regmap_update_bits(wm8904
->regmap
, WM8904_DAC_DIGITAL_VOLUME_RIGHT
,
2182 WM8904_DAC_VU
, WM8904_DAC_VU
);
2183 regmap_update_bits(wm8904
->regmap
, WM8904_ANALOGUE_OUT1_LEFT
,
2184 WM8904_HPOUT_VU
| WM8904_HPOUTLZC
,
2185 WM8904_HPOUT_VU
| WM8904_HPOUTLZC
);
2186 regmap_update_bits(wm8904
->regmap
, WM8904_ANALOGUE_OUT1_RIGHT
,
2187 WM8904_HPOUT_VU
| WM8904_HPOUTRZC
,
2188 WM8904_HPOUT_VU
| WM8904_HPOUTRZC
);
2189 regmap_update_bits(wm8904
->regmap
, WM8904_ANALOGUE_OUT2_LEFT
,
2190 WM8904_LINEOUT_VU
| WM8904_LINEOUTLZC
,
2191 WM8904_LINEOUT_VU
| WM8904_LINEOUTLZC
);
2192 regmap_update_bits(wm8904
->regmap
, WM8904_ANALOGUE_OUT2_RIGHT
,
2193 WM8904_LINEOUT_VU
| WM8904_LINEOUTRZC
,
2194 WM8904_LINEOUT_VU
| WM8904_LINEOUTRZC
);
2195 regmap_update_bits(wm8904
->regmap
, WM8904_CLOCK_RATES_0
,
2198 /* Apply configuration from the platform data. */
2199 if (wm8904
->pdata
) {
2200 for (i
= 0; i
< WM8904_GPIO_REGS
; i
++) {
2201 if (!wm8904
->pdata
->gpio_cfg
[i
])
2204 regmap_update_bits(wm8904
->regmap
,
2205 WM8904_GPIO_CONTROL_1
+ i
,
2207 wm8904
->pdata
->gpio_cfg
[i
]);
2210 /* Zero is the default value for these anyway */
2211 for (i
= 0; i
< WM8904_MIC_REGS
; i
++)
2212 regmap_update_bits(wm8904
->regmap
,
2213 WM8904_MIC_BIAS_CONTROL_0
+ i
,
2215 wm8904
->pdata
->mic_cfg
[i
]);
2218 /* Set Class W by default - this will be managed by the Class
2219 * G widget at runtime where bypass paths are available.
2221 regmap_update_bits(wm8904
->regmap
, WM8904_CLASS_W_0
,
2222 WM8904_CP_DYN_PWR
, WM8904_CP_DYN_PWR
);
2224 /* Use normal bias source */
2225 regmap_update_bits(wm8904
->regmap
, WM8904_BIAS_CONTROL_0
,
2228 /* Can leave the device powered off until we need it */
2229 regcache_cache_only(wm8904
->regmap
, true);
2230 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2232 ret
= snd_soc_register_codec(&i2c
->dev
,
2233 &soc_codec_dev_wm8904
, &wm8904_dai
, 1);
2240 regulator_bulk_disable(ARRAY_SIZE(wm8904
->supplies
), wm8904
->supplies
);
2244 static int wm8904_i2c_remove(struct i2c_client
*client
)
2246 snd_soc_unregister_codec(&client
->dev
);
2250 static const struct i2c_device_id wm8904_i2c_id
[] = {
2251 { "wm8904", WM8904
},
2252 { "wm8912", WM8912
},
2253 { "wm8918", WM8904
}, /* Actually a subset, updates to follow */
2256 MODULE_DEVICE_TABLE(i2c
, wm8904_i2c_id
);
2258 static struct i2c_driver wm8904_i2c_driver
= {
2261 .owner
= THIS_MODULE
,
2263 .probe
= wm8904_i2c_probe
,
2264 .remove
= wm8904_i2c_remove
,
2265 .id_table
= wm8904_i2c_id
,
2268 module_i2c_driver(wm8904_i2c_driver
);
2270 MODULE_DESCRIPTION("ASoC WM8904 driver");
2271 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2272 MODULE_LICENSE("GPL");