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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / sound / soc / omap / omap-mcpdm.c
blob90d2a7cd2563d06170d450b5bb6a9cc8a6615210
1 /*
2 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
3 *
4 * Copyright (C) 2009 - 2011 Texas Instruments
5 *
6 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
7 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
8 * Margarita Olaya <magi.olaya@ti.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
37
38 #include <sound/core.h>
39 #include <sound/pcm.h>
40 #include <sound/pcm_params.h>
41 #include <sound/soc.h>
42 #include <sound/dmaengine_pcm.h>
43
44 #include "omap-mcpdm.h"
45
46 struct mcpdm_link_config {
47 u32 link_mask; /* channel mask for the direction */
48 u32 threshold; /* FIFO threshold */
49 };
50
51 struct omap_mcpdm {
52 struct device *dev;
53 unsigned long phys_base;
54 void __iomem *io_base;
55 int irq;
56
57 struct mutex mutex;
58
59 /* Playback/Capture configuration */
60 struct mcpdm_link_config config[2];
61
62 /* McPDM dn offsets for rx1, and 2 channels */
63 u32 dn_rx_offset;
64
65 /* McPDM needs to be restarted due to runtime reconfiguration */
66 bool restart;
67
68 struct snd_dmaengine_dai_dma_data dma_data[2];
69 };
70
71 /*
72 * Stream DMA parameters
73 */
74
75 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
76 {
77 __raw_writel(val, mcpdm->io_base + reg);
78 }
79
80 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
81 {
82 return __raw_readl(mcpdm->io_base + reg);
83 }
84
85 #ifdef DEBUG
86 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
87 {
88 dev_dbg(mcpdm->dev, "***********************\n");
89 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
90 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
91 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
92 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
93 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
94 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
95 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
96 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
97 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
98 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
99 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
100 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
101 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
102 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
103 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
104 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
105 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
106 omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
107 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
108 omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
109 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
110 omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
111 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
112 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
113 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
114 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
115 dev_dbg(mcpdm->dev, "***********************\n");
116 }
117 #else
118 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
119 #endif
120
121 /*
122 * Enables the transfer through the PDM interface to/from the Phoenix
123 * codec by enabling the corresponding UP or DN channels.
124 */
125 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
126 {
127 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
128 u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
129
130 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
131 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
132
133 ctrl |= link_mask;
134 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
135
136 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
137 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
138 }
139
140 /*
141 * Disables the transfer through the PDM interface to/from the Phoenix
142 * codec by disabling the corresponding UP or DN channels.
143 */
144 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
145 {
146 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
147 u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
148
149 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
150 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
151
152 ctrl &= ~(link_mask);
153 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
154
155 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
156 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
157
158 }
159
160 /*
161 * Is the physical McPDM interface active.
162 */
163 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
164 {
165 return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
166 (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
167 }
168
169 /*
170 * Configures McPDM uplink, and downlink for audio.
171 * This function should be called before omap_mcpdm_start.
172 */
173 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
174 {
175 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
176 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
177 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
178
179 /* Enable DN RX1/2 offset cancellation feature, if configured */
180 if (mcpdm->dn_rx_offset) {
181 u32 dn_offset = mcpdm->dn_rx_offset;
182
183 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
184 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
185 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
186 }
187
188 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
189 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
190 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
191 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
192
193 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
194 MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
195 }
196
197 /*
198 * Cleans McPDM uplink, and downlink configuration.
199 * This function should be called when the stream is closed.
200 */
201 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
202 {
203 /* Disable irq request generation for downlink */
204 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
205 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
206
207 /* Disable DMA request generation for downlink */
208 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
209
210 /* Disable irq request generation for uplink */
211 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
212 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
213
214 /* Disable DMA request generation for uplink */
215 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
216
217 /* Disable RX1/2 offset cancellation */
218 if (mcpdm->dn_rx_offset)
219 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
220 }
221
222 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
223 {
224 struct omap_mcpdm *mcpdm = dev_id;
225 int irq_status;
226
227 irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
228
229 /* Acknowledge irq event */
230 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
231
232 if (irq_status & MCPDM_DN_IRQ_FULL)
233 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
234
235 if (irq_status & MCPDM_DN_IRQ_EMPTY)
236 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
237
238 if (irq_status & MCPDM_DN_IRQ)
239 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
240
241 if (irq_status & MCPDM_UP_IRQ_FULL)
242 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
243
244 if (irq_status & MCPDM_UP_IRQ_EMPTY)
245 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
246
247 if (irq_status & MCPDM_UP_IRQ)
248 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
249
250 return IRQ_HANDLED;
251 }
252
253 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
254 struct snd_soc_dai *dai)
255 {
256 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
257
258 mutex_lock(&mcpdm->mutex);
259
260 if (!dai->active) {
261 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
262
263 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
264 omap_mcpdm_open_streams(mcpdm);
265 }
266 mutex_unlock(&mcpdm->mutex);
267
268 snd_soc_dai_set_dma_data(dai, substream,
269 &mcpdm->dma_data[substream->stream]);
270
271 return 0;
272 }
273
274 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
275 struct snd_soc_dai *dai)
276 {
277 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
278
279 mutex_lock(&mcpdm->mutex);
280
281 if (!dai->active) {
282 if (omap_mcpdm_active(mcpdm)) {
283 omap_mcpdm_stop(mcpdm);
284 omap_mcpdm_close_streams(mcpdm);
285 mcpdm->config[0].link_mask = 0;
286 mcpdm->config[1].link_mask = 0;
287 }
288 }
289
290 mutex_unlock(&mcpdm->mutex);
291 }
292
293 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
294 struct snd_pcm_hw_params *params,
295 struct snd_soc_dai *dai)
296 {
297 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
298 int stream = substream->stream;
299 struct snd_dmaengine_dai_dma_data *dma_data;
300 u32 threshold;
301 int channels;
302 int link_mask = 0;
303
304 channels = params_channels(params);
305 switch (channels) {
306 case 5:
307 if (stream == SNDRV_PCM_STREAM_CAPTURE)
308 /* up to 3 channels for capture */
309 return -EINVAL;
310 link_mask |= 1 << 4;
311 case 4:
312 if (stream == SNDRV_PCM_STREAM_CAPTURE)
313 /* up to 3 channels for capture */
314 return -EINVAL;
315 link_mask |= 1 << 3;
316 case 3:
317 link_mask |= 1 << 2;
318 case 2:
319 link_mask |= 1 << 1;
320 case 1:
321 link_mask |= 1 << 0;
322 break;
323 default:
324 /* unsupported number of channels */
325 return -EINVAL;
326 }
327
328 dma_data = snd_soc_dai_get_dma_data(dai, substream);
329
330 threshold = mcpdm->config[stream].threshold;
331 /* Configure McPDM channels, and DMA packet size */
332 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
333 link_mask <<= 3;
334
335 /* If capture is not running assume a stereo stream to come */
336 if (!mcpdm->config[!stream].link_mask)
337 mcpdm->config[!stream].link_mask = 0x3;
338
339 dma_data->maxburst =
340 (MCPDM_DN_THRES_MAX - threshold) * channels;
341 } else {
342 /* If playback is not running assume a stereo stream to come */
343 if (!mcpdm->config[!stream].link_mask)
344 mcpdm->config[!stream].link_mask = (0x3 << 3);
345
346 dma_data->maxburst = threshold * channels;
347 }
348
349 /* Check if we need to restart McPDM with this stream */
350 if (mcpdm->config[stream].link_mask &&
351 mcpdm->config[stream].link_mask != link_mask)
352 mcpdm->restart = true;
353
354 mcpdm->config[stream].link_mask = link_mask;
355
356 return 0;
357 }
358
359 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
360 struct snd_soc_dai *dai)
361 {
362 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
363
364 if (!omap_mcpdm_active(mcpdm)) {
365 omap_mcpdm_start(mcpdm);
366 omap_mcpdm_reg_dump(mcpdm);
367 } else if (mcpdm->restart) {
368 omap_mcpdm_stop(mcpdm);
369 omap_mcpdm_start(mcpdm);
370 mcpdm->restart = false;
371 omap_mcpdm_reg_dump(mcpdm);
372 }
373
374 return 0;
375 }
376
377 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
378 .startup = omap_mcpdm_dai_startup,
379 .shutdown = omap_mcpdm_dai_shutdown,
380 .hw_params = omap_mcpdm_dai_hw_params,
381 .prepare = omap_mcpdm_prepare,
382 };
383
384 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
385 {
386 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
387 int ret;
388
389 pm_runtime_enable(mcpdm->dev);
390
391 /* Disable lines while request is ongoing */
392 pm_runtime_get_sync(mcpdm->dev);
393 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
394
395 ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
396 0, "McPDM", (void *)mcpdm);
397
398 pm_runtime_put_sync(mcpdm->dev);
399
400 if (ret) {
401 dev_err(mcpdm->dev, "Request for IRQ failed\n");
402 pm_runtime_disable(mcpdm->dev);
403 }
404
405 /* Configure McPDM threshold values */
406 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
407 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
408 MCPDM_UP_THRES_MAX - 3;
409 return ret;
410 }
411
412 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
413 {
414 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
415
416 pm_runtime_disable(mcpdm->dev);
417
418 return 0;
419 }
420
421 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
422 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
423
424 static struct snd_soc_dai_driver omap_mcpdm_dai = {
425 .probe = omap_mcpdm_probe,
426 .remove = omap_mcpdm_remove,
427 .probe_order = SND_SOC_COMP_ORDER_LATE,
428 .remove_order = SND_SOC_COMP_ORDER_EARLY,
429 .playback = {
430 .channels_min = 1,
431 .channels_max = 5,
432 .rates = OMAP_MCPDM_RATES,
433 .formats = OMAP_MCPDM_FORMATS,
434 .sig_bits = 24,
435 },
436 .capture = {
437 .channels_min = 1,
438 .channels_max = 3,
439 .rates = OMAP_MCPDM_RATES,
440 .formats = OMAP_MCPDM_FORMATS,
441 .sig_bits = 24,
442 },
443 .ops = &omap_mcpdm_dai_ops,
444 };
445
446 static const struct snd_soc_component_driver omap_mcpdm_component = {
447 .name = "omap-mcpdm",
448 };
449
450 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
451 u8 rx1, u8 rx2)
452 {
453 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
454
455 mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
456 }
457 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
458
459 static int asoc_mcpdm_probe(struct platform_device *pdev)
460 {
461 struct omap_mcpdm *mcpdm;
462 struct resource *res;
463
464 mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
465 if (!mcpdm)
466 return -ENOMEM;
467
468 platform_set_drvdata(pdev, mcpdm);
469
470 mutex_init(&mcpdm->mutex);
471
472 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
473 if (res == NULL)
474 return -ENOMEM;
475
476 mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
477 mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
478
479 mcpdm->dma_data[0].filter_data = "dn_link";
480 mcpdm->dma_data[1].filter_data = "up_link";
481
482 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
483 mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
484 if (IS_ERR(mcpdm->io_base))
485 return PTR_ERR(mcpdm->io_base);
486
487 mcpdm->irq = platform_get_irq(pdev, 0);
488 if (mcpdm->irq < 0)
489 return mcpdm->irq;
490
491 mcpdm->dev = &pdev->dev;
492
493 return snd_soc_register_component(&pdev->dev, &omap_mcpdm_component,
494 &omap_mcpdm_dai, 1);
495 }
496
497 static int asoc_mcpdm_remove(struct platform_device *pdev)
498 {
499 snd_soc_unregister_component(&pdev->dev);
500 return 0;
501 }
502
503 static const struct of_device_id omap_mcpdm_of_match[] = {
504 { .compatible = "ti,omap4-mcpdm", },
505 { }
506 };
507 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
508
509 static struct platform_driver asoc_mcpdm_driver = {
510 .driver = {
511 .name = "omap-mcpdm",
512 .owner = THIS_MODULE,
513 .of_match_table = omap_mcpdm_of_match,
514 },
515
516 .probe = asoc_mcpdm_probe,
517 .remove = asoc_mcpdm_remove,
518 };
519
520 module_platform_driver(asoc_mcpdm_driver);
521
522 MODULE_ALIAS("platform:omap-mcpdm");
523 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
524 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
525 MODULE_LICENSE("GPL");
Linux with added FPC-III support