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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / sound / soc / pxa / pxa-ssp.c
bloba3119a00d8fac8ef8295ef3593f16a60c2603aab
1 /*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/pxa2xx_ssp.h>
24 #include <linux/of.h>
25 #include <linux/dmaengine.h>
26
27 #include <asm/irq.h>
28
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
36
37 #include <mach/hardware.h>
38
39 #include "../../arm/pxa2xx-pcm.h"
40 #include "pxa-ssp.h"
41
42 /*
43 * SSP audio private data
44 */
45 struct ssp_priv {
46 struct ssp_device *ssp;
47 unsigned int sysclk;
48 int dai_fmt;
49 #ifdef CONFIG_PM
50 uint32_t cr0;
51 uint32_t cr1;
52 uint32_t to;
53 uint32_t psp;
54 #endif
55 };
56
57 static void dump_registers(struct ssp_device *ssp)
58 {
59 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
60 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
61 pxa_ssp_read_reg(ssp, SSTO));
62
63 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
64 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
65 pxa_ssp_read_reg(ssp, SSACD));
66 }
67
68 static void pxa_ssp_enable(struct ssp_device *ssp)
69 {
70 uint32_t sscr0;
71
72 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
73 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
74 }
75
76 static void pxa_ssp_disable(struct ssp_device *ssp)
77 {
78 uint32_t sscr0;
79
80 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
81 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
82 }
83
84 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
85 int out, struct snd_dmaengine_dai_dma_data *dma)
86 {
87 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
88 DMA_SLAVE_BUSWIDTH_2_BYTES;
89 dma->maxburst = 16;
90 dma->addr = ssp->phys_base + SSDR;
91 }
92
93 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
94 struct snd_soc_dai *cpu_dai)
95 {
96 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
97 struct ssp_device *ssp = priv->ssp;
98 struct snd_dmaengine_dai_dma_data *dma;
99 int ret = 0;
100
101 if (!cpu_dai->active) {
102 clk_enable(ssp->clk);
103 pxa_ssp_disable(ssp);
104 }
105
106 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
107 if (!dma)
108 return -ENOMEM;
109
110 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
111 &ssp->drcmr_tx : &ssp->drcmr_rx;
112
113 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
114
115 return ret;
116 }
117
118 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
119 struct snd_soc_dai *cpu_dai)
120 {
121 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
122 struct ssp_device *ssp = priv->ssp;
123
124 if (!cpu_dai->active) {
125 pxa_ssp_disable(ssp);
126 clk_disable(ssp->clk);
127 }
128
129 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
130 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
131 }
132
133 #ifdef CONFIG_PM
134
135 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
136 {
137 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
138 struct ssp_device *ssp = priv->ssp;
139
140 if (!cpu_dai->active)
141 clk_enable(ssp->clk);
142
143 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
144 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
145 priv->to = __raw_readl(ssp->mmio_base + SSTO);
146 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
147
148 pxa_ssp_disable(ssp);
149 clk_disable(ssp->clk);
150 return 0;
151 }
152
153 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
154 {
155 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
156 struct ssp_device *ssp = priv->ssp;
157 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
158
159 clk_enable(ssp->clk);
160
161 __raw_writel(sssr, ssp->mmio_base + SSSR);
162 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
163 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
164 __raw_writel(priv->to, ssp->mmio_base + SSTO);
165 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
166
167 if (cpu_dai->active)
168 pxa_ssp_enable(ssp);
169 else
170 clk_disable(ssp->clk);
171
172 return 0;
173 }
174
175 #else
176 #define pxa_ssp_suspend NULL
177 #define pxa_ssp_resume NULL
178 #endif
179
180 /**
181 * ssp_set_clkdiv - set SSP clock divider
182 * @div: serial clock rate divider
183 */
184 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
185 {
186 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
187
188 if (ssp->type == PXA25x_SSP) {
189 sscr0 &= ~0x0000ff00;
190 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
191 } else {
192 sscr0 &= ~0x000fff00;
193 sscr0 |= (div - 1) << 8; /* 1..4096 */
194 }
195 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
196 }
197
198 /**
199 * pxa_ssp_get_clkdiv - get SSP clock divider
200 */
201 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
202 {
203 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
204 u32 div;
205
206 if (ssp->type == PXA25x_SSP)
207 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
208 else
209 div = ((sscr0 >> 8) & 0xfff) + 1;
210 return div;
211 }
212
213 /*
214 * Set the SSP ports SYSCLK.
215 */
216 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
217 int clk_id, unsigned int freq, int dir)
218 {
219 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
220 struct ssp_device *ssp = priv->ssp;
221 int val;
222
223 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
224 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
225
226 dev_dbg(&ssp->pdev->dev,
227 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
228 cpu_dai->id, clk_id, freq);
229
230 switch (clk_id) {
231 case PXA_SSP_CLK_NET_PLL:
232 sscr0 |= SSCR0_MOD;
233 break;
234 case PXA_SSP_CLK_PLL:
235 /* Internal PLL is fixed */
236 if (ssp->type == PXA25x_SSP)
237 priv->sysclk = 1843200;
238 else
239 priv->sysclk = 13000000;
240 break;
241 case PXA_SSP_CLK_EXT:
242 priv->sysclk = freq;
243 sscr0 |= SSCR0_ECS;
244 break;
245 case PXA_SSP_CLK_NET:
246 priv->sysclk = freq;
247 sscr0 |= SSCR0_NCS | SSCR0_MOD;
248 break;
249 case PXA_SSP_CLK_AUDIO:
250 priv->sysclk = 0;
251 pxa_ssp_set_scr(ssp, 1);
252 sscr0 |= SSCR0_ACS;
253 break;
254 default:
255 return -ENODEV;
256 }
257
258 /* The SSP clock must be disabled when changing SSP clock mode
259 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
260 if (ssp->type != PXA3xx_SSP)
261 clk_disable(ssp->clk);
262 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
263 pxa_ssp_write_reg(ssp, SSCR0, val);
264 if (ssp->type != PXA3xx_SSP)
265 clk_enable(ssp->clk);
266
267 return 0;
268 }
269
270 /*
271 * Set the SSP clock dividers.
272 */
273 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
274 int div_id, int div)
275 {
276 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
277 struct ssp_device *ssp = priv->ssp;
278 int val;
279
280 switch (div_id) {
281 case PXA_SSP_AUDIO_DIV_ACDS:
282 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
283 pxa_ssp_write_reg(ssp, SSACD, val);
284 break;
285 case PXA_SSP_AUDIO_DIV_SCDB:
286 val = pxa_ssp_read_reg(ssp, SSACD);
287 val &= ~SSACD_SCDB;
288 if (ssp->type == PXA3xx_SSP)
289 val &= ~SSACD_SCDX8;
290 switch (div) {
291 case PXA_SSP_CLK_SCDB_1:
292 val |= SSACD_SCDB;
293 break;
294 case PXA_SSP_CLK_SCDB_4:
295 break;
296 case PXA_SSP_CLK_SCDB_8:
297 if (ssp->type == PXA3xx_SSP)
298 val |= SSACD_SCDX8;
299 else
300 return -EINVAL;
301 break;
302 default:
303 return -EINVAL;
304 }
305 pxa_ssp_write_reg(ssp, SSACD, val);
306 break;
307 case PXA_SSP_DIV_SCR:
308 pxa_ssp_set_scr(ssp, div);
309 break;
310 default:
311 return -ENODEV;
312 }
313
314 return 0;
315 }
316
317 /*
318 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
319 */
320 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
321 int source, unsigned int freq_in, unsigned int freq_out)
322 {
323 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
324 struct ssp_device *ssp = priv->ssp;
325 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
326
327 if (ssp->type == PXA3xx_SSP)
328 pxa_ssp_write_reg(ssp, SSACDD, 0);
329
330 switch (freq_out) {
331 case 5622000:
332 break;
333 case 11345000:
334 ssacd |= (0x1 << 4);
335 break;
336 case 12235000:
337 ssacd |= (0x2 << 4);
338 break;
339 case 14857000:
340 ssacd |= (0x3 << 4);
341 break;
342 case 32842000:
343 ssacd |= (0x4 << 4);
344 break;
345 case 48000000:
346 ssacd |= (0x5 << 4);
347 break;
348 case 0:
349 /* Disable */
350 break;
351
352 default:
353 /* PXA3xx has a clock ditherer which can be used to generate
354 * a wider range of frequencies - calculate a value for it.
355 */
356 if (ssp->type == PXA3xx_SSP) {
357 u32 val;
358 u64 tmp = 19968;
359 tmp *= 1000000;
360 do_div(tmp, freq_out);
361 val = tmp;
362
363 val = (val << 16) | 64;
364 pxa_ssp_write_reg(ssp, SSACDD, val);
365
366 ssacd |= (0x6 << 4);
367
368 dev_dbg(&ssp->pdev->dev,
369 "Using SSACDD %x to supply %uHz\n",
370 val, freq_out);
371 break;
372 }
373
374 return -EINVAL;
375 }
376
377 pxa_ssp_write_reg(ssp, SSACD, ssacd);
378
379 return 0;
380 }
381
382 /*
383 * Set the active slots in TDM/Network mode
384 */
385 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
386 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
387 {
388 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
389 struct ssp_device *ssp = priv->ssp;
390 u32 sscr0;
391
392 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
393 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
394
395 /* set slot width */
396 if (slot_width > 16)
397 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
398 else
399 sscr0 |= SSCR0_DataSize(slot_width);
400
401 if (slots > 1) {
402 /* enable network mode */
403 sscr0 |= SSCR0_MOD;
404
405 /* set number of active slots */
406 sscr0 |= SSCR0_SlotsPerFrm(slots);
407
408 /* set active slot mask */
409 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
410 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
411 }
412 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
413
414 return 0;
415 }
416
417 /*
418 * Tristate the SSP DAI lines
419 */
420 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
421 int tristate)
422 {
423 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
424 struct ssp_device *ssp = priv->ssp;
425 u32 sscr1;
426
427 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
428 if (tristate)
429 sscr1 &= ~SSCR1_TTE;
430 else
431 sscr1 |= SSCR1_TTE;
432 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
433
434 return 0;
435 }
436
437 /*
438 * Set up the SSP DAI format.
439 * The SSP Port must be inactive before calling this function as the
440 * physical interface format is changed.
441 */
442 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
443 unsigned int fmt)
444 {
445 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
446 struct ssp_device *ssp = priv->ssp;
447 u32 sscr0, sscr1, sspsp, scfr;
448
449 /* check if we need to change anything at all */
450 if (priv->dai_fmt == fmt)
451 return 0;
452
453 /* we can only change the settings if the port is not in use */
454 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
455 dev_err(&ssp->pdev->dev,
456 "can't change hardware dai format: stream is in use");
457 return -EINVAL;
458 }
459
460 /* reset port settings */
461 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
462 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
463 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
464 sspsp = 0;
465
466 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
467 case SND_SOC_DAIFMT_CBM_CFM:
468 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
469 break;
470 case SND_SOC_DAIFMT_CBM_CFS:
471 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
472 break;
473 case SND_SOC_DAIFMT_CBS_CFS:
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
480 case SND_SOC_DAIFMT_NB_NF:
481 sspsp |= SSPSP_SFRMP;
482 break;
483 case SND_SOC_DAIFMT_NB_IF:
484 break;
485 case SND_SOC_DAIFMT_IB_IF:
486 sspsp |= SSPSP_SCMODE(2);
487 break;
488 case SND_SOC_DAIFMT_IB_NF:
489 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
496 case SND_SOC_DAIFMT_I2S:
497 sscr0 |= SSCR0_PSP;
498 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
499 /* See hw_params() */
500 break;
501
502 case SND_SOC_DAIFMT_DSP_A:
503 sspsp |= SSPSP_FSRT;
504 case SND_SOC_DAIFMT_DSP_B:
505 sscr0 |= SSCR0_MOD | SSCR0_PSP;
506 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
507 break;
508
509 default:
510 return -EINVAL;
511 }
512
513 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
514 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
515 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
516
517 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
518 case SND_SOC_DAIFMT_CBM_CFM:
519 case SND_SOC_DAIFMT_CBM_CFS:
520 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
521 pxa_ssp_write_reg(ssp, SSCR1, scfr);
522
523 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
524 cpu_relax();
525 break;
526 }
527
528 dump_registers(ssp);
529
530 /* Since we are configuring the timings for the format by hand
531 * we have to defer some things until hw_params() where we
532 * know parameters like the sample size.
533 */
534 priv->dai_fmt = fmt;
535
536 return 0;
537 }
538
539 /*
540 * Set the SSP audio DMA parameters and sample size.
541 * Can be called multiple times by oss emulation.
542 */
543 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
544 struct snd_pcm_hw_params *params,
545 struct snd_soc_dai *cpu_dai)
546 {
547 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
548 struct ssp_device *ssp = priv->ssp;
549 int chn = params_channels(params);
550 u32 sscr0;
551 u32 sspsp;
552 int width = snd_pcm_format_physical_width(params_format(params));
553 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
554 struct snd_dmaengine_dai_dma_data *dma_data;
555
556 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
557
558 /* Network mode with one active slot (ttsa == 1) can be used
559 * to force 16-bit frame width on the wire (for S16_LE), even
560 * with two channels. Use 16-bit DMA transfers for this case.
561 */
562 pxa_ssp_set_dma_params(ssp,
563 ((chn == 2) && (ttsa != 1)) || (width == 32),
564 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
565
566 /* we can only change the settings if the port is not in use */
567 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
568 return 0;
569
570 /* clear selected SSP bits */
571 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
572
573 /* bit size */
574 switch (params_format(params)) {
575 case SNDRV_PCM_FORMAT_S16_LE:
576 if (ssp->type == PXA3xx_SSP)
577 sscr0 |= SSCR0_FPCKE;
578 sscr0 |= SSCR0_DataSize(16);
579 break;
580 case SNDRV_PCM_FORMAT_S24_LE:
581 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
582 break;
583 case SNDRV_PCM_FORMAT_S32_LE:
584 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
585 break;
586 }
587 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
588
589 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
590 case SND_SOC_DAIFMT_I2S:
591 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
592
593 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
594 /* This is a special case where the bitclk is 64fs
595 * and we're not dealing with 2*32 bits of audio
596 * samples.
597 *
598 * The SSP values used for that are all found out by
599 * trying and failing a lot; some of the registers
600 * needed for that mode are only available on PXA3xx.
601 */
602 if (ssp->type != PXA3xx_SSP)
603 return -EINVAL;
604
605 sspsp |= SSPSP_SFRMWDTH(width * 2);
606 sspsp |= SSPSP_SFRMDLY(width * 4);
607 sspsp |= SSPSP_EDMYSTOP(3);
608 sspsp |= SSPSP_DMYSTOP(3);
609 sspsp |= SSPSP_DMYSTRT(1);
610 } else {
611 /* The frame width is the width the LRCLK is
612 * asserted for; the delay is expressed in
613 * half cycle units. We need the extra cycle
614 * because the data starts clocking out one BCLK
615 * after LRCLK changes polarity.
616 */
617 sspsp |= SSPSP_SFRMWDTH(width + 1);
618 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
619 sspsp |= SSPSP_DMYSTRT(1);
620 }
621
622 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
623 break;
624 default:
625 break;
626 }
627
628 /* When we use a network mode, we always require TDM slots
629 * - complain loudly and fail if they've not been set up yet.
630 */
631 if ((sscr0 & SSCR0_MOD) && !ttsa) {
632 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
633 return -EINVAL;
634 }
635
636 dump_registers(ssp);
637
638 return 0;
639 }
640
641 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
642 struct ssp_device *ssp, int value)
643 {
644 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
645 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
646 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
647 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
648
649 if (value && (sscr0 & SSCR0_SSE))
650 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
651
652 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
653 if (value)
654 sscr1 |= SSCR1_TSRE;
655 else
656 sscr1 &= ~SSCR1_TSRE;
657 } else {
658 if (value)
659 sscr1 |= SSCR1_RSRE;
660 else
661 sscr1 &= ~SSCR1_RSRE;
662 }
663
664 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
665
666 if (value) {
667 pxa_ssp_write_reg(ssp, SSSR, sssr);
668 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
669 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
670 }
671 }
672
673 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
674 struct snd_soc_dai *cpu_dai)
675 {
676 int ret = 0;
677 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
678 struct ssp_device *ssp = priv->ssp;
679 int val;
680
681 switch (cmd) {
682 case SNDRV_PCM_TRIGGER_RESUME:
683 pxa_ssp_enable(ssp);
684 break;
685 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
686 pxa_ssp_set_running_bit(substream, ssp, 1);
687 val = pxa_ssp_read_reg(ssp, SSSR);
688 pxa_ssp_write_reg(ssp, SSSR, val);
689 break;
690 case SNDRV_PCM_TRIGGER_START:
691 pxa_ssp_set_running_bit(substream, ssp, 1);
692 break;
693 case SNDRV_PCM_TRIGGER_STOP:
694 pxa_ssp_set_running_bit(substream, ssp, 0);
695 break;
696 case SNDRV_PCM_TRIGGER_SUSPEND:
697 pxa_ssp_disable(ssp);
698 break;
699 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
700 pxa_ssp_set_running_bit(substream, ssp, 0);
701 break;
702
703 default:
704 ret = -EINVAL;
705 }
706
707 dump_registers(ssp);
708
709 return ret;
710 }
711
712 static int pxa_ssp_probe(struct snd_soc_dai *dai)
713 {
714 struct device *dev = dai->dev;
715 struct ssp_priv *priv;
716 int ret;
717
718 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
719 if (!priv)
720 return -ENOMEM;
721
722 if (dev->of_node) {
723 struct device_node *ssp_handle;
724
725 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
726 if (!ssp_handle) {
727 dev_err(dev, "unable to get 'port' phandle\n");
728 return -ENODEV;
729 }
730
731 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
732 if (priv->ssp == NULL) {
733 ret = -ENODEV;
734 goto err_priv;
735 }
736 } else {
737 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
738 if (priv->ssp == NULL) {
739 ret = -ENODEV;
740 goto err_priv;
741 }
742 }
743
744 priv->dai_fmt = (unsigned int) -1;
745 snd_soc_dai_set_drvdata(dai, priv);
746
747 return 0;
748
749 err_priv:
750 kfree(priv);
751 return ret;
752 }
753
754 static int pxa_ssp_remove(struct snd_soc_dai *dai)
755 {
756 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
757
758 pxa_ssp_free(priv->ssp);
759 kfree(priv);
760 return 0;
761 }
762
763 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
764 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
765 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
766 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
767 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
768
769 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
770 SNDRV_PCM_FMTBIT_S24_LE | \
771 SNDRV_PCM_FMTBIT_S32_LE)
772
773 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
774 .startup = pxa_ssp_startup,
775 .shutdown = pxa_ssp_shutdown,
776 .trigger = pxa_ssp_trigger,
777 .hw_params = pxa_ssp_hw_params,
778 .set_sysclk = pxa_ssp_set_dai_sysclk,
779 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
780 .set_pll = pxa_ssp_set_dai_pll,
781 .set_fmt = pxa_ssp_set_dai_fmt,
782 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
783 .set_tristate = pxa_ssp_set_dai_tristate,
784 };
785
786 static struct snd_soc_dai_driver pxa_ssp_dai = {
787 .probe = pxa_ssp_probe,
788 .remove = pxa_ssp_remove,
789 .suspend = pxa_ssp_suspend,
790 .resume = pxa_ssp_resume,
791 .playback = {
792 .channels_min = 1,
793 .channels_max = 8,
794 .rates = PXA_SSP_RATES,
795 .formats = PXA_SSP_FORMATS,
796 },
797 .capture = {
798 .channels_min = 1,
799 .channels_max = 8,
800 .rates = PXA_SSP_RATES,
801 .formats = PXA_SSP_FORMATS,
802 },
803 .ops = &pxa_ssp_dai_ops,
804 };
805
806 static const struct snd_soc_component_driver pxa_ssp_component = {
807 .name = "pxa-ssp",
808 };
809
810 #ifdef CONFIG_OF
811 static const struct of_device_id pxa_ssp_of_ids[] = {
812 { .compatible = "mrvl,pxa-ssp-dai" },
813 };
814 #endif
815
816 static int asoc_ssp_probe(struct platform_device *pdev)
817 {
818 return snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
819 &pxa_ssp_dai, 1);
820 }
821
822 static int asoc_ssp_remove(struct platform_device *pdev)
823 {
824 snd_soc_unregister_component(&pdev->dev);
825 return 0;
826 }
827
828 static struct platform_driver asoc_ssp_driver = {
829 .driver = {
830 .name = "pxa-ssp-dai",
831 .owner = THIS_MODULE,
832 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
833 },
834
835 .probe = asoc_ssp_probe,
836 .remove = asoc_ssp_remove,
837 };
838
839 module_platform_driver(asoc_ssp_driver);
840
841 /* Module information */
842 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
843 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
844 MODULE_LICENSE("GPL");
Linux with added FPC-III support