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net/mlx5: Fix driver load bad flow when having fw initializing timeout
[linux/fpc-iii.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
blob4ee7ea775a023bb39d5a43adaa584a2165f702c0
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "fs_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
57 #include "eswitch.h"
58 #endif
59
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION);
64
65 unsigned int mlx5_core_debug_mask;
66 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
67 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
68
69 #define MLX5_DEFAULT_PROF 2
70 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
71 module_param_named(prof_sel, prof_sel, uint, 0444);
72 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
73
74 enum {
75 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
76 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
77 };
78
79 static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
90 .log_max_qp = 18,
91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
155 },
156 };
157
158 #define FW_INIT_TIMEOUT_MILI 2000
159 #define FW_INIT_WAIT_MS 2
160
161 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
162 {
163 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
164 int err = 0;
165
166 while (fw_initializing(dev)) {
167 if (time_after(jiffies, end)) {
168 err = -EBUSY;
169 break;
170 }
171 msleep(FW_INIT_WAIT_MS);
172 }
173
174 return err;
175 }
176
177 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
178 {
179 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
180 driver_version);
181 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
182 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
183 int remaining_size = driver_ver_sz;
184 char *string;
185
186 if (!MLX5_CAP_GEN(dev, driver_version))
187 return;
188
189 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
190
191 strncpy(string, "Linux", remaining_size);
192
193 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
194 strncat(string, ",", remaining_size);
195
196 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
197 strncat(string, DRIVER_NAME, remaining_size);
198
199 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
200 strncat(string, ",", remaining_size);
201
202 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
203 strncat(string, DRIVER_VERSION, remaining_size);
204
205 /*Send the command*/
206 MLX5_SET(set_driver_version_in, in, opcode,
207 MLX5_CMD_OP_SET_DRIVER_VERSION);
208
209 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
210 }
211
212 static int set_dma_caps(struct pci_dev *pdev)
213 {
214 int err;
215
216 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
217 if (err) {
218 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
219 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
220 if (err) {
221 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
222 return err;
223 }
224 }
225
226 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
227 if (err) {
228 dev_warn(&pdev->dev,
229 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
230 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
231 if (err) {
232 dev_err(&pdev->dev,
233 "Can't set consistent PCI DMA mask, aborting\n");
234 return err;
235 }
236 }
237
238 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
239 return err;
240 }
241
242 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
243 {
244 struct pci_dev *pdev = dev->pdev;
245 int err = 0;
246
247 mutex_lock(&dev->pci_status_mutex);
248 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
249 err = pci_enable_device(pdev);
250 if (!err)
251 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
252 }
253 mutex_unlock(&dev->pci_status_mutex);
254
255 return err;
256 }
257
258 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
259 {
260 struct pci_dev *pdev = dev->pdev;
261
262 mutex_lock(&dev->pci_status_mutex);
263 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
264 pci_disable_device(pdev);
265 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
266 }
267 mutex_unlock(&dev->pci_status_mutex);
268 }
269
270 static int request_bar(struct pci_dev *pdev)
271 {
272 int err = 0;
273
274 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
275 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
276 return -ENODEV;
277 }
278
279 err = pci_request_regions(pdev, DRIVER_NAME);
280 if (err)
281 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
282
283 return err;
284 }
285
286 static void release_bar(struct pci_dev *pdev)
287 {
288 pci_release_regions(pdev);
289 }
290
291 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
292 {
293 struct mlx5_priv *priv = &dev->priv;
294 struct mlx5_eq_table *table = &priv->eq_table;
295 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
296 int nvec;
297 int i;
298
299 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
300 MLX5_EQ_VEC_COMP_BASE;
301 nvec = min_t(int, nvec, num_eqs);
302 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
303 return -ENOMEM;
304
305 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
306
307 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
308 if (!priv->msix_arr || !priv->irq_info)
309 goto err_free_msix;
310
311 for (i = 0; i < nvec; i++)
312 priv->msix_arr[i].entry = i;
313
314 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
315 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
316 if (nvec < 0)
317 return nvec;
318
319 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
320
321 return 0;
322
323 err_free_msix:
324 kfree(priv->irq_info);
325 kfree(priv->msix_arr);
326 return -ENOMEM;
327 }
328
329 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
330 {
331 struct mlx5_priv *priv = &dev->priv;
332
333 pci_disable_msix(dev->pdev);
334 kfree(priv->irq_info);
335 kfree(priv->msix_arr);
336 }
337
338 struct mlx5_reg_host_endianess {
339 u8 he;
340 u8 rsvd[15];
341 };
342
343
344 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
345
346 enum {
347 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
348 MLX5_DEV_CAP_FLAG_DCT,
349 };
350
351 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
352 {
353 switch (size) {
354 case 128:
355 return 0;
356 case 256:
357 return 1;
358 case 512:
359 return 2;
360 case 1024:
361 return 3;
362 case 2048:
363 return 4;
364 case 4096:
365 return 5;
366 default:
367 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
368 return 0;
369 }
370 }
371
372 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
373 enum mlx5_cap_type cap_type,
374 enum mlx5_cap_mode cap_mode)
375 {
376 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
377 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
378 void *out, *hca_caps;
379 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
380 int err;
381
382 memset(in, 0, sizeof(in));
383 out = kzalloc(out_sz, GFP_KERNEL);
384 if (!out)
385 return -ENOMEM;
386
387 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
388 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
389 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
390 if (err) {
391 mlx5_core_warn(dev,
392 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
393 cap_type, cap_mode, err);
394 goto query_ex;
395 }
396
397 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
398
399 switch (cap_mode) {
400 case HCA_CAP_OPMOD_GET_MAX:
401 memcpy(dev->hca_caps_max[cap_type], hca_caps,
402 MLX5_UN_SZ_BYTES(hca_cap_union));
403 break;
404 case HCA_CAP_OPMOD_GET_CUR:
405 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
406 MLX5_UN_SZ_BYTES(hca_cap_union));
407 break;
408 default:
409 mlx5_core_warn(dev,
410 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
411 cap_type, cap_mode);
412 err = -EINVAL;
413 break;
414 }
415 query_ex:
416 kfree(out);
417 return err;
418 }
419
420 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
421 {
422 int ret;
423
424 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
425 if (ret)
426 return ret;
427 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
428 }
429
430 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
431 {
432 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
433
434 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
435 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
436 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
437 }
438
439 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
440 {
441 void *set_ctx;
442 void *set_hca_cap;
443 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
444 int req_endianness;
445 int err;
446
447 if (MLX5_CAP_GEN(dev, atomic)) {
448 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
449 if (err)
450 return err;
451 } else {
452 return 0;
453 }
454
455 req_endianness =
456 MLX5_CAP_ATOMIC(dev,
457 supported_atomic_req_8B_endianess_mode_1);
458
459 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
460 return 0;
461
462 set_ctx = kzalloc(set_sz, GFP_KERNEL);
463 if (!set_ctx)
464 return -ENOMEM;
465
466 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
467
468 /* Set requestor to host endianness */
469 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
470 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
471
472 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
473
474 kfree(set_ctx);
475 return err;
476 }
477
478 static int handle_hca_cap(struct mlx5_core_dev *dev)
479 {
480 void *set_ctx = NULL;
481 struct mlx5_profile *prof = dev->profile;
482 int err = -ENOMEM;
483 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
484 void *set_hca_cap;
485
486 set_ctx = kzalloc(set_sz, GFP_KERNEL);
487 if (!set_ctx)
488 goto query_ex;
489
490 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
491 if (err)
492 goto query_ex;
493
494 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
495 capability);
496 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
497 MLX5_ST_SZ_BYTES(cmd_hca_cap));
498
499 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
500 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
501 128);
502 /* we limit the size of the pkey table to 128 entries for now */
503 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
504 to_fw_pkey_sz(dev, 128));
505
506 /* Check log_max_qp from HCA caps to set in current profile */
507 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
508 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
509 profile[prof_sel].log_max_qp,
510 MLX5_CAP_GEN_MAX(dev, log_max_qp));
511 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
512 }
513 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
514 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
515 prof->log_max_qp);
516
517 /* disable cmdif checksum */
518 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
519
520 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
521
522 err = set_caps(dev, set_ctx, set_sz,
523 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
524
525 query_ex:
526 kfree(set_ctx);
527 return err;
528 }
529
530 static int set_hca_ctrl(struct mlx5_core_dev *dev)
531 {
532 struct mlx5_reg_host_endianess he_in;
533 struct mlx5_reg_host_endianess he_out;
534 int err;
535
536 if (!mlx5_core_is_pf(dev))
537 return 0;
538
539 memset(&he_in, 0, sizeof(he_in));
540 he_in.he = MLX5_SET_HOST_ENDIANNESS;
541 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
542 &he_out, sizeof(he_out),
543 MLX5_REG_HOST_ENDIANNESS, 0, 1);
544 return err;
545 }
546
547 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
548 {
549 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
550 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
551
552 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
553 MLX5_SET(enable_hca_in, in, function_id, func_id);
554 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
555 }
556
557 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
558 {
559 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
560 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
561
562 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
563 MLX5_SET(disable_hca_in, in, function_id, func_id);
564 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
565 }
566
567 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
568 {
569 u32 timer_h, timer_h1, timer_l;
570
571 timer_h = ioread32be(&dev->iseg->internal_timer_h);
572 timer_l = ioread32be(&dev->iseg->internal_timer_l);
573 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
574 if (timer_h != timer_h1) /* wrap around */
575 timer_l = ioread32be(&dev->iseg->internal_timer_l);
576
577 return (u64)timer_l | (u64)timer_h1 << 32;
578 }
579
580 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
581 {
582 struct mlx5_priv *priv = &mdev->priv;
583 struct msix_entry *msix = priv->msix_arr;
584 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
585 int err;
586
587 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
588 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
589 return -ENOMEM;
590 }
591
592 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
593 priv->irq_info[i].mask);
594
595 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
596 if (err) {
597 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
598 irq);
599 goto err_clear_mask;
600 }
601
602 return 0;
603
604 err_clear_mask:
605 free_cpumask_var(priv->irq_info[i].mask);
606 return err;
607 }
608
609 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
610 {
611 struct mlx5_priv *priv = &mdev->priv;
612 struct msix_entry *msix = priv->msix_arr;
613 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
614
615 irq_set_affinity_hint(irq, NULL);
616 free_cpumask_var(priv->irq_info[i].mask);
617 }
618
619 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
620 {
621 int err;
622 int i;
623
624 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
625 err = mlx5_irq_set_affinity_hint(mdev, i);
626 if (err)
627 goto err_out;
628 }
629
630 return 0;
631
632 err_out:
633 for (i--; i >= 0; i--)
634 mlx5_irq_clear_affinity_hint(mdev, i);
635
636 return err;
637 }
638
639 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
640 {
641 int i;
642
643 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
644 mlx5_irq_clear_affinity_hint(mdev, i);
645 }
646
647 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
648 unsigned int *irqn)
649 {
650 struct mlx5_eq_table *table = &dev->priv.eq_table;
651 struct mlx5_eq *eq, *n;
652 int err = -ENOENT;
653
654 spin_lock(&table->lock);
655 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
656 if (eq->index == vector) {
657 *eqn = eq->eqn;
658 *irqn = eq->irqn;
659 err = 0;
660 break;
661 }
662 }
663 spin_unlock(&table->lock);
664
665 return err;
666 }
667 EXPORT_SYMBOL(mlx5_vector2eqn);
668
669 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
670 {
671 struct mlx5_eq_table *table = &dev->priv.eq_table;
672 struct mlx5_eq *eq;
673
674 spin_lock(&table->lock);
675 list_for_each_entry(eq, &table->comp_eqs_list, list)
676 if (eq->eqn == eqn) {
677 spin_unlock(&table->lock);
678 return eq;
679 }
680
681 spin_unlock(&table->lock);
682
683 return ERR_PTR(-ENOENT);
684 }
685
686 static void free_comp_eqs(struct mlx5_core_dev *dev)
687 {
688 struct mlx5_eq_table *table = &dev->priv.eq_table;
689 struct mlx5_eq *eq, *n;
690
691 #ifdef CONFIG_RFS_ACCEL
692 if (dev->rmap) {
693 free_irq_cpu_rmap(dev->rmap);
694 dev->rmap = NULL;
695 }
696 #endif
697 spin_lock(&table->lock);
698 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
699 list_del(&eq->list);
700 spin_unlock(&table->lock);
701 if (mlx5_destroy_unmap_eq(dev, eq))
702 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
703 eq->eqn);
704 kfree(eq);
705 spin_lock(&table->lock);
706 }
707 spin_unlock(&table->lock);
708 }
709
710 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
711 {
712 struct mlx5_eq_table *table = &dev->priv.eq_table;
713 char name[MLX5_MAX_IRQ_NAME];
714 struct mlx5_eq *eq;
715 int ncomp_vec;
716 int nent;
717 int err;
718 int i;
719
720 INIT_LIST_HEAD(&table->comp_eqs_list);
721 ncomp_vec = table->num_comp_vectors;
722 nent = MLX5_COMP_EQ_SIZE;
723 #ifdef CONFIG_RFS_ACCEL
724 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
725 if (!dev->rmap)
726 return -ENOMEM;
727 #endif
728 for (i = 0; i < ncomp_vec; i++) {
729 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
730 if (!eq) {
731 err = -ENOMEM;
732 goto clean;
733 }
734
735 #ifdef CONFIG_RFS_ACCEL
736 irq_cpu_rmap_add(dev->rmap,
737 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
738 #endif
739 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
740 err = mlx5_create_map_eq(dev, eq,
741 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
742 name, &dev->priv.uuari.uars[0]);
743 if (err) {
744 kfree(eq);
745 goto clean;
746 }
747 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
748 eq->index = i;
749 spin_lock(&table->lock);
750 list_add_tail(&eq->list, &table->comp_eqs_list);
751 spin_unlock(&table->lock);
752 }
753
754 return 0;
755
756 clean:
757 free_comp_eqs(dev);
758 return err;
759 }
760
761 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
762 {
763 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
764 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
765 u32 sup_issi;
766 int err;
767
768 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
769 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
770 query_out, sizeof(query_out));
771 if (err) {
772 u32 syndrome;
773 u8 status;
774
775 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
776 if (!status || syndrome == MLX5_DRIVER_SYND) {
777 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
778 err, status, syndrome);
779 return err;
780 }
781
782 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
783 dev->issi = 0;
784 return 0;
785 }
786
787 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
788
789 if (sup_issi & (1 << 1)) {
790 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
791 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
792
793 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
794 MLX5_SET(set_issi_in, set_in, current_issi, 1);
795 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
796 set_out, sizeof(set_out));
797 if (err) {
798 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
799 err);
800 return err;
801 }
802
803 dev->issi = 1;
804
805 return 0;
806 } else if (sup_issi & (1 << 0) || !sup_issi) {
807 return 0;
808 }
809
810 return -EOPNOTSUPP;
811 }
812
813
814 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
815 {
816 struct pci_dev *pdev = dev->pdev;
817 int err = 0;
818
819 pci_set_drvdata(dev->pdev, dev);
820 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
821 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
822
823 mutex_init(&priv->pgdir_mutex);
824 INIT_LIST_HEAD(&priv->pgdir_list);
825 spin_lock_init(&priv->mkey_lock);
826
827 mutex_init(&priv->alloc_mutex);
828
829 priv->numa_node = dev_to_node(&dev->pdev->dev);
830
831 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
832 if (!priv->dbg_root)
833 return -ENOMEM;
834
835 err = mlx5_pci_enable_device(dev);
836 if (err) {
837 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
838 goto err_dbg;
839 }
840
841 err = request_bar(pdev);
842 if (err) {
843 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
844 goto err_disable;
845 }
846
847 pci_set_master(pdev);
848
849 err = set_dma_caps(pdev);
850 if (err) {
851 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
852 goto err_clr_master;
853 }
854
855 dev->iseg_base = pci_resource_start(dev->pdev, 0);
856 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
857 if (!dev->iseg) {
858 err = -ENOMEM;
859 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
860 goto err_clr_master;
861 }
862
863 return 0;
864
865 err_clr_master:
866 pci_clear_master(dev->pdev);
867 release_bar(dev->pdev);
868 err_disable:
869 mlx5_pci_disable_device(dev);
870
871 err_dbg:
872 debugfs_remove(priv->dbg_root);
873 return err;
874 }
875
876 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
877 {
878 iounmap(dev->iseg);
879 pci_clear_master(dev->pdev);
880 release_bar(dev->pdev);
881 mlx5_pci_disable_device(dev);
882 debugfs_remove(priv->dbg_root);
883 }
884
885 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
886 {
887 struct pci_dev *pdev = dev->pdev;
888 int err;
889
890 err = mlx5_query_board_id(dev);
891 if (err) {
892 dev_err(&pdev->dev, "query board id failed\n");
893 goto out;
894 }
895
896 err = mlx5_eq_init(dev);
897 if (err) {
898 dev_err(&pdev->dev, "failed to initialize eq\n");
899 goto out;
900 }
901
902 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
903
904 err = mlx5_init_cq_table(dev);
905 if (err) {
906 dev_err(&pdev->dev, "failed to initialize cq table\n");
907 goto err_eq_cleanup;
908 }
909
910 mlx5_init_qp_table(dev);
911
912 mlx5_init_srq_table(dev);
913
914 mlx5_init_mkey_table(dev);
915
916 err = mlx5_init_rl_table(dev);
917 if (err) {
918 dev_err(&pdev->dev, "Failed to init rate limiting\n");
919 goto err_tables_cleanup;
920 }
921
922 #ifdef CONFIG_MLX5_CORE_EN
923 err = mlx5_eswitch_init(dev);
924 if (err) {
925 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
926 goto err_rl_cleanup;
927 }
928 #endif
929
930 err = mlx5_sriov_init(dev);
931 if (err) {
932 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
933 goto err_eswitch_cleanup;
934 }
935
936 return 0;
937
938 err_eswitch_cleanup:
939 #ifdef CONFIG_MLX5_CORE_EN
940 mlx5_eswitch_cleanup(dev->priv.eswitch);
941
942 err_rl_cleanup:
943 #endif
944 mlx5_cleanup_rl_table(dev);
945
946 err_tables_cleanup:
947 mlx5_cleanup_mkey_table(dev);
948 mlx5_cleanup_srq_table(dev);
949 mlx5_cleanup_qp_table(dev);
950 mlx5_cleanup_cq_table(dev);
951
952 err_eq_cleanup:
953 mlx5_eq_cleanup(dev);
954
955 out:
956 return err;
957 }
958
959 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
960 {
961 mlx5_sriov_cleanup(dev);
962 #ifdef CONFIG_MLX5_CORE_EN
963 mlx5_eswitch_cleanup(dev->priv.eswitch);
964 #endif
965 mlx5_cleanup_rl_table(dev);
966 mlx5_cleanup_mkey_table(dev);
967 mlx5_cleanup_srq_table(dev);
968 mlx5_cleanup_qp_table(dev);
969 mlx5_cleanup_cq_table(dev);
970 mlx5_eq_cleanup(dev);
971 }
972
973 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
974 bool boot)
975 {
976 struct pci_dev *pdev = dev->pdev;
977 int err;
978
979 mutex_lock(&dev->intf_state_mutex);
980 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
981 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
982 __func__);
983 goto out;
984 }
985
986 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
987 fw_rev_min(dev), fw_rev_sub(dev));
988
989 /* on load removing any previous indication of internal error, device is
990 * up
991 */
992 dev->state = MLX5_DEVICE_STATE_UP;
993
994 err = mlx5_cmd_init(dev);
995 if (err) {
996 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
997 goto out_err;
998 }
999
1000 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1001 if (err) {
1002 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1003 FW_INIT_TIMEOUT_MILI);
1004 goto err_cmd_cleanup;
1005 }
1006
1007 err = mlx5_core_enable_hca(dev, 0);
1008 if (err) {
1009 dev_err(&pdev->dev, "enable hca failed\n");
1010 goto err_cmd_cleanup;
1011 }
1012
1013 err = mlx5_core_set_issi(dev);
1014 if (err) {
1015 dev_err(&pdev->dev, "failed to set issi\n");
1016 goto err_disable_hca;
1017 }
1018
1019 err = mlx5_satisfy_startup_pages(dev, 1);
1020 if (err) {
1021 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1022 goto err_disable_hca;
1023 }
1024
1025 err = set_hca_ctrl(dev);
1026 if (err) {
1027 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1028 goto reclaim_boot_pages;
1029 }
1030
1031 err = handle_hca_cap(dev);
1032 if (err) {
1033 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1034 goto reclaim_boot_pages;
1035 }
1036
1037 err = handle_hca_cap_atomic(dev);
1038 if (err) {
1039 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1040 goto reclaim_boot_pages;
1041 }
1042
1043 err = mlx5_satisfy_startup_pages(dev, 0);
1044 if (err) {
1045 dev_err(&pdev->dev, "failed to allocate init pages\n");
1046 goto reclaim_boot_pages;
1047 }
1048
1049 err = mlx5_pagealloc_start(dev);
1050 if (err) {
1051 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1052 goto reclaim_boot_pages;
1053 }
1054
1055 err = mlx5_cmd_init_hca(dev);
1056 if (err) {
1057 dev_err(&pdev->dev, "init hca failed\n");
1058 goto err_pagealloc_stop;
1059 }
1060
1061 mlx5_set_driver_version(dev);
1062
1063 mlx5_start_health_poll(dev);
1064
1065 err = mlx5_query_hca_caps(dev);
1066 if (err) {
1067 dev_err(&pdev->dev, "query hca failed\n");
1068 goto err_stop_poll;
1069 }
1070
1071 if (boot && mlx5_init_once(dev, priv)) {
1072 dev_err(&pdev->dev, "sw objs init failed\n");
1073 goto err_stop_poll;
1074 }
1075
1076 err = mlx5_enable_msix(dev);
1077 if (err) {
1078 dev_err(&pdev->dev, "enable msix failed\n");
1079 goto err_cleanup_once;
1080 }
1081
1082 err = mlx5_alloc_uuars(dev, &priv->uuari);
1083 if (err) {
1084 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1085 goto err_disable_msix;
1086 }
1087
1088 err = mlx5_start_eqs(dev);
1089 if (err) {
1090 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1091 goto err_free_uar;
1092 }
1093
1094 err = alloc_comp_eqs(dev);
1095 if (err) {
1096 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1097 goto err_stop_eqs;
1098 }
1099
1100 err = mlx5_irq_set_affinity_hints(dev);
1101 if (err) {
1102 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1103 goto err_affinity_hints;
1104 }
1105
1106 err = mlx5_init_fs(dev);
1107 if (err) {
1108 dev_err(&pdev->dev, "Failed to init flow steering\n");
1109 goto err_fs;
1110 }
1111
1112 #ifdef CONFIG_MLX5_CORE_EN
1113 mlx5_eswitch_attach(dev->priv.eswitch);
1114 #endif
1115
1116 err = mlx5_sriov_attach(dev);
1117 if (err) {
1118 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1119 goto err_sriov;
1120 }
1121
1122 if (mlx5_device_registered(dev)) {
1123 mlx5_attach_device(dev);
1124 } else {
1125 err = mlx5_register_device(dev);
1126 if (err) {
1127 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1128 goto err_reg_dev;
1129 }
1130 }
1131
1132 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1133 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1134 out:
1135 mutex_unlock(&dev->intf_state_mutex);
1136
1137 return 0;
1138
1139 err_reg_dev:
1140 mlx5_sriov_detach(dev);
1141
1142 err_sriov:
1143 #ifdef CONFIG_MLX5_CORE_EN
1144 mlx5_eswitch_detach(dev->priv.eswitch);
1145 #endif
1146 mlx5_cleanup_fs(dev);
1147
1148 err_fs:
1149 mlx5_irq_clear_affinity_hints(dev);
1150
1151 err_affinity_hints:
1152 free_comp_eqs(dev);
1153
1154 err_stop_eqs:
1155 mlx5_stop_eqs(dev);
1156
1157 err_free_uar:
1158 mlx5_free_uuars(dev, &priv->uuari);
1159
1160 err_disable_msix:
1161 mlx5_disable_msix(dev);
1162
1163 err_cleanup_once:
1164 if (boot)
1165 mlx5_cleanup_once(dev);
1166
1167 err_stop_poll:
1168 mlx5_stop_health_poll(dev);
1169 if (mlx5_cmd_teardown_hca(dev)) {
1170 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1171 goto out_err;
1172 }
1173
1174 err_pagealloc_stop:
1175 mlx5_pagealloc_stop(dev);
1176
1177 reclaim_boot_pages:
1178 mlx5_reclaim_startup_pages(dev);
1179
1180 err_disable_hca:
1181 mlx5_core_disable_hca(dev, 0);
1182
1183 err_cmd_cleanup:
1184 mlx5_cmd_cleanup(dev);
1185
1186 out_err:
1187 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1188 mutex_unlock(&dev->intf_state_mutex);
1189
1190 return err;
1191 }
1192
1193 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1194 bool cleanup)
1195 {
1196 int err = 0;
1197
1198 if (cleanup)
1199 mlx5_drain_health_wq(dev);
1200
1201 mutex_lock(&dev->intf_state_mutex);
1202 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1203 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1204 __func__);
1205 if (cleanup)
1206 mlx5_cleanup_once(dev);
1207 goto out;
1208 }
1209
1210 if (mlx5_device_registered(dev))
1211 mlx5_detach_device(dev);
1212
1213 mlx5_sriov_detach(dev);
1214 #ifdef CONFIG_MLX5_CORE_EN
1215 mlx5_eswitch_detach(dev->priv.eswitch);
1216 #endif
1217 mlx5_cleanup_fs(dev);
1218 mlx5_irq_clear_affinity_hints(dev);
1219 free_comp_eqs(dev);
1220 mlx5_stop_eqs(dev);
1221 mlx5_free_uuars(dev, &priv->uuari);
1222 mlx5_disable_msix(dev);
1223 if (cleanup)
1224 mlx5_cleanup_once(dev);
1225 mlx5_stop_health_poll(dev);
1226 err = mlx5_cmd_teardown_hca(dev);
1227 if (err) {
1228 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1229 goto out;
1230 }
1231 mlx5_pagealloc_stop(dev);
1232 mlx5_reclaim_startup_pages(dev);
1233 mlx5_core_disable_hca(dev, 0);
1234 mlx5_cmd_cleanup(dev);
1235
1236 out:
1237 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1238 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1239 mutex_unlock(&dev->intf_state_mutex);
1240 return err;
1241 }
1242
1243 struct mlx5_core_event_handler {
1244 void (*event)(struct mlx5_core_dev *dev,
1245 enum mlx5_dev_event event,
1246 void *data);
1247 };
1248
1249 static const struct devlink_ops mlx5_devlink_ops = {
1250 #ifdef CONFIG_MLX5_CORE_EN
1251 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1252 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1253 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1254 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1255 #endif
1256 };
1257
1258 #define MLX5_IB_MOD "mlx5_ib"
1259 static int init_one(struct pci_dev *pdev,
1260 const struct pci_device_id *id)
1261 {
1262 struct mlx5_core_dev *dev;
1263 struct devlink *devlink;
1264 struct mlx5_priv *priv;
1265 int err;
1266
1267 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1268 if (!devlink) {
1269 dev_err(&pdev->dev, "kzalloc failed\n");
1270 return -ENOMEM;
1271 }
1272
1273 dev = devlink_priv(devlink);
1274 priv = &dev->priv;
1275 priv->pci_dev_data = id->driver_data;
1276
1277 pci_set_drvdata(pdev, dev);
1278
1279 dev->pdev = pdev;
1280 dev->event = mlx5_core_event;
1281 dev->profile = &profile[prof_sel];
1282
1283 INIT_LIST_HEAD(&priv->ctx_list);
1284 spin_lock_init(&priv->ctx_lock);
1285 mutex_init(&dev->pci_status_mutex);
1286 mutex_init(&dev->intf_state_mutex);
1287 err = mlx5_pci_init(dev, priv);
1288 if (err) {
1289 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1290 goto clean_dev;
1291 }
1292
1293 err = mlx5_health_init(dev);
1294 if (err) {
1295 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1296 goto close_pci;
1297 }
1298
1299 mlx5_pagealloc_init(dev);
1300
1301 err = mlx5_load_one(dev, priv, true);
1302 if (err) {
1303 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1304 goto clean_health;
1305 }
1306
1307 err = request_module_nowait(MLX5_IB_MOD);
1308 if (err)
1309 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1310
1311 err = devlink_register(devlink, &pdev->dev);
1312 if (err)
1313 goto clean_load;
1314
1315 return 0;
1316
1317 clean_load:
1318 mlx5_unload_one(dev, priv, true);
1319 clean_health:
1320 mlx5_pagealloc_cleanup(dev);
1321 mlx5_health_cleanup(dev);
1322 close_pci:
1323 mlx5_pci_close(dev, priv);
1324 clean_dev:
1325 pci_set_drvdata(pdev, NULL);
1326 devlink_free(devlink);
1327
1328 return err;
1329 }
1330
1331 static void remove_one(struct pci_dev *pdev)
1332 {
1333 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1334 struct devlink *devlink = priv_to_devlink(dev);
1335 struct mlx5_priv *priv = &dev->priv;
1336
1337 devlink_unregister(devlink);
1338 mlx5_unregister_device(dev);
1339
1340 if (mlx5_unload_one(dev, priv, true)) {
1341 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1342 mlx5_health_cleanup(dev);
1343 return;
1344 }
1345
1346 mlx5_pagealloc_cleanup(dev);
1347 mlx5_health_cleanup(dev);
1348 mlx5_pci_close(dev, priv);
1349 pci_set_drvdata(pdev, NULL);
1350 devlink_free(devlink);
1351 }
1352
1353 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1354 pci_channel_state_t state)
1355 {
1356 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1357 struct mlx5_priv *priv = &dev->priv;
1358
1359 dev_info(&pdev->dev, "%s was called\n", __func__);
1360
1361 mlx5_enter_error_state(dev);
1362 mlx5_unload_one(dev, priv, false);
1363 /* In case of kernel call save the pci state and drain the health wq */
1364 if (state) {
1365 pci_save_state(pdev);
1366 mlx5_drain_health_wq(dev);
1367 mlx5_pci_disable_device(dev);
1368 }
1369
1370 return state == pci_channel_io_perm_failure ?
1371 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1372 }
1373
1374 /* wait for the device to show vital signs by waiting
1375 * for the health counter to start counting.
1376 */
1377 static int wait_vital(struct pci_dev *pdev)
1378 {
1379 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1380 struct mlx5_core_health *health = &dev->priv.health;
1381 const int niter = 100;
1382 u32 last_count = 0;
1383 u32 count;
1384 int i;
1385
1386 for (i = 0; i < niter; i++) {
1387 count = ioread32be(health->health_counter);
1388 if (count && count != 0xffffffff) {
1389 if (last_count && last_count != count) {
1390 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1391 return 0;
1392 }
1393 last_count = count;
1394 }
1395 msleep(50);
1396 }
1397
1398 return -ETIMEDOUT;
1399 }
1400
1401 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1402 {
1403 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1404 int err;
1405
1406 dev_info(&pdev->dev, "%s was called\n", __func__);
1407
1408 err = mlx5_pci_enable_device(dev);
1409 if (err) {
1410 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1411 , __func__, err);
1412 return PCI_ERS_RESULT_DISCONNECT;
1413 }
1414
1415 pci_set_master(pdev);
1416 pci_restore_state(pdev);
1417
1418 if (wait_vital(pdev)) {
1419 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1420 return PCI_ERS_RESULT_DISCONNECT;
1421 }
1422
1423 return PCI_ERS_RESULT_RECOVERED;
1424 }
1425
1426 static void mlx5_pci_resume(struct pci_dev *pdev)
1427 {
1428 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1429 struct mlx5_priv *priv = &dev->priv;
1430 int err;
1431
1432 dev_info(&pdev->dev, "%s was called\n", __func__);
1433
1434 err = mlx5_load_one(dev, priv, false);
1435 if (err)
1436 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1437 , __func__, err);
1438 else
1439 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1440 }
1441
1442 static const struct pci_error_handlers mlx5_err_handler = {
1443 .error_detected = mlx5_pci_err_detected,
1444 .slot_reset = mlx5_pci_slot_reset,
1445 .resume = mlx5_pci_resume
1446 };
1447
1448 static void shutdown(struct pci_dev *pdev)
1449 {
1450 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1451 struct mlx5_priv *priv = &dev->priv;
1452
1453 dev_info(&pdev->dev, "Shutdown was called\n");
1454 /* Notify mlx5 clients that the kernel is being shut down */
1455 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1456 mlx5_unload_one(dev, priv, false);
1457 mlx5_pci_disable_device(dev);
1458 }
1459
1460 static const struct pci_device_id mlx5_core_pci_table[] = {
1461 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1462 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1463 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1464 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1465 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1466 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1467 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1468 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1469 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
1470 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5, PCIe 4.0 VF */
1471 { 0, }
1472 };
1473
1474 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1475
1476 void mlx5_disable_device(struct mlx5_core_dev *dev)
1477 {
1478 mlx5_pci_err_detected(dev->pdev, 0);
1479 }
1480
1481 void mlx5_recover_device(struct mlx5_core_dev *dev)
1482 {
1483 mlx5_pci_disable_device(dev);
1484 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1485 mlx5_pci_resume(dev->pdev);
1486 }
1487
1488 static struct pci_driver mlx5_core_driver = {
1489 .name = DRIVER_NAME,
1490 .id_table = mlx5_core_pci_table,
1491 .probe = init_one,
1492 .remove = remove_one,
1493 .shutdown = shutdown,
1494 .err_handler = &mlx5_err_handler,
1495 .sriov_configure = mlx5_core_sriov_configure,
1496 };
1497
1498 static void mlx5_core_verify_params(void)
1499 {
1500 if (prof_sel >= ARRAY_SIZE(profile)) {
1501 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1502 prof_sel,
1503 ARRAY_SIZE(profile) - 1,
1504 MLX5_DEFAULT_PROF);
1505 prof_sel = MLX5_DEFAULT_PROF;
1506 }
1507 }
1508
1509 static int __init init(void)
1510 {
1511 int err;
1512
1513 mlx5_core_verify_params();
1514 mlx5_register_debugfs();
1515
1516 err = pci_register_driver(&mlx5_core_driver);
1517 if (err)
1518 goto err_debug;
1519
1520 #ifdef CONFIG_MLX5_CORE_EN
1521 mlx5e_init();
1522 #endif
1523
1524 return 0;
1525
1526 err_debug:
1527 mlx5_unregister_debugfs();
1528 return err;
1529 }
1530
1531 static void __exit cleanup(void)
1532 {
1533 #ifdef CONFIG_MLX5_CORE_EN
1534 mlx5e_cleanup();
1535 #endif
1536 pci_unregister_driver(&mlx5_core_driver);
1537 mlx5_unregister_debugfs();
1538 }
1539
1540 module_init(init);
1541 module_exit(cleanup);
Linux with added FPC-III support