Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

   1 Hisilicon Platforms Device Tree Bindings
   2 ----------------------------------------------------
   3
   4 Hi4511 Board
   5 Required root node properties:
   6         - compatible = "hisilicon,hi3620-hi4511";
   7
   8 HiP04 D01 Board
   9 Required root node properties:
  10         - compatible = "hisilicon,hip04-d01";
  11
  12 HiP01 ca9x2 Board
  13 Required root node properties:
  14         - compatible = "hisilicon,hip01-ca9x2";
  15
  16
  17 Hisilicon system controller
  18
  19 Required properties:
  20 - compatible : "hisilicon,sysctrl"
  21 - reg : Register address and size
  22
  23 Optional properties:
  24 - smp-offset : offset in sysctrl for notifying slave cpu booting
  25                 cpu 1, reg;
  26                 cpu 2, reg + 0x4;
  27                 cpu 3, reg + 0x8;
  28                 If reg value is not zero, cpun exit wfi and go
  29 - resume-offset : offset in sysctrl for notifying cpu0 when resume
  30 - reboot-offset : offset in sysctrl for system reboot
  31
  32 Example:
  33
  34         /* for Hi3620 */
  35         sysctrl: system-controller@fc802000 {
  36                 compatible = "hisilicon,sysctrl";
  37                 reg = <0xfc802000 0x1000>;
  38                 smp-offset = <0x31c>;
  39                 resume-offset = <0x308>;
  40                 reboot-offset = <0x4>;
  41         };
  42
  43 -----------------------------------------------------------------------
  44 Hisilicon HiP01 system controller
  45
  46 Required properties:
  47 - compatible : "hisilicon,hip01-sysctrl"
  48 - reg : Register address and size
  49
  50 The HiP01 system controller is mostly compatible with hisilicon
  51 system controller,but it has some specific control registers for
  52 HIP01 SoC family, such as slave core boot, and also some same
  53 registers located at different offset.
  54
  55 Example:
  56
  57         /* for hip01-ca9x2 */
  58         sysctrl: system-controller@10000000 {
  59                 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
  60                 reg = <0x10000000 0x1000>;
  61                 reboot-offset = <0x4>;
  62         };
  63
  64 -----------------------------------------------------------------------
  65 Hisilicon CPU controller
  66
  67 Required properties:
  68 - compatible : "hisilicon,cpuctrl"
  69 - reg : Register address and size
  70
  71 The clock registers and power registers of secondary cores are defined
  72 in CPU controller, especially in HIX5HD2 SoC.
  73
  74 -----------------------------------------------------------------------
  75 PCTRL: Peripheral misc control register
  76
  77 Required Properties:
  78 - compatible: "hisilicon,pctrl"
  79 - reg: Address and size of pctrl.
  80
  81 Example:
  82
  83         /* for Hi3620 */
  84         pctrl: pctrl@fca09000 {
  85                 compatible = "hisilicon,pctrl";
  86                 reg = <0xfca09000 0x1000>;
  87         };
  88
  89 -----------------------------------------------------------------------
  90 Fabric:
  91
  92 Required Properties:
  93 - compatible: "hisilicon,hip04-fabric";
  94 - reg: Address and size of Fabric
  95
  96 -----------------------------------------------------------------------
  97 Bootwrapper boot method (software protocol on SMP):
  98
  99 Required Properties:
 100 - compatible: "hisilicon,hip04-bootwrapper";
 101 - boot-method: Address and size of boot method.
 102   [0]: bootwrapper physical address
 103   [1]: bootwrapper size
 104   [2]: relocation physical address
 105   [3]: relocation size