1 Marvell Berlin SoC Family Device Tree Bindings
2 ---------------------------------------------------------------
4 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
5 shall have the following properties:
7 * Required root node properties:
8 compatible: must contain "marvell,berlin"
10 In addition, the above compatible shall be extended with the specific
11 SoC and board used. Currently known SoC compatibles are:
12 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
13 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
14 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
15 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
16 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
21 model = "Sony NSZ-GS7";
22 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
27 * Marvell Berlin CPU control bindings
29 CPU control register allows various operations on CPUs, like resetting them
33 - compatible: should be "marvell,berlin-cpu-ctrl"
34 - reg: address and length of the register set
39 compatible = "marvell,berlin-cpu-ctrl";
40 reg = <0xf7dd0000 0x10000>;
43 * Marvell Berlin2 chip control binding
45 Marvell Berlin SoCs have a chip control register set providing several
46 individual registers dealing with pinmux, padmux, clock, reset, and secondary
47 CPU boot address. Unfortunately, the individual registers are spread among the
48 chip control registers, so there should be a single DT node only providing the
49 different functions which are described below.
52 - compatible: shall be one of
53 "marvell,berlin2-chip-ctrl" for BG2
54 "marvell,berlin2cd-chip-ctrl" for BG2CD
55 "marvell,berlin2q-chip-ctrl" for BG2Q
56 - reg: address and length of following register sets for
57 BG2/BG2CD: chip control register set
58 BG2Q: chip control register set and cpu pll registers
60 * Marvell Berlin2 system control binding
62 Marvell Berlin SoCs have a system control register set providing several
63 individual registers dealing with pinmux, padmux, and reset.
66 - compatible: should be one of
67 "marvell,berlin2-system-ctrl" for BG2
68 "marvell,berlin2cd-system-ctrl" for BG2CD
69 "marvell,berlin2q-system-ctrl" for BG2Q
70 - reg: address and length of the system control register set
72 * Clock provider binding
74 As clock related registers are spread among the chip control registers, the
75 chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
76 SoCs share the same IP for PLLs and clocks, with some minor differences in
77 features and register layout.
80 - #clock-cells: shall be set to 1
81 - clocks: clock specifiers referencing the core clock input clocks
82 - clock-names: array of strings describing the input clock specifiers above.
83 Allowed clock-names for the reference clocks are
84 "refclk" for the SoCs osciallator input on all SoCs,
85 and SoC-specific input clocks for
86 BG2/BG2CD: "video_ext0" for the external video clock input
88 Clocks provided by core clocks shall be referenced by a clock specifier
89 indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
90 for the corresponding index mapping.
92 * Pin controller binding
94 Pin control registers are part of both register sets, chip control and system
95 control. The pins controlled are organized in groups, so no actual pin
96 information is needed.
98 A pin-controller node should contain subnodes representing the pin group
99 configurations, one per function. Each subnode has the group name and the muxing
102 Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
103 a 'function' in the pin-controller subsystem.
105 Required subnode-properties:
106 - groups: a list of strings describing the group names.
107 - function: a string describing the function used to mux the groups.
109 * Reset controller binding
111 A reset controller is part of the chip control registers set. The chip control
112 node also provides the reset. The register set is not at the same offset between
116 - #reset-cells: must be set to 2
120 chip: chip-control@ea0000 {
121 compatible = "marvell,berlin2-chip-ctrl";
124 reg = <0xea0000 0x400>;
125 clocks = <&refclk>, <&externaldev 0>;
126 clock-names = "refclk", "video_ext0";
128 spi1_pmux: spi1-pmux {
134 sysctrl: system-controller@d000 {
135 compatible = "marvell,berlin2-system-ctrl";
136 reg = <0xd000 0x100>;
138 uart0_pmux: uart0-pmux {
143 uart1_pmux: uart1-pmux {
148 uart2_pmux: uart2-pmux {