Documentation/devicetree/bindings/clock/renesas,sh73a0-cpg-clocks.txt

   1 These bindings should be considered EXPERIMENTAL for now.
   2
   3 * Renesas SH73A0 Clock Pulse Generator (CPG)
   4
   5 The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
   6 and several fixed ratio dividers.
   7
   8 Required Properties:
   9
  10   - compatible: Must be "renesas,sh73a0-cpg-clocks"
  11
  12   - reg: Base address and length of the memory resource used by the CPG
  13
  14   - clocks: Reference to the parent clocks ("extal1" and "extal2")
  15
  16   - #clock-cells: Must be 1
  17
  18   - clock-output-names: The names of the clocks. Supported clocks are "main",
  19     "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
  20     "m1", "m2", "z", "zx", and "hp".
  21
  22
  23 Example
  24 -------
  25
  26         cpg_clocks: cpg_clocks@e6150000 {
  27                 compatible = "renesas,sh73a0-cpg-clocks";
  28                 reg = <0 0xe6150000 0 0x10000>;
  29                 clocks = <&extal1_clk>, <&extal2_clk>;
  30                 #clock-cells = <1>;
  31                 clock-output-names = "main", "pll0", "pll1", "pll2",
  32                                      "pll3", "dsi0phy", "dsi1phy",
  33                                      "zg", "m3", "b", "m1", "m2",
  34                                      "z", "zx", "hp";
  35         };