1 Binding for a ST divider and multiplexer clock driver.
3 This binding uses the common clock binding[1].
4 Base address is located to the parent node. See clock binding[2]
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
11 - compatible : shall be:
12 "st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
13 "st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
14 "st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
15 "st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
16 "st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
17 "st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
19 - #clock-cells : From common clock binding; shall be set to 1.
21 - clocks : From common clock binding
23 - clock-output-names : From common clock binding.
28 reg = <0xfd345000 0xb50>;
30 clk_m_a1_div1: clk-m-a1-div1 {
32 compatible = "st,clkgena-divmux-c32-odf1",
35 clocks = <&clk_m_a1_osc_prediv>,
36 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
37 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
39 clock-output-names = "clk-m-rx-icn-ts",