Linux 4.1.18
[linux/fpc-iii.git] / Documentation / devicetree / bindings / clock / st / st,clkgen.txt
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1 Binding for a Clockgen hardware block found on
2 certain STMicroelectronics consumer electronics SoC devices.
4 A Clockgen node can contain pll, diviser or multiplexer nodes.
6 We will find only the base address of the Clockgen, this base
7 address is common of all subnode.
9         clockgen_node {
10                 reg = <>;
12                 pll_node {
13                         ...
14                 };
16                 prediv_node {
17                         ...
18                 };
20                 divmux_node {
21                         ...
22                 };
24                 quadfs_node {
25                         ...
26                 };
28                 mux_node {
29                         ...
30                 };
32                 vcc_node {
33                         ...
34                 };
36                 flexgen_node {
37                         ...
38                 };
39                 ...
40         };
42 This binding uses the common clock binding[1].
43 Each subnode should use the binding discribe in [2]..[7]
45 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
46 [2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
47 [3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
48 [4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
49 [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
50 [6] Documentation/devicetree/bindings/clock/st,vcc.txt
51 [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
52 [8] Documentation/devicetree/bindings/clock/st,flexgen.txt
55 Required properties:
56 - reg : A Base address and length of the register set.
58 Example:
60         clockgen-a@fee62000 {
62                 reg = <0xfee62000 0xb48>;
64                 clk_s_a0_pll: clk-s-a0-pll {
65                         #clock-cells = <1>;
66                         compatible = "st,clkgena-plls-c65";
68                         clocks = <&clk-sysin>;
70                         clock-output-names = "clk-s-a0-pll0-hs",
71                                              "clk-s-a0-pll0-ls",
72                                              "clk-s-a0-pll1";
73                 };
75                 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
76                         #clock-cells = <0>;
77                         compatible = "st,clkgena-prediv-c65",
78                                      "st,clkgena-prediv";
80                         clocks = <&clk_sysin>;
82                         clock-output-names = "clk-s-a0-osc-prediv";
83                 };
85                 clk_s_a0_hs: clk-s-a0-hs {
86                         #clock-cells = <1>;
87                         compatible = "st,clkgena-divmux-c65-hs",
88                                      "st,clkgena-divmux";
90                         clocks = <&clk-s_a0_osc_prediv>,
91                                  <&clk-s_a0_pll 0>, /* pll0 hs */
92                                  <&clk-s_a0_pll 2>; /* pll1 */
94                         clock-output-names = "clk-s-fdma-0",
95                                              "clk-s-fdma-1",
96                                              ""; /* clk-s-jit-sense */
97                                              /* fourth output unused */
98                 };
99         };