1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
8 =====================================================================
13 Node defines the base address of the SEC 6 block.
14 This block specifies the address range of all global
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
23 Definition: Must include "fsl,sec-v6.0".
28 Definition: A standard property. Define the 'ERA' of the SEC
34 Definition: A standard property. Defines the number of cells
35 for representing physical addresses in child nodes.
40 Definition: A standard property. Defines the number of cells
41 for representing the size of physical addresses in
46 Value type: <prop-encoded-array>
47 Definition: A standard property. Specifies the physical
48 address and length of the SEC 6 configuration registers.
52 Value type: <prop-encoded-array>
53 Definition: A standard property. Specifies the physical address
54 range of the SEC 6.0 register space (-SNVS not included). A
55 triplet that includes the child address, parent address, &
58 Note: All other standard properties (see the ePAPR) are allowed
63 compatible = "fsl,sec-v6.0";
67 reg = <0xa0000 0x20000>;
68 ranges = <0 0xa0000 0x20000>;
71 =====================================================================
74 Child of the crypto node defines data processing interface to SEC 6
75 across the peripheral bus for purposes of processing
76 cryptographic descriptors. The specified address
77 range can be made visible to one (or more) cores.
78 The interrupt defined for this node is controlled within
79 the address range of this node.
84 Definition: Must include "fsl,sec-v6.0-job-ring".
88 Value type: <prop-encoded-array>
89 Definition: Specifies a two JR parameters: an offset from
90 the parent physical address and the length the JR registers.
94 Value type: <prop_encoded-array>
95 Definition: Specifies the interrupts generated by this
96 device. The value of the interrupts property
97 consists of one interrupt specifier. The format
98 of the specifier is defined by the binding document
99 describing the node's interrupt parent.
103 compatible = "fsl,sec-v6.0-job-ring";
104 reg = <0x1000 0x1000>;
105 interrupts = <49 2 0 0>;
108 ===================================================================
111 Since some chips may contain more than one SEC, the dtsi contains
112 only the node contents, not the node itself. A chip using the SEC
113 should include the dtsi inside each SEC node. Example:
115 In qoriq-sec6.0.dtsi:
117 compatible = "fsl,sec-v6.0";
119 #address-cells = <1>;
123 compatible = "fsl,sec-v6.0-job-ring",
124 "fsl,sec-v5.2-job-ring",
125 "fsl,sec-v5.0-job-ring",
126 "fsl,sec-v4.4-job-ring",
127 "fsl,sec-v4.0-job-ring";
128 reg = <0x1000 0x1000>;
132 compatible = "fsl,sec-v6.0-job-ring",
133 "fsl,sec-v5.2-job-ring",
134 "fsl,sec-v5.0-job-ring",
135 "fsl,sec-v4.4-job-ring",
136 "fsl,sec-v4.0-job-ring";
137 reg = <0x2000 0x1000>;
140 In the C293 device tree, we add the include of public property:
143 /include/ "qoriq-sec6.0.dtsi"
147 reg = <0xa0000 0x20000>;
148 ranges = <0 0xa0000 0x20000>;
151 interrupts = <49 2 0 0>;
155 interrupts = <50 2 0 0>;