1 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
2 target devices. It can be configured to have one channel or two channels.
3 If configured as two channels, one is to transmit to the device and another
4 is to receive from the device.
7 - compatible: Should be "xlnx,axi-dma-1.00.a"
8 - #dma-cells: Should be <1>, see "dmas" property below
9 - reg: Should contain DMA registers location and length.
10 - dma-channel child node: Should have atleast one channel and can have upto
11 two channels per device. This node specifies the properties of each
12 DMA channel (see child node properties below).
15 - xlnx,include-sg: Tells whether configured for Scatter-mode in
18 Required child node properties:
19 - compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
20 "xlnx,axi-dma-s2mm-channel".
21 - interrupts: Should contain per channel DMA interrupts.
22 - xlnx,datawidth: Should contain the stream data width, take values
25 Option child node properties:
26 - xlnx,include-dre: Tells whether hardware is configured for Data
32 axi_dma_0: axidma@40400000 {
33 compatible = "xlnx,axi-dma-1.00.a";
35 reg = < 0x40400000 0x10000 >;
36 dma-channel@40400000 {
37 compatible = "xlnx,axi-dma-mm2s-channel";
38 interrupts = < 0 59 4 >;
39 xlnx,datawidth = <0x40>;
41 dma-channel@40400030 {
42 compatible = "xlnx,axi-dma-s2mm-channel";
43 interrupts = < 0 58 4 >;
44 xlnx,datawidth = <0x40>;
52 - dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
53 where Channel ID is '0' for write/tx and '1' for read/rx
55 - dma-names: a list of DMA channel names, one per "dmas" entry
60 dmatest_0: dmatest@0 {
61 compatible ="xlnx,axi-dma-test-1.00.a";
64 dma-names = "dma0", "dma1";