4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
19 The host1x top-level node defines a number of children, each representing one
20 of the following host1x client modules:
25 - compatible: "nvidia,tegra<chip>-mpe"
26 - reg: Physical base address and length of the controller's registers.
27 - interrupts: The interrupt outputs from the controller.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
38 - compatible: "nvidia,tegra<chip>-vi"
39 - reg: Physical base address and length of the controller's registers.
40 - interrupts: The interrupt outputs from the controller.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
48 - epp: encoder pre-processor
51 - compatible: "nvidia,tegra<chip>-epp"
52 - reg: Physical base address and length of the controller's registers.
53 - interrupts: The interrupt outputs from the controller.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
61 - isp: image signal processor
64 - compatible: "nvidia,tegra<chip>-isp"
65 - reg: Physical base address and length of the controller's registers.
66 - interrupts: The interrupt outputs from the controller.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
69 - resets: Must contain an entry for each entry in reset-names.
70 See ../reset/reset.txt for details.
71 - reset-names: Must include the following entries:
74 - gr2d: 2D graphics engine
77 - compatible: "nvidia,tegra<chip>-gr2d"
78 - reg: Physical base address and length of the controller's registers.
79 - interrupts: The interrupt outputs from the controller.
80 - clocks: Must contain one entry, for the module clock.
81 See ../clocks/clock-bindings.txt for details.
82 - resets: Must contain an entry for each entry in reset-names.
83 See ../reset/reset.txt for details.
84 - reset-names: Must include the following entries:
87 - gr3d: 3D graphics engine
90 - compatible: "nvidia,tegra<chip>-gr3d"
91 - reg: Physical base address and length of the controller's registers.
92 - clocks: Must contain an entry for each entry in clock-names.
93 See ../clocks/clock-bindings.txt for details.
94 - clock-names: Must include the following entries:
95 (This property may be omitted if the only clock in the list is "3d")
97 This MUST be the first entry.
98 - 3d2 (Only required on SoCs with two 3D clocks)
99 - resets: Must contain an entry for each entry in reset-names.
100 See ../reset/reset.txt for details.
101 - reset-names: Must include the following entries:
103 - 3d2 (Only required on SoCs with two 3D clocks)
105 - dc: display controller
108 - compatible: "nvidia,tegra<chip>-dc"
109 - reg: Physical base address and length of the controller's registers.
110 - interrupts: The interrupt outputs from the controller.
111 - clocks: Must contain an entry for each entry in clock-names.
112 See ../clocks/clock-bindings.txt for details.
113 - clock-names: Must include the following entries:
115 This MUST be the first entry.
117 - resets: Must contain an entry for each entry in reset-names.
118 See ../reset/reset.txt for details.
119 - reset-names: Must include the following entries:
121 - nvidia,head: The number of the display controller head. This is used to
122 setup the various types of output to receive video data from the given
125 Each display controller node has a child node, named "rgb", that represents
126 the RGB output associated with the controller. It can take the following
128 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
129 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
130 - nvidia,edid: supplies a binary EDID blob
131 - nvidia,panel: phandle of a display panel
133 - hdmi: High Definition Multimedia Interface
136 - compatible: "nvidia,tegra<chip>-hdmi"
137 - reg: Physical base address and length of the controller's registers.
138 - interrupts: The interrupt outputs from the controller.
139 - hdmi-supply: supply for the +5V HDMI connector pin
140 - vdd-supply: regulator for supply voltage
141 - pll-supply: regulator for PLL
142 - clocks: Must contain an entry for each entry in clock-names.
143 See ../clocks/clock-bindings.txt for details.
144 - clock-names: Must include the following entries:
146 This MUST be the first entry.
148 - resets: Must contain an entry for each entry in reset-names.
149 See ../reset/reset.txt for details.
150 - reset-names: Must include the following entries:
154 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
155 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
156 - nvidia,edid: supplies a binary EDID blob
157 - nvidia,panel: phandle of a display panel
159 - tvo: TV encoder output
162 - compatible: "nvidia,tegra<chip>-tvo"
163 - reg: Physical base address and length of the controller's registers.
164 - interrupts: The interrupt outputs from the controller.
165 - clocks: Must contain one entry, for the module clock.
166 See ../clocks/clock-bindings.txt for details.
168 - dsi: display serial interface
171 - compatible: "nvidia,tegra<chip>-dsi"
172 - reg: Physical base address and length of the controller's registers.
173 - clocks: Must contain an entry for each entry in clock-names.
174 See ../clocks/clock-bindings.txt for details.
175 - clock-names: Must include the following entries:
177 This MUST be the first entry.
180 - resets: Must contain an entry for each entry in reset-names.
181 See ../reset/reset.txt for details.
182 - reset-names: Must include the following entries:
184 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
185 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
186 which pads are used by this DSI output and need to be calibrated. See also
187 ../mipi/nvidia,tegra114-mipi.txt.
190 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
191 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
192 - nvidia,edid: supplies a binary EDID blob
193 - nvidia,panel: phandle of a display panel
194 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
195 up with in order to support up to 8 data lanes
197 - sor: serial output resource
200 - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
201 must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
203 - reg: Physical base address and length of the controller's registers.
204 - interrupts: The interrupt outputs from the controller.
205 - clocks: Must contain an entry for each entry in clock-names.
206 See ../clocks/clock-bindings.txt for details.
207 - clock-names: Must include the following entries:
208 - sor: clock input for the SOR hardware
209 - parent: input for the pixel clock
210 - dp: reference clock for the SOR clock
211 - safe: safe reference for the SOR clock during power up
212 - resets: Must contain an entry for each entry in reset-names.
213 See ../reset/reset.txt for details.
214 - reset-names: Must include the following entries:
218 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
219 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
220 - nvidia,edid: supplies a binary EDID blob
221 - nvidia,panel: phandle of a display panel
223 Optional properties when driving an eDP output:
224 - nvidia,dpaux: phandle to a DispayPort AUX interface
226 - dpaux: DisplayPort AUX interface
227 - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
228 must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
230 - reg: Physical base address and length of the controller's registers.
231 - interrupts: The interrupt outputs from the controller.
232 - clocks: Must contain an entry for each entry in clock-names.
233 See ../clocks/clock-bindings.txt for details.
234 - clock-names: Must include the following entries:
235 - dpaux: clock input for the DPAUX hardware
236 - parent: reference clock
237 - resets: Must contain an entry for each entry in reset-names.
238 See ../reset/reset.txt for details.
239 - reset-names: Must include the following entries:
241 - vdd-supply: phandle of a supply that powers the DisplayPort link
249 compatible = "nvidia,tegra20-host1x", "simple-bus";
250 reg = <0x50000000 0x00024000>;
251 interrupts = <0 65 0x04 /* mpcore syncpt */
252 0 67 0x04>; /* mpcore general */
253 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
254 resets = <&tegra_car 28>;
255 reset-names = "host1x";
257 #address-cells = <1>;
260 ranges = <0x54000000 0x54000000 0x04000000>;
263 compatible = "nvidia,tegra20-mpe";
264 reg = <0x54040000 0x00040000>;
265 interrupts = <0 68 0x04>;
266 clocks = <&tegra_car TEGRA20_CLK_MPE>;
267 resets = <&tegra_car 60>;
272 compatible = "nvidia,tegra20-vi";
273 reg = <0x54080000 0x00040000>;
274 interrupts = <0 69 0x04>;
275 clocks = <&tegra_car TEGRA20_CLK_VI>;
276 resets = <&tegra_car 100>;
281 compatible = "nvidia,tegra20-epp";
282 reg = <0x540c0000 0x00040000>;
283 interrupts = <0 70 0x04>;
284 clocks = <&tegra_car TEGRA20_CLK_EPP>;
285 resets = <&tegra_car 19>;
290 compatible = "nvidia,tegra20-isp";
291 reg = <0x54100000 0x00040000>;
292 interrupts = <0 71 0x04>;
293 clocks = <&tegra_car TEGRA20_CLK_ISP>;
294 resets = <&tegra_car 23>;
299 compatible = "nvidia,tegra20-gr2d";
300 reg = <0x54140000 0x00040000>;
301 interrupts = <0 72 0x04>;
302 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
303 resets = <&tegra_car 21>;
308 compatible = "nvidia,tegra20-gr3d";
309 reg = <0x54180000 0x00040000>;
310 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
311 resets = <&tegra_car 24>;
316 compatible = "nvidia,tegra20-dc";
317 reg = <0x54200000 0x00040000>;
318 interrupts = <0 73 0x04>;
319 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
320 <&tegra_car TEGRA20_CLK_PLL_P>;
321 clock-names = "dc", "parent";
322 resets = <&tegra_car 27>;
331 compatible = "nvidia,tegra20-dc";
332 reg = <0x54240000 0x00040000>;
333 interrupts = <0 74 0x04>;
334 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
335 <&tegra_car TEGRA20_CLK_PLL_P>;
336 clock-names = "dc", "parent";
337 resets = <&tegra_car 26>;
346 compatible = "nvidia,tegra20-hdmi";
347 reg = <0x54280000 0x00040000>;
348 interrupts = <0 75 0x04>;
349 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
350 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
351 clock-names = "hdmi", "parent";
352 resets = <&tegra_car 51>;
353 reset-names = "hdmi";
358 compatible = "nvidia,tegra20-tvo";
359 reg = <0x542c0000 0x00040000>;
360 interrupts = <0 76 0x04>;
361 clocks = <&tegra_car TEGRA20_CLK_TVO>;
366 compatible = "nvidia,tegra20-dsi";
367 reg = <0x54300000 0x00040000>;
368 clocks = <&tegra_car TEGRA20_CLK_DSI>,
369 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
370 clock-names = "dsi", "parent";
371 resets = <&tegra_car 48>;