1 Xilinx Video Test Pattern Generator (TPG)
2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
11 TPG versions backward-compatible with previous versions should list all
12 compatible versions in the newer to older order.
14 - reg: Physical base address and length of the registers set for the device.
16 - clocks: Reference to the video core clock.
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
21 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
22 The TPG has a single output port numbered 0.
26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
27 video timings for the TPG test patterns.
29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
30 input. The GPIO active level corresponds to the selection of VTC-generated
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
34 synthesized with two ports and forbidden when synthesized with one port.
39 compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
40 reg = <0x40050000 0x10000>;
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
53 xlnx,video-format = <XVIP_VF_YUV_422>;
54 xlnx,video-width = <8>;
57 remote-endpoint = <&adv7611_out>;
63 xlnx,video-format = <XVIP_VF_YUV_422>;
64 xlnx,video-width = <8>;
67 remote-endpoint = <&switch_in0>;