3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
8 - compatible: "cavium,octeon-5750-bootbus-dma"
10 Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
12 - reg: The base address of the DMA Engine's register bank.
14 - interrupts: A single interrupt specifier.
17 dma0: dma-engine@1180000000100 {
18 compatible = "cavium,octeon-5750-bootbus-dma";
19 reg = <0x11800 0x00000100 0x0 0x8>;