1 * Synopsys Designware PCIe interface
4 - compatible: should contain "snps,dw-pcie" to identify the core.
5 - reg: Should contain the configuration address space.
6 - reg-names: Must be "config" for the PCIe configuration space.
7 (The old way of getting the configuration address space from "ranges"
8 is deprecated and should be avoided.)
9 - #address-cells: set to <3>
10 - #size-cells: set to <2>
11 - device_type: set to "pci"
12 - ranges: ranges for the PCI memory and I/O regions
13 - #interrupt-cells: set to <1>
14 - interrupt-map-mask and interrupt-map: standard PCI properties
15 to define the mapping of the PCIe interface to interrupt
17 - num-lanes: number of lanes to use
18 - clocks: Must contain an entry for each entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
20 - clock-names: Must include the following entries:
25 - reset-gpio: gpio pin number of power good signal
26 - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
27 specify this property, to keep backwards compatibility a range of 0x00-0xff
28 is assumed if not present)