Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt

   1 == Amlogic Meson pinmux controller ==
   2
   3 Required properties for the root node:
   4  - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
   5  - reg: address and size of registers controlling irq functionality
   6
   7 === GPIO sub-nodes ===
   8
   9 The 2 power domains of the controller (regular and always-on) are
  10 represented as sub-nodes and each of them acts as a GPIO controller.
  11
  12 Required properties for sub-nodes are:
  13  - reg: should contain address and size for mux, pull-enable, pull and
  14    gpio register sets
  15  - reg-names: an array of strings describing the "reg" entries. Must
  16    contain "mux", "pull" and "gpio". "pull-enable" is optional and
  17    when it is missing the "pull" registers are used instead
  18  - gpio-controller: identifies the node as a gpio controller
  19  - #gpio-cells: must be 2
  20
  21 Valid sub-node names are:
  22  - "banks" for the regular domain
  23  - "ao-bank" for the always-on domain
  24
  25 === Other sub-nodes ===
  26
  27 Child nodes without the "gpio-controller" represent some desired
  28 configuration for a pin or a group. Those nodes can be pinmux nodes or
  29 configuration nodes.
  30
  31 Required properties for pinmux nodes are:
  32  - groups: a list of pinmux groups. The list of all available groups
  33    depends on the SoC and can be found in driver sources.
  34  - function: the name of a function to activate for the specified set
  35    of groups. The list of all available functions depends on the SoC
  36    and can be found in driver sources.
  37
  38 Required properties for configuration nodes:
  39  - pins: a list of pin names
  40
  41 Configuration nodes support the generic properties "bias-disable",
  42 "bias-pull-up" and "bias-pull-down", described in file
  43 pinctrl-bindings.txt
  44
  45 === Example ===
  46
  47         pinctrl: pinctrl@c1109880 {
  48                 compatible = "amlogic,meson8-pinctrl";
  49                 reg = <0xc1109880 0x10>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges;
  53
  54                 gpio: banks@c11080b0 {
  55                         reg = <0xc11080b0 0x28>,
  56                               <0xc11080e8 0x18>,
  57                               <0xc1108120 0x18>,
  58                               <0xc1108030 0x30>;
  59                         reg-names = "mux", "pull", "pull-enable", "gpio";
  60                         gpio-controller;
  61                         #gpio-cells = <2>;
  62                };
  63
  64                 gpio_ao: ao-bank@c1108030 {
  65                         reg = <0xc8100014 0x4>,
  66                               <0xc810002c 0x4>,
  67                               <0xc8100024 0x8>;
  68                         reg-names = "mux", "pull", "gpio";
  69                         gpio-controller;
  70                         #gpio-cells = <2>;
  71                 };
  72
  73                 nand {
  74                         mux {
  75                                 groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
  76                                          "nand_io_rb0", "nand_ale", "nand_cle",
  77                                          "nand_wen_clk", "nand_ren_clk", "nand_dqs",
  78                                          "nand_ce2", "nand_ce3";
  79                                 function = "nand";
  80                         };
  81                 };
  82
  83                 uart_ao_a {
  84                         mux {
  85                                 groups = "uart_tx_ao_a", "uart_rx_ao_a",
  86                                          "uart_cts_ao_a", "uart_rts_ao_a";
  87                                 function = "uart_ao";
  88                         };
  89
  90                         conf {
  91                                 pins = "GPIOAO_0", "GPIOAO_1",
  92                                        "GPIOAO_2", "GPIOAO_3";
  93                                 bias-disable;
  94                         };
  95                 };
  96         };