1 * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
4 - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
5 The compatible <chip> indicated will be the first SoC to support an
6 additional mode or an USART new feature.
7 For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
8 - reg: Should contain registers location and length
9 - interrupts: Should contain interrupt
10 - clock-names: tuple listing input clock names.
11 Required elements: "usart"
12 - clocks: phandles to input clocks.
15 - atmel,use-dma-rx: use of PDC or DMA for receiving data
16 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
17 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
18 It will use specified PIO instead of the peripheral function pin for the USART feature.
19 If unsure, don't specify this property.
20 - add dma bindings for dma transfer:
21 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
22 memory peripheral interface and USART DMA channel ID, FIFO configuration.
23 Refer to dma.txt and atmel-dma.txt for details.
24 - dma-names: "rx" for RX channel, "tx" for TX channel.
26 <chip> compatible description:
27 - at91rm9200: legacy USART support
28 - at91sam9260: generic USART implementation for SAM9 SoCs
32 usart0: serial@fff8c000 {
33 compatible = "atmel,at91sam9260-usart";
34 reg = <0xfff8c000 0x4000>;
36 clocks = <&usart0_clk>;
37 clock-names = "usart";
40 rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
41 cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
42 dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
43 dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
44 dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
45 rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
49 usart0: serial@f001c000 {
50 compatible = "atmel,at91sam9260-usart";
51 reg = <0xf001c000 0x100>;
52 interrupts = <12 4 5>;
53 clocks = <&usart0_clk>;
54 clock-names = "usart";
59 dma-names = "tx", "rx";