1 Bindings for I2S controller built into xtfpga Xtensa bitstreams.
4 - compatible: shall be "cdns,xtfpga-i2s".
5 - reg: memory region (address and length) with device registers.
6 - interrupts: interrupt for the device.
7 - clocks: phandle to the clk used as master clock. I2S bus clock
12 i2s0: xtfpga-i2s@0d080000 {
13 #sound-dai-cells = <0>;
14 compatible = "cdns,xtfpga-i2s";
15 reg = <0x0d080000 0x40>;
17 clocks = <&cdce706 4>;