1 * Universal Flash Storage (UFS) Host Controller
3 UFSHC nodes are defined to describe on-chip UFS host controllers.
4 Each UFS controller instance should have its own node.
7 - compatible : compatible list, contains "jedec,ufs-1.1"
8 - interrupts : <interrupt mapping for UFS host controller IRQ>
9 - reg : <registers mapping>
12 - vdd-hba-supply : phandle to UFS host controller supply regulator node
13 - vcc-supply : phandle to VCC supply regulator node
14 - vccq-supply : phandle to VCCQ supply regulator node
15 - vccq2-supply : phandle to VCCQ2 supply regulator node
16 - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
17 or 2.7-3.6V. This boolean property when set, specifies
18 to use low voltage range of 1.7-1.95V. Note for external
19 UFS cards this property is invalid and valid VCC range is
21 - vcc-max-microamp : specifies max. load that can be drawn from vcc supply
22 - vccq-max-microamp : specifies max. load that can be drawn from vccq supply
23 - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
24 - <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
26 - clocks : List of phandle and clock specifier pairs
27 - clock-names : List of clock input name strings sorted in the same
28 order as the clocks property.
29 - freq-table-hz : Array of <min max> operating frequencies stored in the same
30 order as the clocks property. If this property is not
31 defined or a value in the array is "0" then it is assumed
32 that the frequency is set by the parent clock or a
33 fixed rate clock source.
35 Note: If above properties are not defined it can be assumed that the supply
36 regulators or clocks are always on.
40 compatible = "jedec,ufs-1.1";
41 reg = <0xfc598000 0x800>;
42 interrupts = <0 28 0>;
44 vdd-hba-supply = <&xxx_reg0>;
45 vdd-hba-fixed-regulator;
46 vcc-supply = <&xxx_reg1>;
48 vccq-supply = <&xxx_reg2>;
49 vccq2-supply = <&xxx_reg3>;
50 vcc-max-microamp = 500000;
51 vccq-max-microamp = 200000;
52 vccq2-max-microamp = 200000;
54 clocks = <&core 0>, <&ref 0>, <&iface 0>;
55 clock-names = "core_clk", "ref_clk", "iface_clk";
56 freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;