1 Texas Instruments DRA7x Display Subsystem
2 =========================================
4 See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
5 description about OMAP Display Subsystem bindings.
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
16 - syscon: phandle to control module core syscon node
20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
21 can be used to describe the video PLLs:
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
24 'pll1', 'pll2_clkctrl', 'pll2'
25 - clocks: handle to video1 pll clock and video2 pll clock
26 - clock-names: "video1_clk" and "video2_clk"
32 - DSS Submodules: HDMI
33 - Video port for DPI output
35 DPI Endpoint required properties:
36 - data-lines: number of lines used
43 - compatible: "ti,dra7-dispc"
44 - reg: address and length of the register space
45 - ti,hwmods: "dss_dispc"
46 - interrupts: the DISPC interrupt
47 - clocks: handle to fclk
54 - compatible: "ti,dra7-hdmi"
55 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
57 - reg-names: "wp", "pll", "phy", "core"
58 - interrupts: the HDMI interrupt line
59 - ti,hwmods: "dss_hdmi"
60 - vdda-supply: vdda power supply
61 - clocks: handles to fclk and pll clock
62 - clock-names: "fck", "sys_clk"
65 - Video port for HDMI output
67 HDMI Endpoint optional properties:
68 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
69 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)