arch/arm/mach-exynos/firmware.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics.
   3  * Kyungmin Park <kyungmin.park@samsung.com>
   4  * Tomasz Figa <t.figa@samsung.com>
   5  *
   6  * This program is free software,you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/io.h>
  13 #include <linux/init.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/cputype.h>
  19 #include <asm/firmware.h>
  20 #include <asm/hardware/cache-l2x0.h>
  21 #include <asm/suspend.h>
  22
  23 #include <mach/map.h>
  24
  25 #include "common.h"
  26 #include "smc.h"
  27
  28 #define EXYNOS_SLEEP_MAGIC      0x00000bad
  29 #define EXYNOS_AFTR_MAGIC       0xfcba0d10
  30 #define EXYNOS_BOOT_ADDR        0x8
  31 #define EXYNOS_BOOT_FLAG        0xc
  32
  33 static void exynos_save_cp15(void)
  34 {
  35         /* Save Power control and Diagnostic registers */
  36         asm ("mrc p15, 0, %0, c15, c0, 0\n"
  37              "mrc p15, 0, %1, c15, c0, 1\n"
  38              : "=r" (cp15_save_power), "=r" (cp15_save_diag)
  39              : : "cc");
  40 }
  41
  42 static int exynos_do_idle(unsigned long mode)
  43 {
  44         switch (mode) {
  45         case FW_DO_IDLE_AFTR:
  46                 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
  47                         exynos_save_cp15();
  48                 __raw_writel(virt_to_phys(exynos_cpu_resume_ns),
  49                              sysram_ns_base_addr + 0x24);
  50                 __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
  51                 if (soc_is_exynos3250()) {
  52                         exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
  53                                    SMC_POWERSTATE_IDLE, 0);
  54                         exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
  55                                    SMC_POWERSTATE_IDLE, 0);
  56                 } else
  57                         exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
  58                 break;
  59         case FW_DO_IDLE_SLEEP:
  60                 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
  61         }
  62         return 0;
  63 }
  64
  65 static int exynos_cpu_boot(int cpu)
  66 {
  67         /*
  68          * Exynos3250 doesn't need to send smc command for secondary CPU boot
  69          * because Exynos3250 removes WFE in secure mode.
  70          */
  71         if (soc_is_exynos3250())
  72                 return 0;
  73
  74         /*
  75          * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
  76          * But, Exynos4212 has only one secondary CPU so second parameter
  77          * isn't used for informing secure firmware about CPU id.
  78          */
  79         if (soc_is_exynos4212())
  80                 cpu = 0;
  81
  82         exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
  83         return 0;
  84 }
  85
  86 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
  87 {
  88         void __iomem *boot_reg;
  89
  90         if (!sysram_ns_base_addr)
  91                 return -ENODEV;
  92
  93         boot_reg = sysram_ns_base_addr + 0x1c;
  94
  95         /*
  96          * Almost all Exynos-series of SoCs that run in secure mode don't need
  97          * additional offset for every CPU, with Exynos4412 being the only
  98          * exception.
  99          */
 100         if (soc_is_exynos4412())
 101                 boot_reg += 4 * cpu;
 102
 103         __raw_writel(boot_addr, boot_reg);
 104         return 0;
 105 }
 106
 107 static int exynos_cpu_suspend(unsigned long arg)
 108 {
 109         flush_cache_all();
 110         outer_flush_all();
 111
 112         exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
 113
 114         pr_info("Failed to suspend the system\n");
 115         writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 116         return 1;
 117 }
 118
 119 static int exynos_suspend(void)
 120 {
 121         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 122                 exynos_save_cp15();
 123
 124         writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 125         writel(virt_to_phys(exynos_cpu_resume_ns),
 126                 sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
 127
 128         return cpu_suspend(0, exynos_cpu_suspend);
 129 }
 130
 131 static int exynos_resume(void)
 132 {
 133         writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
 134
 135         return 0;
 136 }
 137
 138 static const struct firmware_ops exynos_firmware_ops = {
 139         .do_idle                = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
 140         .set_cpu_boot_addr      = exynos_set_cpu_boot_addr,
 141         .cpu_boot               = exynos_cpu_boot,
 142         .suspend                = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
 143         .resume                 = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
 144 };
 145
 146 static void exynos_l2_write_sec(unsigned long val, unsigned reg)
 147 {
 148         static int l2cache_enabled;
 149
 150         switch (reg) {
 151         case L2X0_CTRL:
 152                 if (val & L2X0_CTRL_EN) {
 153                         /*
 154                          * Before the cache can be enabled, due to firmware
 155                          * design, SMC_CMD_L2X0INVALL must be called.
 156                          */
 157                         if (!l2cache_enabled) {
 158                                 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
 159                                 l2cache_enabled = 1;
 160                         }
 161                 } else {
 162                         l2cache_enabled = 0;
 163                 }
 164                 exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
 165                 break;
 166
 167         case L2X0_DEBUG_CTRL:
 168                 exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
 169                 break;
 170
 171         default:
 172                 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
 173         }
 174 }
 175
 176 static void exynos_l2_configure(const struct l2x0_regs *regs)
 177 {
 178         exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
 179                    regs->prefetch_ctrl);
 180         exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
 181 }
 182
 183 void __init exynos_firmware_init(void)
 184 {
 185         struct device_node *nd;
 186         const __be32 *addr;
 187
 188         nd = of_find_compatible_node(NULL, NULL,
 189                                         "samsung,secure-firmware");
 190         if (!nd)
 191                 return;
 192
 193         addr = of_get_address(nd, 0, NULL, NULL);
 194         if (!addr) {
 195                 pr_err("%s: No address specified.\n", __func__);
 196                 return;
 197         }
 198
 199         pr_info("Running under secure firmware.\n");
 200
 201         register_firmware_ops(&exynos_firmware_ops);
 202
 203         /*
 204          * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
 205          * running under secure firmware, require certain registers of L2
 206          * cache controller to be written in secure mode. Here .write_sec
 207          * callback is provided to perform necessary SMC calls.
 208          */
 209         if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
 210             read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 211                 outer_cache.write_sec = exynos_l2_write_sec;
 212                 outer_cache.configure = exynos_l2_configure;
 213         }
 214 }
 215
 216 #define REG_CPU_STATE_ADDR      (sysram_ns_base_addr + 0x28)
 217 #define BOOT_MODE_MASK          0x1f
 218
 219 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
 220 {
 221         unsigned int tmp;
 222
 223         tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
 224
 225         if (mode & BOOT_MODE_MASK)
 226                 tmp &= ~BOOT_MODE_MASK;
 227
 228         tmp |= mode;
 229         __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 230 }
 231
 232 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
 233 {
 234         unsigned int tmp;
 235
 236         tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
 237         tmp &= ~mode;
 238         __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 239 }