arch/arm/mach-imx/clk.h

   1 #ifndef __MACH_IMX_CLK_H
   2 #define __MACH_IMX_CLK_H
   3
   4 #include <linux/spinlock.h>
   5 #include <linux/clk-provider.h>
   6
   7 extern spinlock_t imx_ccm_lock;
   8
   9 void imx_check_clocks(struct clk *clks[], unsigned int count);
  10
  11 extern void imx_cscmr1_fixup(u32 *val);
  12
  13 struct clk *imx_clk_pllv1(const char *name, const char *parent,
  14                 void __iomem *base);
  15
  16 struct clk *imx_clk_pllv2(const char *name, const char *parent,
  17                 void __iomem *base);
  18
  19 enum imx_pllv3_type {
  20         IMX_PLLV3_GENERIC,
  21         IMX_PLLV3_SYS,
  22         IMX_PLLV3_USB,
  23         IMX_PLLV3_USB_VF610,
  24         IMX_PLLV3_AV,
  25         IMX_PLLV3_ENET,
  26 };
  27
  28 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  29                 const char *parent_name, void __iomem *base, u32 div_mask);
  30
  31 struct clk *clk_register_gate2(struct device *dev, const char *name,
  32                 const char *parent_name, unsigned long flags,
  33                 void __iomem *reg, u8 bit_idx,
  34                 u8 clk_gate_flags, spinlock_t *lock,
  35                 unsigned int *share_count);
  36
  37 struct clk * imx_obtain_fixed_clock(
  38                         const char *name, unsigned long rate);
  39
  40 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
  41          void __iomem *reg, u8 shift, u32 exclusive_mask);
  42
  43 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
  44                 void __iomem *reg, u8 shift)
  45 {
  46         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  47                         shift, 0, &imx_ccm_lock, NULL);
  48 }
  49
  50 static inline struct clk *imx_clk_gate2_shared(const char *name,
  51                 const char *parent, void __iomem *reg, u8 shift,
  52                 unsigned int *share_count)
  53 {
  54         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  55                         shift, 0, &imx_ccm_lock, share_count);
  56 }
  57
  58 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  59                 void __iomem *reg, u8 idx);
  60
  61 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
  62                                  void __iomem *reg, u8 shift, u8 width,
  63                                  void __iomem *busy_reg, u8 busy_shift);
  64
  65 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
  66                              u8 width, void __iomem *busy_reg, u8 busy_shift,
  67                              const char **parent_names, int num_parents);
  68
  69 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
  70                                   void __iomem *reg, u8 shift, u8 width,
  71                                   void (*fixup)(u32 *val));
  72
  73 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  74                               u8 shift, u8 width, const char **parents,
  75                               int num_parents, void (*fixup)(u32 *val));
  76
  77 static inline struct clk *imx_clk_fixed(const char *name, int rate)
  78 {
  79         return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
  80 }
  81
  82 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  83                 void __iomem *reg, u8 shift, u8 width)
  84 {
  85         return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  86                         reg, shift, width, 0, &imx_ccm_lock);
  87 }
  88
  89 static inline struct clk *imx_clk_divider_flags(const char *name,
  90                 const char *parent, void __iomem *reg, u8 shift, u8 width,
  91                 unsigned long flags)
  92 {
  93         return clk_register_divider(NULL, name, parent, flags,
  94                         reg, shift, width, 0, &imx_ccm_lock);
  95 }
  96
  97 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
  98                 void __iomem *reg, u8 shift)
  99 {
 100         return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 101                         shift, 0, &imx_ccm_lock);
 102 }
 103
 104 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
 105                 void __iomem *reg, u8 shift)
 106 {
 107         return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 108                         shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
 109 }
 110
 111 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 112                 u8 shift, u8 width, const char **parents, int num_parents)
 113 {
 114         return clk_register_mux(NULL, name, parents, num_parents,
 115                         CLK_SET_RATE_NO_REPARENT, reg, shift,
 116                         width, 0, &imx_ccm_lock);
 117 }
 118
 119 static inline struct clk *imx_clk_mux_flags(const char *name,
 120                 void __iomem *reg, u8 shift, u8 width, const char **parents,
 121                 int num_parents, unsigned long flags)
 122 {
 123         return clk_register_mux(NULL, name, parents, num_parents,
 124                         flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
 125                         &imx_ccm_lock);
 126 }
 127
 128 static inline struct clk *imx_clk_fixed_factor(const char *name,
 129                 const char *parent, unsigned int mult, unsigned int div)
 130 {
 131         return clk_register_fixed_factor(NULL, name, parent,
 132                         CLK_SET_RATE_PARENT, mult, div);
 133 }
 134
 135 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
 136                 struct clk *div, struct clk *mux, struct clk *pll,
 137                 struct clk *step);
 138
 139 #endif